KR101020297B1 - Word line driving circuit - Google Patents

Abstract

The word line driver circuit may include: a selection delay unit delaying the bank selection signal by a predetermined delay period in response to the test mode signal and transferring the bank selection signal as a low path enable signal; A driving signal generator configured to be driven in response to the low path enable signal to generate a word line driving signal; And a subword line signal driver configured to receive the word line driving signal and drive a subword line signal in response to a main word line signal.

Word line driver circuit, sub word line

Description

Word Line Driving Circuit {WORDLINE DRIVING CIRCUIT}

The present invention relates to a semiconductor memory device, and more particularly, to a word line driver circuit capable of reducing leakage current.

1 is a circuit diagram of a subword line driving circuit according to the prior art.

As shown in FIG. 1, the conventional subword line driving circuit includes a PMOS transistor P1 that pulls up the subword line signal SWL to the word line driving signal FX in response to the main word line signal MWLb. And the NMOS transistor N1 which pulls down the subword line signal SWL to the ground voltage Vss in response to the main word line signal MWLb, and the inverted signal FxB of the word line driving signal. An NMOS transistor N2 that pulls down the word line signal SWL to the ground voltage Vss.

The subword line driving circuit configured as described above has the subword line signal SWL when the main word line signal MWLb is selected and enabled at a low level while the selected word line driving signal FX is driven with the high voltage VPP. ) To the high voltage (VPP) level.

However, the main word line signal MWLb and the word line drive signal FX when the word line drive signal FX is selected in a state where the main word line signal MWLb is not selected in the conventional subword line driving circuit. Are all driven to a high voltage (VPP) level. At this time, as shown in FIG. 2, when the word line driving signal FX rises to the high voltage VPP level earlier than the main word line signal MWLb, the word line driving signal FX and the main word line signal MWLb are increased. ) May occur when the level difference is greater than or equal to the threshold voltage of the PMOS transistor P1. In this case, the NMOS N1 and the PMOS transistor P1 are turned on at the same time, so that a direct leakage current is generated from the word line driving signal FX to the ground voltage Vss.

The present invention discloses a word line driving circuit which provides a test mode that can slow down the driving period of a word line driving signal to reduce leakage current.

To this end, the present invention includes a selection delay unit for delaying the bank selection signal by a predetermined delay period in response to the test mode signal and transmitting the delayed bank selection signal as a low path enable signal; A driving signal generator configured to be driven in response to the low path enable signal to generate a word line driving signal; And a sub word line signal driver configured to receive the word line drive signal and drive a sub word line signal in response to a main word line signal.

In addition, the present invention includes a selection delay unit for delaying the bank selection signal by a predetermined delay period in response to the test mode signal and transmitting the delayed bank selection signal as a low path enable signal; A driving signal generator configured to be driven in response to the low path enable signal to generate a word line driving signal; A power selector configured to selectively transfer an external voltage or an internal voltage to an internal power source in response to the test mode signal and the enable signal; A main word line signal driver to generate a first main word line signal in response to the bank selection signal; A buffer unit configured to receive the internal power and buffer the first main word line signal to generate a second main word line signal; And a sub word line signal driver configured to receive the word line drive signal and drive a sub word line signal in response to a second main word line signal.

Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

3 is a block diagram illustrating a configuration of a word line driver circuit according to an exemplary embodiment of the present invention.

As shown in FIG. 3, the word line driver circuit according to the present embodiment includes a selection delay unit 1, a drive signal generator 2, a power selector 3, a main word line signal driver 4, and a buffer. And a sub word line signal driver 6.

As shown in FIG. 4, the selection delay unit 1 transmits the bank selection signal BS as the low path enable signal XDECEN in response to the test mode signal TMOFFB. The delay unit 10 delays the bank selection signal BS by a predetermined delay period, and the output signal of the delay unit 10 is transmitted as the low path enable signal XDECEN in response to the test mode signal TMOFFB. It is composed of a second transfer gate (T11). Here, the test mode signal TMOFFB is a signal applied at a low level to selectively drive the main word line signal to the high voltage VPP or the external voltage VDD, and the bank selection signal BS is a word line driving circuit. This signal is enabled at a high level when the included bank is selected.

When the test mode signal TMOFFB is applied at the high level, the selection delay unit 1 configured as described above transmits the bank selection signal BS as the low path enable signal XDECEN, and the test mode signal TMOFFB is When applied at the low level, the bank selection signal BS is delayed by the delay period of the delay unit 10 and then transferred as the low path enable signal XDECEN.

When the low path enable signal XDECEN is applied at a high level, the driving signal generator 2 selects a word line driving signal FxN for driving the subword line signal SWL to a high voltage VPP level. Drive. The driving signal generator 2 may be implemented as a general word line driving signal generating circuit including a decoder.

As shown in FIG. 5, the power selector 3 receives a test mode signal TMOFFB and an enable signal VPPCEN, and performs a logic logic operation to generate a turn-on signal ON. ), Between the PMOS transistor P30, which is turned on in response to the turn-on signal ON, and operates as a switch element for supplying the high voltage VPP to the internal power supply VPPC, between the external voltage VDD and the internal power supply VPPC. An NMOS transistor N30, which operates as a diode element connected to the transistor, is configured. The enable signal VPPCEN is a signal that is enabled at a high level when the first main word line signal MWLb1 is driven at a low level.

The main word line signal driver 4 generates the first main word line signal MWLb1 enabled at a low level when the bank selection signal BS having a high level is applied. The main word line signal driver 4 may be easily implemented as a decoder (not shown) that is driven by the bank selection signal BS to decode the low address to selectively enable the first main word line signal MWLb1. .

As shown in FIG. 6, the buffer unit 5 is connected between the internal power supply VPPC and the node nd50 to pull up and drive the node nd50 in response to the first main word line signal MWLb1. PMOS transistor P50, which operates as an element, is connected between node nd50 and ground voltage Vss, and operates as a pull-down element that pulls down node nd50 in response to the first main word line signal MWLb1. NMOS transistor N50 and inverter IV50 for inverting the signal of node nd50 to generate second main word line signal MWLb2.

As illustrated in FIG. 7, the subword line signal driver 6 is connected between the word line driving signal FxN and the node nd60 to which the subword line signal SWL is output, thereby providing a second main word line signal. The PMOS transistor P60, which operates as a pull-up device for pulling up the node nd60 in response to the MWLb2, is connected between the node nd60 and the ground voltage Vss to the second main word line signal MWbb2. NMOS transistor N60, which operates as a pull-down device that pulls-down node nd60 in response, is connected between node nd60 and ground voltage Vss and responds to the inversion signal FxNB of the word line driving signal. An NMOS transistor N61 that acts as a pull-down element for driving down nd60.

The operation of the word line driver circuit configured as described above is as follows.

First, when the test mode signal TMOFFB is applied at the low level and the bank selection signal BS is applied at the high level, the enable signal VPPCEN is enabled when the first main word line signal MWLb1 is enabled at the low level. Is enabled at a high level.

Next, the selection delay unit 1 generates the low path enable signal XDECEN by delaying the bank selection signal BS by the delay period of the delay unit 10, and the driving signal generation unit 2 generates the low path. The word line driving signal FxN is driven to the high voltage VPP level in the period where the enable signal XDECEN is applied to the high level. The word line drive signal FxN starts to be driven as late as the delay period of the delay unit 10 as compared with the prior art.

In addition, the power selector 3 receives the high voltage VPP by the low level turn-on signal ON generated by the low level test mode signal TMOFFB and the high level enable signal VPPCEN. VPPC). Accordingly, the buffer unit 5 receives the internal power supply VPPC to buffer the first main word line signal MWLb1 and generates the second main word line signal MWLb2.

Next, the subword line signal driver 6 receives the word line drive signal FXN and drives the subword line signal SWL in response to the second main word line signal MWLb2.

A characteristic of the word line driver circuit described above is a delay unit which delays the driving start section of the word line driver signal FxN when the second main word line signal MWLb2 is driven by an internal power supply VPPC having a high voltage VPP level. It is delayed as much as the delay section of 10). As a result, the word line driving signal FxN is selected while the second main word line signal MWLb2 is not selected, and thus the second main word line signal MWLb2 and the second main word line signal MWLb2 are selected. When both are driven to the high voltage VPP level, it is possible to prevent a case where the level difference between the word line driving signal FX and the main word line signal MWLb is greater than or equal to the threshold voltage of the PMOS transistor P60.

1 is a circuit diagram of a subword line driving circuit according to the prior art.

FIG. 2 is a diagram for describing an operation of a subword line driver circuit shown in FIG. 1.

3 is a block diagram illustrating a configuration of a word line driver circuit according to an exemplary embodiment of the present invention.

FIG. 4 is a circuit diagram of a selection delay unit included in the word line driver circuit shown in FIG. 3.

FIG. 5 is a circuit diagram of a power selector included in the word line driver circuit shown in FIG. 3.

6 is a circuit diagram of a buffer unit included in the word line driver circuit shown in FIG. 3.

FIG. 7 is a circuit diagram of a subword line signal driver included in the word line driver circuit shown in FIG. 3.

Claims (10)

A selection delay unit delaying the bank selection signal by a predetermined delay period in response to the test mode signal and transferring the bank selection signal as a low path enable signal; A driving signal generator configured to be driven in response to the low path enable signal to generate a word line driving signal; And And a sub word line signal driver configured to receive the word line drive signal and drive a sub word line signal in response to a main word line signal. The method of claim 1, wherein the selection delay unit A first transfer gate configured to transfer the bank selection signal as the low path enable signal in response to the test mode signal; A delay unit delaying the bank selection signal by the delay period; And And a second transfer gate configured to transfer the output signal of the delay unit as the low path enable signal in response to the test mode signal. The word line driver circuit of claim 1, wherein the driving signal generation unit selects and drives a word line driving signal when the row path enable signal is enabled. A selection delay unit delaying the bank selection signal by a predetermined delay period in response to the test mode signal and transferring the bank selection signal as a low path enable signal; A driving signal generator configured to be driven in response to the low path enable signal to generate a word line driving signal; A power selector configured to selectively transfer an external voltage or an internal voltage to an internal power source in response to the test mode signal and the enable signal; A main word line signal driver to generate a first main word line signal in response to the bank selection signal; A buffer unit configured to receive the internal power and buffer the first main word line signal to generate a second main word line signal; And And a sub word line signal driver configured to receive the word line drive signal and drive a sub word line signal in response to a second main word line signal. The method of claim 4, wherein the selection delay unit A first transfer gate configured to transfer the bank selection signal as the low path enable signal in response to the test mode signal; A delay unit delaying the bank selection signal by the delay period; And And a second transfer gate configured to transfer the output signal of the delay unit as the low path enable signal in response to the test mode signal. The word line driving circuit of claim 4, wherein the driving signal generator selects and drives a word line driving signal when the row path enable signal is enabled. The method of claim 4, wherein the power selector A turn-on signal generator for receiving the test mode signal and the enable signal and generating a turn-on signal; A switch device connected between the internal voltage and the internal power source and turned on in response to the turn-on signal; And And a diode device connected between the external voltage and the internal power supply. The word line driver circuit of claim 7, wherein the turn-on signal generator receives the test mode signal and the enable signal and performs a negative logic sum operation. The word line driver circuit of claim 4, wherein the internal voltage is formed at a level higher than the external voltage. The method of claim 4, wherein the buffer unit A pull-up element connected between the internal power source and the internal node to pull up the internal node in response to the first main word line signal; And And a pull-down element connected between the internal node and a ground voltage to pull down the internal node in response to the first main word line signal.

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