KR100991938B1 - Synchronous Phaser Measurement Modules, Devices, and Methods - Google Patents

Abstract

The present invention relates to a synchronous pager measurement module, apparatus and method for measuring the size and phase angle of a desired synchronous pager by compensating for the synchronous error when a synchronization error occurs between a reference signal and a sampling and hold control signal. will be.

Measurement, error, compensation, measuring device, sampling

Description

Synchronous Phaser Measurement Modules, Devices, and Methods {SYNCHRO-PHASOR MEASUREMENT MODULE, APPATATUS AND METHOD}

DETAILED DESCRIPTION The present invention relates to a synchronous pager measurement module, apparatus, and method installed in a PMU (Phasor Measurement Unit), a digital protective relay, a meter (METER), and the like to measure a synchronous pager and compensate for the synchronous error when a synchronous error occurs. It is about. A PMU (Phasor Measurement Unit), a digital protective relay, a meter, and the like distributed in various places may be equipped with a synchronous phaser measuring device according to the present invention. The central control center measures the value of the synchronous pager synchronized to the 1PPS (Pulse Per Second) signal of the GPS using the synchronous pager measuring device, and transmits the measured values of the synchronous pager to the central control center. Tide, stability, etc. can be analyzed.

Synchronous phasors are measured in Phasor Measurement Units (PMUs), digital protective relays, and meters (METERs) that are distributed in multiple locations. The central control center can compare the synchronous pagers measured at each location, or perform separate procedures to analyze the flow, stability, etc. of the entire power system to more clearly analyze whether there is a problem with the power system.

In order to measure the synchronous pager, a sample and hold control signal is synchronized with a 1PPS signal (signal as reference) generated by the GPS module. The sample and hold control signal is a signal for controlling to sample and hold the voltage signal input to the sample and hold unit.

However, a constant error occurs while the sample and hold control signal is synchronized with the 1PPS signal (signal as a reference) generated by the GPS module. That is, although the starting point of the 1PPS signal generated by the GPS module and the starting point of the sample and hold control signal are exactly matched, an error occurs due to an internal or external change factor.

The synchronous pager is a very sensitive measurement element, which shows a sensitive response to a very small error, and thus the value may vary greatly. Therefore, in order to solve this problem, various apparatuses and methods for compensating for errors have been used. Apparatus and methods for compensating for the error utilize hardware components and most have a feedback structure.

However, the error compensating process using the device has a problem of generating another error in the process of passing through various hardware components (consisting of analog circuits).

In addition, the feedback structure included in the apparatus has a problem of generating another error due to the time difference occurring during the feedback process.

In addition, the apparatus includes an analog circuit, which has a problem of generating another error as the characteristic changes depending on the surrounding environment such as temperature, load, and the like.

In addition, there is a problem that the parts and the total price of the error compensation devices are expensive.

In order to solve the above problems, an object of the present invention is to measure the error simply by using a digital circuit, and to compensate for the error using software without having to go through the process of compensating for the error through a complex analog circuit. To provide a synchronous pager measurement module, an apparatus and a method for measuring a synchronous pager while reducing another error that may occur in the process of compensating for the problem.

Another object of the present invention is to provide a synchronous pager measurement module, an apparatus, and a method capable of compensating for an error of a synchronous pager that can be implemented at low cost.

It is also an object of the present invention to provide a synchronous pager measurement module, apparatus and method that are less susceptible to external factors such as temperature and load.

Synchronous phaser measurement module according to the present invention, a timer for outputting a sample and hold control signal; When the rising or falling edge signal of GPS 1PPS (Pulse Per Second) signal is input, the counter value is increased every predetermined time, and the rising or falling edge signal of the sample and hold signal output from the timer is A counter for stopping the increase of the counter value and outputting the stopped counter value when inputted; and receiving the counter value output from the counter and multiplying the predetermined time by the counter value to obtain 1PPS (Pulse) of GPS. And a controller for calculating a synchronization error time between the Per Second) signal and the sample and hold signal, and compensating for an error in the synchronization phaser phase angle using the synchronization error time.

In addition, the controller uses the following equation in compensating for the error of the synchronous phaser phase angle by using the synchronous error time.

Øn = Ø'n-(w * e)

Where Øn is the phase angle of the synchronous phaser with error compensation, Ø'n is the phase angle of the synchronous phaser before error is compensated, w is the frequency of 1PPS (Pulse Per Second) signal and sample and hold ( sample and hold)

Compensating for the error of the synchronous phaser phase angle.

The control unit may control to input a signal for initializing the counter value to the counter when the phase angle compensation of the synchronous pager is completed.

In accordance with another aspect of the present invention, a synchronous phaser measuring device includes a timer for outputting a sample and hold control signal; A sample and hold unit repeatedly performing sampling and holding according to the sample and hold control signal, outputting a sampled value, and fixing a frequency of an input voltage signal; An analog-digital converter for converting the sampled value output from the sample-and-hold unit into a digital signal; When the rising or falling edge signal of GPS 1PPS (Pulse Per Second) signal is input, the counter value is increased every predetermined time, and the rising or falling edge signal of the sample and hold signal output from the timer is A counter for stopping the increase of the counter value and outputting the stopped counter value when inputted; and receiving the counter value output from the counter and multiplying the predetermined time by the counter value to obtain 1PPS (Pulse) of GPS. Calculates the synchronization error time between the Per Second) signal and the sample and hold signal, calculates the magnitude and phase angle of the synchronization phaser before compensation using the digital signals output from the analog-to-digital converter; And a controller for compensating for an error in the sync phaser phase angle before compensating using the sync error time.

In addition, the controller uses the following equation in compensating for the error of the synchronous phaser phase angle by using the synchronous error time.

Øn = Ø'n-(w * e)

Where Øn is the phase angle of the synchronous phaser with error compensation, Ø'n is the phase angle of the synchronous phaser before error is compensated, w is the frequency of 1PPS (Pulse Per Second) signal and sample and hold ( sample and hold)

Compensating for the error of the synchronous phaser phase angle.

The apparatus may further include a voltage transformer connected to the front end of the sample and hold unit and changing and outputting the magnitude of the input voltage.

The apparatus may further include an analog filter connected between the voltage transformer and the sample and hold part and configured to pass only a desired voltage among the voltages output from the voltage transformer.

The control unit may control to input a signal for initializing the counter value to the counter when the phase angle compensation of the synchronous pager is completed.

In the synchronous pager measuring method according to the present invention, when the counter receives a rising or falling edge signal of a 1PPS (Pulse Per Second) signal of GPS, the counter increments the counter value every predetermined time, and the sample and hold output from the timer. a first step of stopping the increase of the counter value and outputting the stopped count value when a rising and falling edge signal of a sample and hold control signal is input; A control unit receives the output counter value, and calculates a synchronization error time between a 1PPS (Pulse Per Second) signal and a sample and hold control signal by GPS by multiplying the predetermined time and the counter value. Two steps; A third step of the control unit initializing the first unit sample and hold waveform of the sample and hold control signal after the rising or falling edge of the 1PPS (Pulse Per Second) signal of the GPS is input; A fourth step of a sample and hold unit repeatedly performing sampling and holding according to the sample and hold control signal, outputting a sampled value, and fixing a frequency of an input voltage signal; A fifth step of receiving, by the analog-to-digital converter, the sampled value and converting the sampled value into a digital signal; A sixth step of the control unit calculating the size and phase angle of the synchronous pager before compensation using the digital signals output from the analog-digital converter; and the control unit compensating the synchronous pager phase angle before compensation using the synchronization error time. Thereby calculating a size and phase angle of the compensated sync phaser.

In addition, the eighth step of the control unit increases the order of the unit sample and hold waveform by 1; A ninth step of the control unit comparing the magnitude of the order of the increased unit sample and hold waveform with the magnitude of the total number of unit sample and hold waveforms; The control unit may further include a tenth step of executing a process after the fourth step only when the magnitude of the order of the increased unit sample and hold waveform is smaller than the magnitude of the total number of unit sample and hold waveforms. .

In addition, the seventh step,

Using the equation below

Øn = Ø'n-(w * e)

Where Øn is the phase angle of the synchronous phaser with error compensation, Ø'n is the phase angle of the synchronous phaser before error is compensated, w is the frequency of 1PPS (Pulse Per Second) signal and sample and hold ( sample and hold)

Compensating the synchronous phaser phase angle before compensation is characterized in that the size and phase angle of the compensated synchronous phaser is calculated.

The method may further include determining whether the synchronization error time exists after the first step. If the synchronization error time exists as a result of the determination, the controller executes the step after the second step. It is characterized by.

In addition, if there is no synchronization error time as a result of the determination, the controller executes only the fourth, fifth and sixth steps.

According to the present invention, an accurate synchronization phaser can be measured by compensating for a phase angle caused by a synchronization error.

In addition, there is an advantage that can reduce another error that can occur in the error compensation process through a simple error compensation process.

In addition, there is an advantage that the error compensation circuit is simplified.

In addition, there is an advantage that it is not affected by the surrounding environment such as temperature and load.

In addition, there is an advantage that the error compensation circuit can be implemented at a very low price.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of a synchronous pager measurement module, apparatus and method according to the present invention. The preferred embodiment is only for helping those skilled in the art among various possible examples, the technical spirit of the present invention is not necessarily limited or limited to the above embodiment.

1 is a block diagram of an embodiment of a synchronous pager measurement apparatus.

Referring to FIG. 1, the synchronous pager measuring apparatus includes a voltage transformer 10, an analog filter 15, a GPS module 20, a phase synchronization circuit (PLL), a sample and hold unit 35, and an analog digital conversion unit. 40 and the control part 45 are included.

The voltage transformer 10 changes the magnitude of the input voltage and outputs the changed voltage. For example, the input high voltage is changed to a low voltage capable of driving a circuit and output.

The analog filter 15 passes only a desired voltage among the voltages output from the voltage transformer 10. In this way, unnecessary harmonics that may occur in the process of voltage denaturation may be removed.

The GPS module 20 outputs a 1PPS (Pulse Per Second) signal that is output every second that is synchronized with universal time.

The phase locked loop (PLL) 30 outputs a sample and hold control signal synchronized with the 1PPS signal. The sample and hold control signal is a signal for controlling to fix the voltage signal output from the analog filter 15. The phase synchronization circuit PLL has a feedback structure, and the feedback structure can compensate for a synchronization error between the 1PPS signal and the sample and hold control signal.

The sample and hold unit 35 samples the input voltage signal during the sampling period of the sample and hold control signal output from the phase synchronization circuit (PLL) 30, and holds the sampled value during the holding period. And outputs the sampled value while holding. In the sampling section, the sample and hold control signal may be high, and in the holding section, the sample and hold control signal may be low or vice versa. In addition, the sample-and-hold unit 35 repeatedly performs sampling and hold, and then inputs the unit after the rising or falling edge of the 1PPS (Pulse Per Second) signal of GPS is input (or simultaneously). The frequency (time) of the voltage signal is fixed for each sample and hold waveform. The fixing process is to catch the shaking of the frequency. This makes it possible to more accurately carry out the process of measuring the synchronous pager by converting the analog signal (voltage signal) into a digital signal later through the analog-to-digital converter and performing DFT conversion.

The analog-to-digital converter 40 converts the sampled value output from the sample-and-hold unit 35 into a digital signal.

When the frequency is fixed, the control unit 45 is for each unit sample and hold waveform 230 inputted after (or at the same time) the rising or falling edge of the 1PPS (Pulse Per Second) signal of GPS is input. For each), the size and phase angle of the sync pager are calculated by performing a Discrete Fourier Transformation (DFT) operation using the digital signals output from the analog-to-digital converter 40. By doing the above, it is possible to calculate the size and phase angle of the desired synchronization phaser. The controller 45 transmits the size and phase angle of the sync pager to an external device. The external device may be the central control center described in FIG.

However, the phase synchronization circuit of the synchronous pager measurement apparatus has a feedback structure, causing a synchronization error between the 1PPS and the sample and hold control signal.

In addition, in order to output the sample and hold control signal using the 1PPS signal, the frequency must be multiplied at a very large rate by using a signal higher than 1Hz to 1920Hz (or 3840Hz). Therefore, a large multiplication ratio makes it difficult to design a high precision PLL.

In addition, since the phase synchronizing circuit PLL is composed of an analog circuit, there is a problem that the characteristics are sensitive to warming and the like and the characteristics vary greatly depending on the surrounding environment.

FIG. 2 is a diagram illustrating that a 1PPS (Pulse Per Second) signal of a GPS and a sample and hold control signal are accurately synchronized.

Referring to FIG. 2, the 1PPS signal 100 of the GPS is a 1HZ signal that is output once per second as a signal generated by the GPS module. In addition, the 1PPS signal is a signal including absolute time (phase) information that can be synchronized to universal time regardless of time and place. That is, when synchronizing to the 1PPS signal, it is possible to compare specific values by synchronizing according to an absolute time (1PPS) even between devices in remote locations.

The sample and hold control signal 110 is a signal for controlling the sample and hold unit so that a section for sampling and holding can be repeatedly executed. For example, when the sample and hold control signal 110 is a HIGH signal, the sampling and holding control signal 110 is a signal for controlling to hold the sampled value. In addition, when the sample and hold control signal 110 is a low signal, the sampling and holding may be performed when the sample and hold control signal 110 is a high signal. Although not accurately represented in FIG. 2, in general, the frequency of the voltage signal is 60 Hz, and the frequency of the sample and hold control signal is 1920 Hz. In this case, 32 samplings occur in one period of the voltage signal. In addition, the frequency of the voltage signal and the frequency of the sample and hold control signal may be variously modified.

The voltage signal 120 is sampled according to the sample and hold control signal 110. For example, when the sample and hold control signal 110 is a HIGH signal, the voltage signal 120 is sampled. When the sample and hold control signal 110 is a high signal, the sampled value of the voltage signal 120 is Is held. The sampled values are used to measure the size and phase angle of the sync pager.

The phase angle 130 of the synchronous pager refers to the first phase angle (hereinafter, referred to as Ø ₀ in FIG. 4) among several phase angles measured based on each sampled frequency (time). The phase angle 130 of the sync pager refers to the phase angle when there is no sync error, and the phase angle when there is a sync error will be described with reference to FIG. 3. The number of size and phase angles of the synchronous pagers will be the same as the number of samples.

It shows that the rising edge of the 1PPS signal and the rising edge of the sample and hold control signal are synchronized in synchronization. Alternatively, the falling edge of the 1PPS signal and the falling edge of the sample and hold control signal may be synchronized to match. In addition, it is possible to synchronize by various methods. As described above, accurate synchronization is achieved, and by using this to convert and measure the input voltage signal, it is possible to measure an accurate synchronization phaser. However, a problem occurs because accurate synchronization is not performed as described above, which will be described with reference to FIG. 3 below.

3 is a diagram illustrating a synchronization error between a 1PPS signal and a sample and hold control signal of a GPS.

Referring to FIG. 3, the sample and hold control signal 210 is a signal in which a unit sample and hold waveform 230 is repeatedly present. The unit sample and hold waveform 230 denotes a period in which a sampling section and a holding section occur once each. The total number of unit sample and hold waveforms 230 present within one cycle time of the 1PPS signal is represented by N. After the rising edge of the 1PPS signal 200 is input, n = 0 is applied to the unit sample and hold waveform 230 of the first sample and hold control signal 210. N is a sequence of unit sample and hold waveforms existing within one cycle time of the synchronized 1PPS signal in the sample and hold control signal (n = 0, 1, 2, 3, ..., N-1 ) Means. An initial process of applying n = 0 to the unit sample and hold waveform 230 of the first sample and hold control signal 210 is described. The initialized order n = 0 continues to increase until N-1.

The voltage signal 230 is sampled according to the sample and hold control signal 210. The voltage signal 230 is mainly used 60Hz. For example, when the sample and hold control signal 210 is a HIGH signal, the voltage signal 230 is sampled. When the sample and hold control signal 210 is a high signal, the sampled value of the voltage signal 230 is sampled. Is held. The sampled values are used to measure the size and phase angle of the sync pager.

The phase angle 240 of the synchronous pager means the first phase angle (Ø ' ₀ in FIG. 4 below) among the phase angles measured based on each sampled frequency (time). The phase angle 240 denotes a phase angle when there is a synchronization error. Referring to FIGS. 1 and 2, when the phase angle 130 of the synchronous phaser is compared with the phase angle 240 of the synchronous phaser, It can be seen that the phase angle 130 of the sync page, which was originally intended to be measured, is changed due to the occurrence of the sync error 220.

The synchronization error 220 may occur between the GPS 1PPS signal 200 and the sample and hold control signal 210 for various reasons. This synchronization error 220 results in an inaccurate value of the synchronization pager finally obtained. Therefore, accurate synchronization phase can be measured only when the synchronization error is compensated. The present invention relates to a synchronous pager measurement module, apparatus and method capable of compensating for the above error.

4 is a block diagram of a synchronous pager measurement module and apparatus related to an embodiment of the present invention.

Referring to FIG. 4, the synchronous pager measurement module includes a timer 340, a counter 350, and a controller 360. The synchronous pager measuring apparatus includes the synchronous pager measuring module, the voltage transformer 310, the analog filter 320, the sample and hold unit 370, the analog digital converter 380, and the GPS module 330.

The voltage transformer 310 changes the magnitude of the input voltage and outputs the changed voltage. For example, the input high voltage is changed to a low voltage capable of driving a circuit and output.

The analog filter 320 passes only a desired voltage among the voltages output from the voltage transformer 310. In this way, unnecessary harmonics that may occur in the process of voltage denaturation may be removed.

The GPS module 330 outputs a 1PPS (Pulse Per Second) signal that is output every second synchronized to the universal time.

The timer 340 is a sample and hold of N unit sample and hold waveform 230 is present during one cycle time of the 1PPS (Pulse Per Second) signal of the GPS generated by the GPS module 330 (sample and hold) hold) Outputs a control signal. For example, when one cycle time of the 1PPS (Pulse Per Second) signal of the GPS is 1 second, the timer 340 may generate a sample and hold (N) having N unit sample and hold waveforms 230 during the 1 second. sample and hold) control signal is output.

The counter 350 increases a counter value every predetermined time when a rising or falling edge signal of the 1PPS signal is input and a sample and hold signal output from the timer. When the rising or falling edge signal is inputted, the increase of the counter value is stopped. The counter 350 outputs the stopped counter value. The predetermined time may be 0.1 ms (one thousandth of a second), 0.5 ms second, 1 ms, 2 ms second, or the like.

The control unit 360 receives the counter value output from the counter 350 and multiplies the predetermined time by the counter value, thereby obtaining a pulse per second (PPS) signal and a sample and hold of GPS. Calculate the synchronization error time between signals. For example, when the predetermined time is 0.1 ms and the incremented counter value is 4, the synchronization error time is 0.4 ms.

The sample-and-hold unit 370 samples an input voltage signal during a sampling period of the sample-and-hold control signal output from the timer 340, and holds and holds a sampled value during the holding period. The sampled value is output. In the sampling section, the sample and hold control signal may be high, and in the holding section, the sample and hold control signal may be low or vice versa. After repeatedly performing sampling and holding, the rising or falling edge of the 1PPS (Pulse Per Second) signal of GPS is input (or at the same time), and the frequency (time) of the voltage signal for each input unit sample and hold waveform. ). The fixing process is to catch the shaking of the frequency. This makes it possible to more accurately carry out the process of measuring the synchronous pager by converting the analog signal (voltage signal) into a digital signal later through the analog-to-digital converter and performing DFT conversion.

The analog-to-digital converter 380 converts the sampled value output from the sample-and-hold unit 370 into a digital signal.

When the frequency is fixed, the control unit 360 receives the unit sample-and-hold waveform 230 input after (or at the same time) the rising or falling edge of the 1PPS (Pulse Per Second) signal of the GPS is input. Each phase) calculates the size and phase angle Øn of the synchronous pager before compensation by performing a Discrete Fourier Transformation (DFT) operation using the digital signals output from the analog-digital converter 380. The size and phase angle Øn of the synchronous pager before compensation is equal to N (the total number of unit sample and hold waveforms present within one cycle time of the synchronized 1PPS signal in the sample and hold control signal). exist. That is, the digital signal is applied to the unit sample-and-hold waveform 230 (when the frequency is fixed) after the rising or falling edge of the 1PPS (Pulse Per Second) signal of the GPS is input (or simultaneously). Since the Discrete Fourier Transformation (DFT) operation is performed using the signals, there are N sizes and phase angles Øn of the synchronous pager before compensation. In addition, the synchronous error time (e) calculated above is substituted into the following equation.

Øn = Ø'n-(w * e)

Øn: Phase angle of the synchronous phaser with error compensation

Ø'n: Phase angle of the sync phaser before the error is compensated

w: each frequency

e: Synchronous error time between 1PPS (Pulse Per Second) signal and sample and hold signal of GPS

n: Sequence of unit sample and hold waveforms existing within one cycle time of the synchronized 1PPS signal during the sample and hold control signal (n = 0, 1, 2, 3, ..., N-1)

By doing the above, the size and phase angle Øn of the compensated sync pager can be calculated.

For example, when the frequency is 1 Hz, the angular frequency is 2п = 2 * 3.14 = 6.28 (rad). If the phase angle Ø ' ₀ of the synchronous pager before compensation is 0.5973 (rad) and e is 0.4 ms, then Ø ₀ = 0.5973-6.28 * (0.0004) = 0.59479 (rad). Thus, the size of the compensated sync pager is equal to the size of the sync pager before being compensated, and the phase angle of the compensated sync pager is 0.59479 (rad). As above, the phase angles of the synchronous phaser before compensation (Ø ' ₀ , Ø' ₁ , Ø ' ₂ , Ø' ₃ , Ø ' ₄ , Ø' ₅ , ..., Ø'n) Is compensated through.

Hereinafter, a process of obtaining Equation 1 for measuring the phase angle of the compensated sync pager will be described.

The voltage output from the voltage transformer 310 is as follows.

v (t) = V * cos (w * t + Ø)

Where w is the angular frequency (e.g. 120п in the 60Hz system), V is the magnitude of the voltage, t is the time, and Ø is the phase angle.

If the synchronization error time is 0 (e = 0), the voltage expression is sampled according to the sample and hold control signal, and the Fourier Transformation (DFT) operation is performed using the sampled value, thereby the size of the synchronization pager. Calculate (V) and phase angle (Ø). The Discrete Fourier Transformation (DFT) operation is a well-known method that anyone skilled in the art may know.

The ideal case is when the synchronization error time is zero. The synchronous pager is a pager synchronized to a 1PPS (Pulse Per Second) signal of GPS, and always has phase information synchronized to universal time regardless of time and place.

If the sync error time is zero, the time t of the sample and hold control signal is

t = t1 + n / N

Where t1 is the time in seconds of 1 PPS and is an integer value (= 0, 1, 2, 3, ...)

n: Sequence of unit sample and hold waveforms existing within one cycle time of the synchronized 1PPS signal during the sample and hold control signal (n = 0, 1, 2, 3, ..., N-1)

N: Total number of sampled and held periodic signals present within one cycle time of the synchronized 1PPS signal during the sample and hold control signal

Referring to FIG. 2, the t1 value may be 0 seconds, 1 second, 2 seconds, ..., and the like, and 0 in FIG. 2. In addition, e is the synchronization error time 220, n is the order of each unit sample and hold waveforms, and N is the total number of periodic signals sampled and held.

Substituting Equation 3 into Equation 2,

v1 (t) = V * cos (w * t1 + w * n / N + Ø)

Here, t1 is an integer value in seconds at 1PPS, and thus is expressed as follows.

v1 (t) = V * cos (w * n / N + Ø)

Here, when performing a Fourth Transformation (DFT) operation, it can be seen that the size of the synchronization phaser when the synchronization error time is 0 (ideal) is V, and the phase angle Øn is w * n / N + Ø. .

On the other hand, if there is a sync error time (e occurs), the time t of the sample and hold control signal is

t = t1 + e + n / N

Where t1 is the time in seconds of 1 PPS and is an integer value (= 0, 1, 2, 3, ...)

n: Sequence of unit sample and hold waveforms existing within one cycle time of the synchronized 1PPS signal during the sample and hold control signal (n = 0, 1, 2, 3, ..., N-1)

N: Total number of sampled and held periodic signals present within one cycle time of the synchronized 1PPS signal during the sample and hold control signal

Referring to FIG. 2, the t1 value may be 0 seconds, 1 second, 2 seconds, ..., and the like, and 0 in FIG. 2. In addition, e is the synchronization error time 220, n is the order of each unit sample and hold waveforms, and N is the total number of periodic signals sampled and held.

Substituting Equation 5 into Equation 2,

v1 (t) = V * cos (w * t1 + w * e + w * n / N + Ø)

Here, t1 is an integer value in seconds at 1PPS, and thus is expressed as follows.

v1 (t) = V * cos (w * e + w * n / N + Ø)

Here, when the Discrete Fourier Transformation (DFT) operation is performed, the size of the synchronous phaser before compensation (with a synchronization error time) is V, and the phase angle Ø'n is w * e + w * n / N + It can be seen that

Comparing Equation 4 and Equation 6, the phase angle Øn of the compensated sync pager is expressed as in Equation 1 below.

Øn = Ø'n-(w * e)

It can be seen that. Therefore, by compensating for the change in the phase angle caused by the synchronization error time, it is possible to obtain the size and phase angle of the original sync pager.

As described above, according to the present invention, by compensating the phase angle by using a digital circuit and software, there is an advantage that can reduce another error that can occur in the complex error compensation process.

In addition, the circuit for compensating the phase angle is simple, there is an advantage that can be implemented at a very low price.

In addition, unlike the analog circuit, according to the present invention, there is an advantage that it is not affected by the surrounding environment such as temperature and load.

5 is a flowchart illustrating a synchronous pager measurement method according to an embodiment of the present invention.

Referring to FIG. 5, when a counter receives a rising or falling edge signal of a 1PPS (Pulse Per Second) signal of a GPS, the counter increases a counter value every predetermined time and outputs a sample and hold output from the timer. hold) When the rising or falling edge signal of the control signal is input, the increase of the counter value is stopped and the suspended count value is output (S400). The control unit receives the output counter value and multiplies the predetermined time by the counter value to synchronize the error time between a 1PPS (Pulse Per Second) signal of the GPS and a sample and hold control signal (e). To calculate (S410). The controller determines whether a synchronization error time exists (S420). If the synchronization error time does not exist, the sample and hold unit samples the input voltage signal during the sampling period of the sample and hold control signal, and holds the sampled value during the holding period. The sampled value is output. After repeatedly performing sampling and holding, the rising or falling edge of the 1PPS (Pulse Per Second) signal of GPS is input (or at the same time), and the frequency (time) of the voltage signal for each input unit sample and hold waveform. ). The analog-to-digital converter receives the sampled value and converts the sampled value into a digital signal. The analog is controlled by the control unit for each of the unit sample and hold waveforms 230 (when the frequency is fixed) input after (or at the same time) the rising or falling edge of the 1PPS (Pulse Per Second) signal of GPS is input. The size and phase angle of the sync pager are calculated by performing a Discrete Fourier Transformation (DFT) operation using the digital signals output from the digital converter 380 (S430). As described above, if there is no synchronization error time, the synchronization phase can be measured directly without going through a separate compensation process.

On the other hand, if it is determined in S420 that the synchronization error time is present as a result of the determination, after the controller inputs the rising or falling edge of the 1PPS (Pulse Per Second) signal of the GPS, the sample and hold (sample) and hold) initializes the first unit sample and hold waveform from the control signal (S440). That is, n = 0 is applied to the first unit sample and hold waveform in the sample and hold control signal. A sample and hold unit samples an input voltage signal during a sampling period of the sample and hold control signal, holds a sampled value during the holding period, and outputs the sampled value. After repeatedly performing sampling and holding, the rising or falling edge of the 1PPS (Pulse Per Second) signal of GPS is input (or at the same time), and the frequency (time) of the voltage signal for each input unit sample and hold waveform. ). A sampled value is output for each unit sample and hold waveform. The analog-to-digital converter receives the sampled value and converts the sampled value into a digital signal. The analog is controlled by the control unit for each of the unit sample and hold waveforms 230 (when the frequency is fixed) input after (or at the same time) the rising or falling edge of the 1PPS (Pulse Per Second) signal of GPS is input. The size and phase angle of the sync phaser before compensation are calculated by performing a Discrete Fourier Transformation (DFT) operation using the digital signals output from the digital converter 380 (S450).

The controller uses the following equation

Øn = Ø'n-(w * e)

Øn: Phase angle of the synchronous phaser with error compensation

Ø'n: Phase angle of the sync phaser before the error is compensated

w: each frequency

e: Synchronous error time between 1PPS (Pulse Per Second) signal and sample and hold signal of GPS

n: Sequence of unit sample and hold waveforms existing within one cycle time of the synchronized 1PPS signal during the sample and hold control signal (n = 0, 1, 2, 3, ..., N-1)

By doing the above, the size and phase angle Øn of the compensated sync pager can be calculated.

For example, when the frequency is 1 Hz, the angular frequency is 2п = 2 * 3.14 = 6.28 (rad). If the phase angle Ø ' ₀ of the synchronous pager before compensation is 0.5973 (rad) and e is 0.4 ms, then Ø ₀ = 0.5973-6.28 * (0.0004) = 0.59479 (rad). Thus, the size of the compensated sync pager is equal to the size of the sync pager before being compensated, and the phase angle of the compensated sync pager is 0.59479 (rad).

Through the values calculated in S450 and S460, the size and phase angle of the compensated sync pager are output (S470). The controller increases the order of the unit sample and hold waveform by 1 (S480). That is, the value of n is increased to the value of n + 1. The control unit compares the magnitude n of the order of the increased unit sample and hold waveforms with the magnitude N of the total number of unit sample and hold waveforms (S490). If the size n of the sequence of the unit sample and hold waveforms increased as a result of the determination is smaller than the size N of the total number of the unit sample and hold waveforms, the process is performed after S450.

On the other hand, when the size n of the order of the unit sample and hold waveforms increased as a result of the determination is greater than or equal to the size N of the total number of the unit sample and hold waveforms, execution ends.

For example, when a synchronization error time occurs, the synchronization error time is measured using a counter value. Assume that the synchronization error time is 3 seconds. Convert the sampled value from the first unit sample and hold waveform (n = 0) into a digital signal, and perform a DFT (Discrete Fourier Transformation) operation on the digital signal to control the size and phase angle of the synchronous pager before compensation. Ø n) Calculate. After calculating the phase angle to be compensated by substituting the equation (w * e) using the synchronization error time, the phase angle of the compensated sync phaser is substituted into the equation Øn = Ø'n− (w * e). Therefore, the size of the compensated sync pager is equal to the size of the sync pager before being compensated, and the phase angle of the compensated sync pager is Øn obtained above. Thereafter, the order n of the unit sample and hold waveforms is increased by one, and the magnitude n of the order of the increased unit sample and hold waveforms and the size N of the total number of unit sample and hold waveforms are increased. Compare.

If the magnitude n of the order of the increased unit sample and hold waveforms is smaller than the magnitude N of the total number of unit sample and hold waveforms, the second unit sample and hold waveform n = 1 is determined. The sampled value is converted into a digital signal, and the control unit calculates the size and phase angle Ø'n of the synchronous phaser before compensation by performing a discrete fourier transform (DFT) operation on the digital signal. The procedure thereafter is the same as described above. By repeating the above process (n = 0, 1, 2, 3, ..., N-1), the size and phase angle of the compensated sync pager can be calculated.

As described above, according to the present invention, the measurement of the synchronization error time is measured by using a circuit and the compensation of the phase angle is compensated by using software, so that the circuit is further simplified and physically compensated (in a complicated process of compensation). Another error such as an error occurring, an error from the feedback structure, an error due to temperature, etc.) can be greatly reduced.

6 is a block diagram of a system using a phasor measurement unit (PMU) equipped with a synchronous pager module and a device according to the present invention.

Referring to FIG. 6, the system according to the present invention includes a pager measuring device 500, a pager measuring device 510, a pager measuring device 520, and a central control center 530.

Each of the pager measuring device 500, the pager measuring device 510, and the pager measuring device 520 are equipped with a synchronous pager module and a device according to the present invention. Each of the pager measuring device 500, the pager measuring device 510, and the pager measuring device 520 measures the value of the synchronous pager synchronized to 1PPS of GPS, and measures the value of the measured synchronous pager in the central control center. 530). In addition to the pager measuring device, the synchronous pager module and the device according to the present invention may be mounted on a digital protective relay, a meter, or the like.

The central control center 530 may receive the measured value of the synchronous pager, and analyze the current, stability, etc. of the entire power system using the value of the received synchronous pager. As such, measuring the sync phaser is an important source of information about the status of the entire power system.

As described above, according to the present invention, it is possible to mount a synchronous pager module and a device having a simple and low-cost circuit while being less affected by external factors such as a pager measuring device. Therefore, even in configuring the overall system, it is possible to implement a system that is more inexpensive and has improved performance by using a pager measuring device having the above characteristics.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a block diagram of an embodiment of a synchronous pager measurement apparatus.

FIG. 2 is a diagram showing that a 1PPS (Pulse Per Second) signal of a GPS and a sample and hold control signal are correctly synchronized. FIG.

3 is a diagram illustrating a synchronization error between a 1PPS signal of a GPS and a sample and hold control signal;

4 is a block diagram of a synchronous pager measurement module and device in accordance with one embodiment of the present invention.

5 is a flow chart of a synchronous pager measurement method associated with one embodiment of the present invention.

6 is a block diagram of a system using a phasor measurement unit (PMU) equipped with a synchronous pager module and a device according to the present invention;

Claims (13)

A timer for outputting a sample and hold control signal; When the rising or falling edge signal of GPS 1PPS (Pulse Per Second) signal is input, the counter value is increased every predetermined time, and the rising or falling edge signal of the sample and hold signal output from the timer is A counter for stopping the increase of the counter value if it is input and outputting the stopped counter value; and Receiving a counter value output from the counter, and calculating a synchronization error time between a 1PPS (Pulse Per Second) signal and a sample and hold signal of GPS by multiplying the predetermined time and the counter value, And a controller for compensating for an error in the sync phaser phase angle by using the sync error time. The control unit, when the phase angle compensation of the synchronization phase is finished, the synchronous phaser measurement module, characterized in that the control to input a signal for initializing the counter value. The method of claim 1, The control unit, In compensating for the error of the synchronous phaser phase angle by using the synchronous error time, the following equation is used. Øn = Ø'n-(w * e) Where Øn is the phase angle of the synchronous phaser with error compensation, Ø'n is the phase angle of the synchronous phaser before error is compensated, and w is the frequency of 1PPS (Pulse Per Second) signal and sample and hold of GPS. Synchronous Error Time of the (sample and hold) Signal A synchronous phaser measurement module, characterized in that for compensating for errors in the phased phase angle. delete A timer for outputting a sample and hold control signal; A sample and hold unit repeatedly performing sampling and holding according to the sample and hold control signal, outputting a sampled value, and fixing a frequency of an input voltage signal; An analog-digital converter for converting the sampled value output from the sample-and-hold unit into a digital signal; When the rising or falling edge signal of GPS 1PPS (Pulse Per Second) signal is input, the counter value is increased every predetermined time, and the rising or falling edge signal of the sample and hold signal output from the timer is A counter for stopping the increase of the counter value if it is input and outputting the stopped counter value; and Receiving a counter value output from the counter, and calculating a synchronization error time between a 1PPS (Pulse Per Second) signal and a sample and hold signal of GPS by multiplying the predetermined time and the counter value, And a control unit for calculating the size and phase angle of the synchronous pager before compensation using the digital signals output from the analog-digital converter, and compensating for the error of the synchronous phaser phase angle before compensation using the synchronization error time. Synchronous phaser measurement device. The method of claim 4, wherein The control unit, In compensating for the error of the synchronous phaser phase angle by using the synchronous error time, the following equation is used. Øn = Ø'n-(w * e) Where Øn is the phase angle of the synchronous phaser with error compensation, Ø'n is the phase angle of the synchronous phaser before error is compensated, w is the frequency of 1PPS (Pulse Per Second) signal and sample and hold ( sample and hold) A synchronous phaser measuring device, characterized in that for compensating for errors in the phased phase of synchronous phases. The method of claim 4, wherein Is connected to the front end of the sample and hold, And a voltage transformer configured to change the magnitude of the input voltage and output the changed voltage. The method of claim 6, Connected between the voltage transformer and the sample and hold unit, The apparatus of claim 1, further comprising an analog filter for passing only a desired voltage among the voltages output from the voltage transformer. The method of claim 4, wherein The control unit, And when the phase angle compensation of the synchronous pager is completed, a signal for initializing the counter value is input to the counter. When the counter inputs the rising or falling edge signal of GPS 1PPS (Pulse Per Second) signal, the counter increases the counter value every predetermined time, and the rising and falling of the sample and hold control signal output from the timer or An output step of stopping the increase of the counter value when the falling edge signal is input and outputting the stopped counter value; The control unit receives the output counter value, and synchronizes the predetermined time and the counter value to calculate a synchronization error time between a 1PPS (Pulse Per Second) signal and a sample and hold control signal. Calculating an error time; An initialization step of the control unit initializing the first unit sample and hold waveform of the sample and hold control signal after the rising or falling edge of the 1PPS signal of the GPS is input; A sample and hold unit repeatedly performs sampling and holding according to the sample and hold control signal to output a sampling value of an input voltage signal, and is synchronized with the 1PPS (Pulse Per Second) signal of GPS. Sampling and frequency fixing step of fixing the frequency of the input voltage signal according to; A conversion step in which an analog-digital converter receives the sampled value and converts the sampled value into a digital signal; A step of calculating a synchronous phaser before compensation, wherein the control unit calculates a size and a phase angle of the synchronous phaser before being compensated using the digital signals output from the analog-to-digital converter; and And a compensated sync phaser calculating step of calculating, by the controller, the size and phase angle of the compensated sync pager by compensating for the sync pager phase angle before it is compensated using the sync error time. The method of claim 9, An order increasing step of the control unit increasing the order of the unit sample and hold waveform by 1; A comparison step of the control unit comparing the magnitude of the order of the increased unit sample and hold waveforms with the magnitude of the total number of unit sample and hold waveforms; And repeating the step of executing the sampling and frequency fixing step and subsequent steps only when the magnitude of the order of the increased unit sample and hold waveform is smaller than the magnitude of the total number of unit sample and hold waveforms. A synchronous phaser measurement method, characterized in that. The method of claim 9, The compensated sync phaser calculating step, Using the equation below Ø = Ø'n-(w * e) Where Øn is the phase angle of the synchronous phaser with error compensation, Ø'n is the phase angle of the synchronous phaser before error is compensated, w is the frequency of 1PPS (Pulse Per Second) signal and sample and hold ( sample and hold) Compensating the synchronous phaser phase angle before it is compensated for calculating the size and phase angle of the compensated synchronous phaser. The method of claim 9, After the synchronization error time calculation step, The control unit further includes a determination step of determining whether a synchronization error time exists, And if the synchronization error time exists as a result of the determination, the control unit executes the initializing step and the subsequent step. 13. The method of claim 12, And if the synchronization error time does not exist, the controller executes only the sampling and frequency fixing step, the conversion step, and the synchronous phaser calculation step before compensation.

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