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KR100971432B1 - Device Separating Method of Semiconductor Device - Google Patents

Device Separating Method of Semiconductor Device Download PDF

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KR100971432B1
KR100971432B1 KR1020030043118A KR20030043118A KR100971432B1 KR 100971432 B1 KR100971432 B1 KR 100971432B1 KR 1020030043118 A KR1020030043118 A KR 1020030043118A KR 20030043118 A KR20030043118 A KR 20030043118A KR 100971432 B1 KR100971432 B1 KR 100971432B1
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film
liner nitride
trench
forming
nitride film
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KR20050002071A (en
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장태식
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means

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  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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Abstract

본 발명은 셀영역의 리프레시 특성은 유지하면서 주변영역의 PMOS 트랜지스터의 특성열화를 방지할 수 있는 반도체 소자의 소자분리막 형성방법을 제공한다.The present invention provides a method of forming a device isolation film of a semiconductor device capable of preventing the deterioration of characteristics of the PMOS transistors in the peripheral region while maintaining the refresh characteristics of the cell region.

본 발명은 셀영역 및 주변영역이 구비된 반도체 기판 상에 하드 마스크를 형성하는 단계; 하드 마스크를 이용하여 기판을 식각하여 소정 깊이의 트렌치를 형성하는 단계; 트렌치 표면에 월산화막을 형성하는 단계; 월산화막 및 하드 마스크 표면에 라이너 질화막을 형성하는 단계; 라이너 질화막 상부에 유동성막을 증착하는 단계; 유동성막을 리플로우하여 셀영역의 트렌치에만 유동성막을 매립시키는 단계; 유동성막을 전면식각하여 하드 마스크 상의 라이너 질화막과 주변영역의 트렌치 저부의 라이너 질화막을 노출시키는 단계; 주변영역의 유동성막을 제거하는 단계; 셀영역의 유동성막을 식각 배리어로하여 주변영역의 라이너 질화막을 제거하는 단계; 및 셀영역의 유동성막을 제거하는 단계를 포함하는 반도체 소자의 소자분리막 형성방법에 의해 달성될 수 있다.
The present invention includes forming a hard mask on a semiconductor substrate having a cell region and a peripheral region; Etching the substrate using a hard mask to form a trench having a predetermined depth; Forming a monthly oxide film on the trench surface; Forming a liner nitride film on the monthly oxide film and the hard mask surface; Depositing a flowable film over the liner nitride film; Reflowing the fluidized film to fill the fluidized film only in the trench in the cell region; Etching the flowable film to expose the liner nitride film on the hard mask and the liner nitride film at the bottom of the trench in the peripheral region; Removing the fluidized film in the peripheral region; Removing the liner nitride film in the peripheral area by using the fluidized film in the cell area as an etch barrier; And removing the fluid film of the cell region.

STI, 전자포획, HDP 산화막, 라이너 질화막, BPSG막STI, electron trap, HDP oxide film, liner nitride film, BPSG film

Description

반도체 소자의 소자분리막 형성방법{METHOD OF FORMING ISOLATION LAYER FOR SEMICONDUCTOR DEVICE} METHODS OF FORMING ISOLATION LAYER FOR SEMICONDUCTOR DEVICE             

도 1a 및 도 1b는 종래의 반도체 소자의 소자분리막 형성방법을 설명하기 위한 단면도.1A and 1B are cross-sectional views illustrating a method of forming a device isolation film of a conventional semiconductor device.

도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위한 단면도.2A to 2F are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device in accordance with an embodiment of the present invention.

※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing

20 : 반도체 기판 21 : 패드 산화막20 semiconductor substrate 21 pad oxide film

22 : 패드 질화막 23 : 월산화막22: pad nitride film 23: monthly oxide film

24 : 라이너 질화막 25 : BPSG막24 liner nitride film 25 BPSG film

26 : HDP 산화막 200 : 하드 마스크
26: HDP oxide film 200: hard mask

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 STI(Sallow Trench Isolation) 공정을 적용한 반도체 소자의 소자분리막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming an isolation layer of a semiconductor device using a shallow trench isolation (STI) process.

반도체 소자의 고집적화에 따른 패턴의 미세화에 대응하기 위하여 기판에 얕은 깊이의 트렌치를 형성하고, 이 트렌치에 산화막을 매립시키는 STI 공정으로 소자분리막을 형성하고 있다. 또한, 최근에는 소자의 리프레시(refresh) 특성 향상을 위하여 STI 공정에 라이너(liner) 질화막을 적용하고 있다.In order to cope with the miniaturization of the pattern due to the high integration of the semiconductor device, a trench having a shallow depth is formed in the substrate, and the device isolation film is formed by an STI process in which an oxide film is embedded in the trench. In recent years, a liner nitride film has been applied to the STI process in order to improve the refresh characteristics of the device.

이러한 STI 공정을 적용한 종래의 반도체 소자의 소자분리막 형성방법을 도 1a 및 도 1b를 참조하여 설명한다.A device isolation film forming method of a conventional semiconductor device to which the STI process is applied will be described with reference to FIGS. 1A and 1B.

도 1a에 도시된 바와 같이, 반도체 기판(10) 상에 패드 산화막(11)과 패드 질화막(12)을 순차적으로 증착하고, 마스크 및 식각공정에 의해 패드 질화막(12)과 패드 산화막(11)을 패터닝하여 기판(10)의 일부를 노출시키는 하드 마스크(100)를 형성한다. 그 다음, 노출된 기판(10)을 식각하여 소정 깊이의 트렌치를 형성하고, 트렌치 표면에 월산화막(13)을 형성한다. 그 후, 월산화막(13) 및 하드 마스크(100) 표면에 라이너 질화막(14)을 증착한다.As shown in FIG. 1A, the pad oxide film 11 and the pad nitride film 12 are sequentially deposited on the semiconductor substrate 10, and the pad nitride film 12 and the pad oxide film 11 are deposited by a mask and etching process. Patterning to form a hard mask 100 to expose a portion of the substrate 10. Next, the exposed substrate 10 is etched to form trenches having a predetermined depth, and the oxide film 13 is formed on the trench surface. Thereafter, the liner nitride film 14 is deposited on the surface of the monthly oxide film 13 and the hard mask 100.

도 1b에 도시된 바와 같이, 트렌치에 매립되도록 라이너 질화막(14) 상부에 매립용 산화막으로서 고밀도 플라즈마(High Density Plasma; HDP) 산화막(15)을 증착한다. 그 후, 도시되지는 않았지만, 화학기계연마(Chemical Mechanical Polishing; CMP) 에 의해 하드 마스크(100)의 표면이 노출되도록 HDP 산화막(15)과 라이너 질화막(14)을 제거하여 소자분리막(16)을 형성하면서 기판 표면을 평탄화한 다음, 습식식각에 의해 하드 마스크(100)를 제거한다.As shown in FIG. 1B, a high density plasma (HDP) oxide film 15 is deposited as a buried oxide film on the liner nitride film 14 so as to be buried in the trench. Thereafter, although not shown, the device isolation film 16 is removed by removing the HDP oxide film 15 and the liner nitride film 14 so that the surface of the hard mask 100 is exposed by chemical mechanical polishing (CMP). While forming, the surface of the substrate is planarized, and then the hard mask 100 is removed by wet etching.

그러나, STI 공정에 라이너 질화막을 적용하게 되면 리프레시 특성은 향상되 는 반면, 주변영역(peripheral area)의 PMOS 트랜지스터에서는 라이너 질화막(14)에서의 핫전자포획(hot electron trap)으로 인하여 스트레스(stress) 인가 후 PMOS 트랜지스터의 오프-누설전류(off leakage current)가 증가하는 HEIP(Hot Electron Induced Punch-through) 특성열화가 야기되어 소자의 수율 및 신뢰성을 저하시키게 된다.
However, when the liner nitride film is applied to the STI process, the refresh characteristics are improved, while in the PMOS transistors in the peripheral area, stress is caused by hot electron traps in the liner nitride film 14. After application, hot electron induced punch-through (HEIP) characteristics are deteriorated, which increases the off-leakage current of the PMOS transistor, thereby lowering the yield and reliability of the device.

본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 셀영역의 리프레시 특성은 유지하면서 주변영역의 PMOS 트랜지스터의 특성열화를 방지할 수 있는 반도체 소자의 소자분리막 형성방법을 제공하는데 그 목적이 있다.
The present invention has been proposed to solve the above problems of the prior art, and provides a method of forming a device isolation film of a semiconductor device capable of preventing the deterioration of characteristics of the PMOS transistors in the peripheral region while maintaining the refresh characteristics of the cell region. There is a purpose.

상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 셀영역 및 주변영역이 구비된 반도체 기판 상에 하드 마스크를 형성하는 단계; 하드 마스크를 이용하여 기판을 식각하여 소정 깊이의 트렌치를 형성하는 단계; 트렌치 표면에 월산화막을 형성하는 단계; 월산화막 및 하드 마스크 표면에 라이너 질화막을 형성하는 단계; 라이너 질화막 상부에 유동성막을 형성하는 단계; 유동성막을 리플로우하여 셀영역의 트렌치에만 유동성막을 매립시키는 단계; 유동성막을 전면식각하여 하드 마스크 상의 라이너 질화막과 주변영역의 트렌치 저부의 라이너 질화막을 노출시키는 단계; 주변영역의 유동성막을 제거하는 단계; 셀영역의 유동성막을 식각 배리어로하여 주변영역의 라이너 질화막을 제거하는 단계; 및 셀영역의 유동성막을 제거하는 단계를 포함하는 반도체 소자의 소자분리막 형성방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, an object of the present invention comprises the steps of forming a hard mask on a semiconductor substrate having a cell region and a peripheral region; Etching the substrate using a hard mask to form a trench having a predetermined depth; Forming a monthly oxide film on the trench surface; Forming a liner nitride film on the monthly oxide film and the hard mask surface; Forming a flowable film on the liner nitride film; Reflowing the fluidized film to fill the fluidized film only in the trench in the cell region; Etching the flowable film to expose the liner nitride film on the hard mask and the liner nitride film at the bottom of the trench in the peripheral region; Removing the fluidized film in the peripheral region; Removing the liner nitride film in the peripheral area by using the fluidized film in the cell area as an etch barrier; And removing the fluid film of the cell region.

바람직하게, 유동성막은 BPSG막, SOG막 또는 포토레지스트막으로 300 내지 600Å의 두께로 형성하고, 유동성막의 제거는 HF를 이용한 습식식각으로 수행한다.Preferably, the flowable film is formed of a BPSG film, an SOG film, or a photoresist film with a thickness of 300 to 600 mm 3, and the removal of the fluidized film is performed by wet etching using HF.

또한, 라이너 질화막의 제거는 인산을 이용한 습식식각으로 수행한다.In addition, the removal of the liner nitride film is performed by wet etching with phosphoric acid.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

도 2a 및 도 2f는 본 발명의 실시예에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위한 단면도이다.2A and 2F are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to an embodiment of the present invention.

도 2a에 도시된 바와 같이, 셀영역 및 주변영역이 구비된 반도체 기판(20) 상에 패드 산화막(21)과 패드 질화막(22)을 순차적으로 증착하고, 마스크 및 식각공정에 의해 패드 질화막(22)과 패드 산화막(21)을 패터닝하여 기판(20)의 일부를 노출시키는 하드 마스크(200)를 형성한다. 그 다음, 노출된 기판(20)을 식각하여 소정 깊이의 트렌치를 형성하고, 트렌치 표면에 월산화막(23)을 형성한 후, 월산화막(23) 및 하드 마스크(200) 표면 에 소자의 리프레시 특성 향상을 위하여 라이너 질화막(24)을 증착한다.As shown in FIG. 2A, the pad oxide layer 21 and the pad nitride layer 22 are sequentially deposited on the semiconductor substrate 20 including the cell region and the peripheral region, and the pad nitride layer 22 is formed by a mask and an etching process. ) And the pad oxide film 21 are formed to form a hard mask 200 exposing a portion of the substrate 20. Next, the exposed substrate 20 is etched to form a trench having a predetermined depth, and a monthly oxide film 23 is formed on the trench surface, and then the refresh characteristics of the device are formed on the surfaces of the monthly oxide film 23 and the hard mask 200. Liner nitride film 24 is deposited for improvement.

도 2b에 도시된 바와 같이, 라이너 질화막(24) 상부에 유동성막으로서 BPSG 막(25)을 300 내지 600Å의 두께로 증착하고, 도 2c에 도시된 바와 같이, BPSG막(25)을 리플로우(reflow)하여 비교적 폭이 좁은 셀영역의 트렌치에만 BPSG막(25)을 매립시킨다. 여기서, BPSG막(25) 대신 SOG(Spin On Glass)막이나 포토레지스트막을 사용할 수도 있다.As shown in FIG. 2B, a BPSG film 25 is deposited to a thickness of 300 to 600 kPa as a flowable film on the liner nitride film 24, and as shown in FIG. 2C, the BPSG film 25 is reflowed. reflow) to fill the BPSG film 25 only in the trenches of the relatively narrow cell region. Here, a SOG (Spin On Glass) film or a photoresist film may be used instead of the BPSG film 25.

도 2d에 도시된 바와 같이, BPSG막(25)을 에치백(etch-back) 공정에 의해 전면식각하여 하드 마스크(200) 상의 라이너 질화막(24)을 노출시킴과 동시에 비교적 폭이 넓은 주변영역의 트렌치 저부의 라이너 질화막(24)을 노출시킨다. As shown in FIG. 2D, the BPSG film 25 is etched back by an etch-back process to expose the liner nitride film 24 on the hard mask 200 and at the same time a relatively wide peripheral region. The liner nitride film 24 at the bottom of the trench is exposed.

도 2e에 도시된 바와 같이, HF를 이용한 딥아웃(dip-out) 방식의 습식식각에 의해 주변영역 트렌치 측부의 BPSG막(25)을 제거하여 주변영역의 라이너 질화막(24)을 완전히 노출시킨 다음, 셀영역의 BPSG막(25)을 식각 배리어로하여 노출된 주변영역의 라이너 질화막(24)을 인산을 이용한 습식식각에 의해 제거한다.As shown in FIG. 2E, the liner nitride layer 24 of the peripheral region is completely exposed by removing the BPSG layer 25 on the peripheral trench side by dip-out wet etching using HF. Using the BPSG film 25 in the cell region as an etching barrier, the liner nitride film 24 in the exposed peripheral region is removed by wet etching using phosphoric acid.

도 2f에 도시된 바와 같이, 다시 HF를 이용한 딥-아웃 방식의 습식식각에 의해 셀영역의 BPSG막(25)도 완전히 제거하고 월산화 공정을 수행한 후, 트렌치에 매립되도록 기판 전면 상에 매립용 산화막으로서 HDP 산화막(26)을 증착한다. 그 다음, 도시되지는 않았지만, CMP 에 의해 하드 마스크(200)의 표면이 노출되도록 HDP 산화막(26)을 제거하여 형성하면서 기판 표면을 평탄화한 다음, 습식식각에 의해 하드 마스크(200)를 제거한다.As shown in FIG. 2F, the BPSG film 25 in the cell region is also completely removed by the wet-out wet etching method using HF, and the metallization process is performed on the front surface of the substrate to be embedded in the trench. The HDP oxide film 26 is deposited as the molten oxide film. Next, although not shown, the surface of the hard mask 200 is exposed by CMP to planarize the surface of the substrate while removing the HDP oxide layer 26, and then the hard mask 200 is removed by wet etching. .

상기 실시예에 의하면, BPSG막과 같은 유동성막을 이용하여 주변영역의 라이너 질화막만 용이하게 제거함으로써, 셀영역의 리프레시 특성은 유지하면서 주변영역 PMOS 트랜지스터에서 전자포획으로 인한 특성 열화를 방지할 수 있게 된다. According to the above embodiment, it is possible to easily remove only the liner nitride film in the peripheral area by using a fluid film such as a BPSG film, thereby preventing the deterioration of characteristics due to electron capture in the peripheral area PMOS transistor while maintaining the refresh characteristics of the cell area. .                     

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.
The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

전술한 본 발명은 STI 공정에 라이너 질화막을 적용하는 경우 주변영역의 라이너 질화막만을 용이하게 제거함으로써 셀영역의 리프레시 특성은 유지하면서 주변영역 PMOS 트랜지스터의 특성열화를 방지할 수 있으므로, 소자의 수율 및 신뢰성을 향상시킬 수 있다.According to the present invention, when the liner nitride film is applied to the STI process, only the liner nitride film in the peripheral region can be easily removed, thereby preventing deterioration of characteristics of the peripheral region PMOS transistor while maintaining the refresh characteristics of the cell region. Can improve.

Claims (5)

셀영역 및 주변영역이 구비된 반도체 기판 상에 하드 마스크를 형성하는 단계;Forming a hard mask on a semiconductor substrate having a cell region and a peripheral region; 상기 하드 마스크를 이용하여 상기 기판을 식각하여 소정 깊이의 트렌치를 형성하는 단계;Etching the substrate using the hard mask to form a trench having a predetermined depth; 상기 트렌치 표면에 월산화막을 형성하는 단계;Forming a monthly oxide film on the trench surface; 상기 월산화막 및 하드 마스크 표면에 라이너 질화막을 형성하는 단계;Forming a liner nitride film on the monthly oxide film and the hard mask surface; 상기 라이너 질화막 상부에 유동성막을 형성하는 단계;Forming a flowable film on the liner nitride film; 상기 유동성막을 리플로우하여 상기 셀영역의 트렌치에만 유동성막을 매립시키는 단계; Reflowing the fluidized film to fill the fluidized film only in the trench in the cell region; 상기 유동성막을 전면식각하여 상기 하드 마스크 상의 라이너 질화막과 상기 주변영역의 트렌치 저부의 라이너 질화막을 노출시키는 단계;Etching the flowable film to expose the liner nitride film on the hard mask and the liner nitride film at the bottom of the trench in the peripheral region; 상기 주변영역의 유동성막을 제거하는 단계;Removing the fluidized film in the peripheral region; 상기 셀영역의 유동성막을 식각 배리어로하여 상기 주변영역의 라이너 질화막을 제거하는 단계; 및 Removing the liner nitride film of the peripheral area by using the fluidized film of the cell area as an etch barrier; And 상기 셀영역의 유동성막을 제거하는 단계를 포함하는 반도체 소자의 소자분리막 형성방법.And removing the fluid film of the cell region. 제 1 항에 있어서, The method of claim 1, 상기 유동성막은 BPSG막, SOG막 또는 포토레지스트막인 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.And the flowable film is a BPSG film, an SOG film, or a photoresist film. 제 1 항 또는 제 2 항에 있어서, The method according to claim 1 or 2, 상기 유동성막은 300 내지 600Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The flowable film is a device isolation film forming method of a semiconductor device, characterized in that formed in a thickness of 300 to 600 내지. 제 1 항 또는 제 2 항에 있어서, The method according to claim 1 or 2, 상기 유동성막의 제거는 HF를 이용한 습식식각으로 수행하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The removal of the flow film is a device isolation film forming method of a semiconductor device, characterized in that the wet etching using HF. 제 1 항에 있어서, The method of claim 1, 상기 라이너 질화막의 제거는 인산을 이용한 습식식각으로 수행하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.And removing the liner nitride film by wet etching using phosphoric acid.
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