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KR100969153B1 - Nonvolatile Resistance Change Memory Device - Google Patents

Nonvolatile Resistance Change Memory Device Download PDF

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KR100969153B1
KR100969153B1 KR1020080033558A KR20080033558A KR100969153B1 KR 100969153 B1 KR100969153 B1 KR 100969153B1 KR 1020080033558 A KR1020080033558 A KR 1020080033558A KR 20080033558 A KR20080033558 A KR 20080033558A KR 100969153 B1 KR100969153 B1 KR 100969153B1
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lower electrode
resistance change
contact hole
memory device
change memory
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KR20090108238A (en
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황현상
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광주과학기술원
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20Multistable switching devices, e.g. memristors
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • H10D64/01334

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Abstract

균일한 스위칭 특성을 갖는 비휘발성 저항변화 메모리 소자가 개시되어 있다. 비휘발성 저항변화 메모리 소자는 하부전극, 하부전극 상에 형성되며, 콘택홀을 갖는 절연막, 콘택홀의 측벽 상에 형성된 절연 스페이서, 절연 스페이서가 형성된 콘택홀 내에 위치하는 산화물 저항막 및 산화물 저항막 상에 형성되는 상부전극을 포함한다. 따라서, 산화물 저항막과 하부전극 사이의 접촉 면적을 미세하게 한정함으로써 국부적인 곳에서 필라멘트가 형성되므로, 낮은 전계에서도 전도성 필라멘트를 형성 시킬 수 있으며, 유효 전류 밀도를 향상시킬 수 있다. A nonvolatile resistance change memory device having uniform switching characteristics is disclosed. The nonvolatile resistance change memory device is formed on a lower electrode and a lower electrode, and includes an insulating film having a contact hole, an insulating spacer formed on the sidewall of the contact hole, and an oxide resist film and an oxide resist film located in the contact hole where the insulating spacer is formed. It includes an upper electrode formed. Therefore, since the filament is formed locally by narrowly limiting the contact area between the oxide resistive film and the lower electrode, the conductive filament can be formed even at a low electric field, and the effective current density can be improved.

스위칭, 비휘발성 메모리, 저항변화메모리 Switching, non-volatile memory, resistance change memory

Description

비휘발성 저항변화 메모리 소자{Nonvolatile Resistance Random Access Memory Device}Nonvolatile Resistance Random Memory Device

본 발명은 비휘발성 메모리 소자에 관한 것으로 더욱 상세하게는 비휘발성 저항 변화 메모리 소자에 관한 것이다.The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile resistance change memory device.

1960년대부터 연구되어온 비휘발성 저항변화 메모리(ReRAM, Resistance Random Access Memory) 소자는 금속산화물을 이용한 MIM(Metal Insulator Metal) 구조로서, 적기적 신호를 가하였을 때 저항이 커서 전도가 되지 않는 상태에서 저항이 작아 전도가 가능한 상태로 바뀌는 메모리 스위칭 특징이 나타난다. Non-volatile resistance change memory (ReRAM) devices, which have been studied since the 1960s, are metal insulator metal (MIM) structures using metal oxides. This small memory-switching feature translates into a conductive state.

저항변화 메모리 소자는 접근시간(Acess Time)이 빠르며, 낮은 전압에서도 소자의 동작이 가능하기 때문에 전력소비가 작은 특징이 있다, 또한, 빠른 읽기 및 쓰기가 가능하며, 간단한 기억소자 구조를 갖기 때문에 공정상의 결함을 줄일 수 있어 생산단가를 낮출 수 있다. The resistance change memory device has fast access time and low power consumption because the device can be operated at low voltage. In addition, it can be quickly read and written and has a simple memory device structure. The defects of the phase can be reduced, and the production cost can be lowered.

그러나, 저항변화 메모리 소자는 필라멘트의 형성 및 끊어짐(ON/OFF)을 유도하여 소자를 동작시키는데, 종래의 비휘발성 저항변화 메모리의 경우, 소정 전계에서 단위 면적당 형성되는 필라멘트의 개수가 균일하지 않으며 반복적인 스위칭 동 작에서 서로 다른 필라멘트가 형성될 수 있어 기가/테라 비트급 메모리 장치 적용하기 어렵다.However, the resistance change memory device operates the device by inducing the formation and breaking of the filament (ON / OFF). In the conventional nonvolatile resistance change memory, the number of filaments formed per unit area in a predetermined electric field is not uniform and iterative. Different filaments can be formed during in-switching operation, making it difficult to apply giga / terabit memory devices.

상술한 문제점을 해결하기 위한 본 발명의 목적은 균일한 스위칭 특성을 갖는 비휘발성 저항 변화 메모리 소자를 제공하는데 있다.An object of the present invention for solving the above problems is to provide a nonvolatile resistance change memory device having a uniform switching characteristics.

상기 목적을 달성하기 위한 본 발명은 하부전극, 상기 하부전극 상에 형성되며, 콘택홀을 갖는 절연막, 상기 콘택홀의 측벽 상에 형성된 절연 스페이서, 상기 절연 스페이서가 형성된 콘택홀 내에 위치하는 산화물 저항막 및 상기 산화물 저항막 상에 형성되는 상부전극을 포함하는 비휘발성 저항변화 메모리 소자를 제공한다.The present invention for achieving the above object is formed on the lower electrode, the lower electrode, an insulating film having a contact hole, an insulating spacer formed on the sidewall of the contact hole, an oxide resist film located in the contact hole formed with the insulating spacer; A nonvolatile resistance change memory device including an upper electrode formed on the oxide resistive film is provided.

본 발명에 따르면, 산화물 저항막과 하부전극 사이의 접촉 면적을 미세하게 한정함으로써 국부적인 곳에서 필라멘트가 형성되므로, 낮은 전계에서도 전도성 필라멘트를 형성시킬 수 있으며, 유효 전류 밀도를 향상시킬 수 있다.  According to the present invention, since the filament is formed locally by restricting the contact area between the oxide resistive film and the lower electrode, the conductive filament can be formed even at a low electric field, and the effective current density can be improved.

또한, 전도성 필라멘트를 소수 개 형성함으로써 반복적인 스위칭 동작에서 같은 전도성 필라멘트를 형성 또는 소멸시킬 수 있으므로 안정적인 스위칭 특성을 구현할 수 있다.In addition, by forming a small number of conductive filaments can form or disappear the same conductive filament in a repetitive switching operation it is possible to implement a stable switching characteristics.

이하, 본 발명에 따른 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1e는 본 발명의 일 실시예에 따른 비휘발성 저항변화 메모리 소자의 제조공정을 나타내는 단면도들로서, 메모리 소자의 단위 셀에 한정되어 도시한다.1A to 1E are cross-sectional views illustrating a manufacturing process of a nonvolatile resistance change memory device according to an exemplary embodiment of the present invention, and are shown in a limited form in a unit cell of the memory device.

도 1a를 참조하면, 하부 전극(110)이 제공된다. 상기 하부전극(110)은 Ti, Cu, Ni, Pt, Ru, Ir 또는 Al 막일 수 있다. Referring to FIG. 1A, a lower electrode 110 is provided. The lower electrode 110 may be a Ti, Cu, Ni, Pt, Ru, Ir, or Al film.

도 1b를 참조하면, 상기 하부전극(110) 상에 콘택홀(125)을 갖는 절연막(120)을 형성한다. 상기 절연막(120)은 SiO2일 수 있다. 상기 콘택홀(125)의 너비는 약 50nm 이하로 형성할 수 있다. Referring to FIG. 1B, an insulating film 120 having a contact hole 125 is formed on the lower electrode 110. The insulating layer 120 may be SiO 2 . The contact hole 125 may have a width of about 50 nm or less.

상기 콘택홀(125)이 형성된 기판 상에 스페이서 절연막(130)을 형성한다. The spacer insulating layer 130 is formed on the substrate on which the contact hole 125 is formed.

상기 스페이서 절연막(130)은 실리콘 질화막일 수 있으며, 원자층 증착법(ALD, Atomic Layer Deposition)을 이용하여 균일한 두께를 갖도록 콘포말(conformal)하게 형성할 수 있다. The spacer insulating layer 130 may be a silicon nitride layer, and may be conformally formed to have a uniform thickness by using atomic layer deposition (ALD).

도 1c를 참조하면, 상기 스페이서 절연막(130)을 이방성 식각(anisotropic etch)하여 상기 콘택홀(125)의 측벽 상에 절연 스페이서(131)를 형성한다. 상기 절연 스페이서(131)가 형성된 콘택홀(125) 내에 상기 하부 전극(110)이 노출될 수 있다. 상기 노출된 하부 전극(110)의 폭은 약 1nm 내지 약 10nm일 수 있다.Referring to FIG. 1C, the spacer insulating layer 130 is anisotropically etched to form an insulating spacer 131 on sidewalls of the contact hole 125. The lower electrode 110 may be exposed in the contact hole 125 where the insulating spacer 131 is formed. The exposed lower electrode 110 may have a width of about 1 nm to about 10 nm.

도 1d를 참조하면, 상기 절연 스페이서(131)가 형성된 콘택홀(125) 내에 산 화물 저항막(140)을 형성한다. 상기 산화물 저항막(140)은 전이금속산화막일 수 있다. 구체적으로, TiO2 -X, Al2O3 -X, NiO1 -X, Nb2O5 -X, Ta2O5 -X, ZrO2 -X, Cu0X, Fe2O3 -X 등과 같은 이성분계 산화물을 산소공공(oxygen vacancy)이 있는 비화학양론적(non-stoichiometric) 조성으로 제조하여 저항 변화 물질로 이용할 수 있다. 일 예로서, X는 0.01-0.5 일 수 있다.Referring to FIG. 1D, an oxide resist film 140 is formed in the contact hole 125 in which the insulating spacer 131 is formed. The oxide resistance layer 140 may be a transition metal oxide layer. Specifically, such as TiO 2 -X , Al 2 O 3 -X , NiO 1 -X , Nb 2 O 5 -X , Ta 2 O 5 -X , ZrO 2 -X , Cu0 X , Fe 2 O 3 -X and the like Binary oxides can be prepared in a non-stoichiometric composition with oxygen vacancy and used as a resistance change material. As an example, X may be 0.01-0.5.

상기 산화물 저항막(140)의 두께는 상기 절연막(120)의 두께에 비해 작을 수 있다. 구체적으로, 상기 산화물 저항막(140)의 두께는 상기 2nm 내지 50nm일 수 있다.The thickness of the oxide resistance layer 140 may be smaller than the thickness of the insulating layer 120. Specifically, the thickness of the oxide resistance layer 140 may be 2nm to 50nm.

상기 산화물 저항막(140)은 스퍼터링(Sputtering), 펄스레이저 증착법 (PLD, Pulsed Laser Deposition), 증발법(Thermal Evaporation), 전자빔 증발법(Electron-beam Evaporation) 등과 같은 물리기상증착법(PVD, Physical Vapor Deposition), 분자선 에피탁시 증착법(MBE, Molecular Beam Epitaxy), 또는 화학기상증착법(CVD, Chemical Vapor Deposition)을 사용하여 형성할 수 있다. 이 경우에, 상기 절연 스페이서(131)가 형성된 콘택홀(125)을 완전히 채우도록 산화물막을 형성한 후, 상기 산화물막을 화학기계적 연마(CMP) 및 에치백(etchback)함으로써, 상기 산화물 저항막(140)을 형성할 수 있다.The oxide resist film 140 may be formed by physical vapor deposition (PVD), such as sputtering, pulsed laser deposition (PLD), thermal evaporation, and electron-beam evaporation. Deposition), Molecular Beam Epitaxy (MBE), or Chemical Vapor Deposition (CVD). In this case, after the oxide film is formed to completely fill the contact hole 125 where the insulating spacer 131 is formed, the oxide resist film 140 is formed by chemical mechanical polishing (CMP) and etchback. ) Can be formed.

이와는 달리, 상기 산화물 저항막(140)은 상기 노출된 하부전극(110)을 산화하여 형성할 수 있다. 이 경우에, 상기 산화물 저항막(140)의 두께를 용이하게 조절할 수 있으며, 상기 하부 전극(110)은 Ti 막, Cu 막 또는 Ni 막일 수 있다. Unlike this, the oxide resistance layer 140 may be formed by oxidizing the exposed lower electrode 110. In this case, the thickness of the oxide resistive film 140 may be easily adjusted, and the lower electrode 110 may be a Ti film, a Cu film, or a Ni film.

도 1e를 참조하면, 상기 산화물 저항막(140) 상에 상부전극(150)을 형성한다. Referring to FIG. 1E, an upper electrode 150 is formed on the oxide resistance layer 140.

상기 상부전극(150)은 Pt, W, Mo, Ti, Cu, Ni, Ru, Ir 또는 Al 막일 수 있으며, 증착 또는 리소그라피를 통한 식각을 이용할 수 있다. The upper electrode 150 may be a Pt, W, Mo, Ti, Cu, Ni, Ru, Ir, or Al film, and may use etching through deposition or lithography.

상기와 같이 형성된 비휘발성 저항변화 메모리 소자는 절연 스페이서(131)가 형성된 콘택홀(125) 내에 산화물 저항막(140)을 형성함으로서, 상기 산화물 저항막(140)과 상기 하부 전극 사이의 접촉 면적을 미세하게 한정할 수 있다. 이 경우에, 상기 하부 전극과 국부적으로 접촉하는 상기 산화물 저항막 내에 유효 전류 밀도(effective current density)가 증가하므로 낮은 전계에서도 전도성 필라멘트가 쉽게 형성될 수 있다. In the nonvolatile resistance change memory device formed as described above, the oxide resistance layer 140 is formed in the contact hole 125 where the insulating spacer 131 is formed, thereby reducing the contact area between the oxide resistance layer 140 and the lower electrode. It can be narrowly defined. In this case, since the effective current density increases in the oxide resistive film in local contact with the lower electrode, the conductive filament can be easily formed even at a low electric field.

또한, 상기 산화물 저항막(140)과 상기 하부 전극(110) 사이의 미세한 접촉 면적으로 인해, 형성되는 전도성 필라멘트가 소수 개, 바람직하게는 하나에 한정될 수 있다. 따라서, 반복적인 스위칭 동작에서 같은 전도성 필라멘트가 형성 또는 소멸되므로, 안정적인 스위칭 특성을 구현할 수 있다.In addition, due to the minute contact area between the oxide resistance layer 140 and the lower electrode 110, the number of conductive filaments to be formed may be limited to one, preferably one. Therefore, since the same conductive filaments are formed or disappeared in the repetitive switching operation, stable switching characteristics can be realized.

이를 위해, 상술한 바와 같이 상기 절연 스페이서(131)가 형성된 콘택홀(125) 내에 노출된 하부 전극(110)의 폭은 약 10nm 이하일 수 있다.To this end, as described above, the width of the lower electrode 110 exposed in the contact hole 125 in which the insulating spacer 131 is formed may be about 10 nm or less.

도 2는 저항의 누적분포를 나타낸 그래프이다. 구체적으로, 스위칭을 반복적으로 진행할 때의 저항의 누적분포를 나타낸다.2 is a graph showing the cumulative distribution of resistances. Specifically, the cumulative distribution of the resistance when the switching is repeatedly performed is shown.

도 2를 참조하면, 산화물 저항막에 전계가 형성되면, 필라멘트가 형성되어 전류가 흐르는데, 이러한 영역을 LRS(low resistance state)라 하며, 반대로, 어느 정도 이상의 높은 전계가 형성되어 과전류로 인해 필라멘트가 끊어져, 줄열 가열(Joule heating)의 원리가 적용되는 영역을 HRS(high resistance state)라 한다.Referring to FIG. 2, when an electric field is formed in the oxide resistive film, a filament is formed and a current flows. Such a region is referred to as a low resistance state (LRS). Cut off, the area to which the principle of Joule heating is applied is called a high resistance state (HRS).

종래 소자는 스위칭을 반복적으로 진행할 때 LRS 및 HRS가 넓은 범위에 분포하고 있어, LRS와 HRS 사이를 구분할 수 있는 특정 저항치를 얻기 어려웠다. 그러나, 본 발명에 따른 메모리 소자는 스위칭을 반복적으로 진행하는 경우에도 LRS와 HRS가 각각 좁은 범위에 분포하므로, LRS와 HRS 사이를 구분할 수 있는 저항치(△R)의 범위가 매우 넓다.In the conventional device, when the switching is repeatedly performed, the LRS and the HRS are distributed in a wide range, and it is difficult to obtain a specific resistance value that can be distinguished between the LRS and the HRS. However, in the memory device according to the present invention, since the LRS and the HRS are distributed in a narrow range even when the switching is repeatedly performed, the resistance value ΔR that can distinguish between the LRS and the HRS is very wide.

본 발명의 일 실시예에서는 국부적인 영역에 필라멘트를 형성시킴으로써 반복적인 스위칭에도 저항이 광범위하게 분산되지 않고, 균일하게 형성될 수 있으며, 안정적인 스위칭 특성을 나타낼 수 있다. In an embodiment of the present invention, by forming a filament in a local region, resistance may not be widely distributed even after repeated switching, and may be uniformly formed, and exhibit stable switching characteristics.

이상, 예를 참조하여 설명하였지만, 해당 기술 분양의 숙련된 당업자는 하기의 특허청구범위에 기재된 본 고안의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 고안을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다. Although described above with reference to examples, those skilled in the art can understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. There will be.

도 1a 내지 도 1e는 본 발명의 일 실시예에 따른 비휘발성 저항변화 메모리 소자의 제조공정을 나타내는 단면도들이다. 1A to 1E are cross-sectional views illustrating a manufacturing process of a nonvolatile resistance change memory device according to an exemplary embodiment of the present invention.

도 2는 저항의 누적분포를 나타낸 그래프이다. 2 is a graph showing the cumulative distribution of resistances.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>

110: 하부전극 120: 절연막110: lower electrode 120: insulating film

125: 콘택홀 130: 스페이서 절연막125: contact hole 130: spacer insulating film

131: 절연 스페이서 140: 산화물 저항막131: insulating spacer 140: oxide resistive film

150: 상부전극150: upper electrode

Claims (7)

삭제delete 삭제delete 삭제delete 삭제delete 하부 전극 상에 절연막을 형성하는 단계; Forming an insulating film on the lower electrode; 상기 절연막 내에 상기 하부 전극의 일부를 노출시키는 콘택홀을 형성하는 단계; Forming a contact hole in the insulating layer to expose a portion of the lower electrode; 상기 콘택홀이 형성된 상기 절연막 상에 스페이서 절연막을 형성하는 단계; Forming a spacer insulating film on the insulating film on which the contact hole is formed; 상기 스페이서 절연막을 식각하여 상기 콘택홀의 측벽 상에 상기 하부 전극의 일부를 노출시키는 절연 스페이서를 형성하는 단계; Etching the spacer insulating layer to form an insulating spacer exposing a portion of the lower electrode on the sidewall of the contact hole; 상기 절연 스페이서에 의하여 노출된 상기 하부 전극을 산화시켜 산화물 저항막을 형성하는 단계; 및 Oxidizing the lower electrode exposed by the insulating spacer to form an oxide resistive film; And 상기 산화물 저항막 상에 상부 전극을 형성하는 단계;를 포함하는 저항변화 메모리 소자의 제조 방법. Forming an upper electrode on the oxide resistive film. 제 5항에 있어서, The method of claim 5, 상기 절연 스페이서에 의하여 노출되는 하부 전극의 폭은 1㎚ 내지 10㎚인 저항변화 메모리 소자의 제조 방법. The width of the lower electrode exposed by the insulating spacer is a manufacturing method of the resistance change memory device 1nm to 10nm. 제 5항에 있어서, The method of claim 5, 상기 하부 전극은 Ti, Cu 및 Ni로 이루어지는 군에서 선택되는 어느 하나인 저항변화 메모리 소자의 제조 방법. And the lower electrode is any one selected from the group consisting of Ti, Cu, and Ni.
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