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KR100967924B1 - A method of manufacturing a semiconductor device, an apparatus for manufacturing a semiconductor device, and a program storage medium - Google Patents

A method of manufacturing a semiconductor device, an apparatus for manufacturing a semiconductor device, and a program storage medium Download PDF

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KR100967924B1
KR100967924B1 KR1020080056158A KR20080056158A KR100967924B1 KR 100967924 B1 KR100967924 B1 KR 100967924B1 KR 1020080056158 A KR1020080056158 A KR 1020080056158A KR 20080056158 A KR20080056158 A KR 20080056158A KR 100967924 B1 KR100967924 B1 KR 100967924B1
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KR20090032938A (en
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코이치 야츠다
에이이치 니시무라
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도쿄엘렉트론가부시키가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask

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Abstract

(과제) 종래에 비하여 공정의 간략화와 제조 비용의 저감을 도모할 수 있어, 생산성의 향상을 도모할 수 있는 반도체 장치의 제조 방법, 반도체 장치의 제조 장치, 제어 프로그램 및, 프로그램 기억 매체를 제공한다.(Problem) Provided are a semiconductor device manufacturing method, a semiconductor device manufacturing apparatus, a control program, and a program storage medium, which can simplify the process and reduce the manufacturing cost, and can improve productivity, as compared with the related art. .

(해결 수단) 포토레지스트(103)의 패턴의 위에 SiO2막(104)을 성막하는 성막 공정과, SiO2막(104)을 포토레지스트(103)의 패턴의 측벽부에만 남도록 에칭하는 에칭 공정과, 포토레지스트(103)의 패턴을 제거하여 SiO2막(104)의 패턴을 형성하는 공정을 구비하고 있다.[MEANS FOR SOLVING PROBLEMS] film-forming step and the etching step of etching to remain only on the side wall of the pattern of the photoresist 103, the SiO 2 film 104 for forming the SiO 2 film 104 on the pattern of the photoresist 103 and the And removing the pattern of the photoresist 103 to form the pattern of the SiO 2 film 104.

반도체 장치, 성막, 에칭  Semiconductor device, film formation, etching

Description

반도체 장치의 제조 방법, 반도체 장치의 제조 장치 및, 프로그램 기억 매체 {METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS, DEVICE FOR MANUFACTURING SEMICONDUCTOR APPARATUS, AND STORAGE MEDIUM FOR PROGRAM}Method for manufacturing semiconductor device, apparatus for manufacturing semiconductor device, and program storage medium {METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS, DEVICE FOR MANUFACTURING SEMICONDUCTOR APPARATUS, AND STORAGE MEDIUM FOR PROGRAM}

본 발명은, 포토레지스트(photoresist)막을 노광, 현상하여 얻어진 포토레지스트의 제1 패턴에 기초하여, 기판 상의 피(被)에칭층을 소정의 패턴으로 에칭하여, 반도체 장치를 제조하는 반도체 장치의 제조 방법, 반도체 장치의 제조 장치, 제어 프로그램 및, 프로그램 기억 매체에 관한 것이다.The present invention manufactures a semiconductor device which manufactures a semiconductor device by etching a target etching layer on a substrate in a predetermined pattern based on a first pattern of a photoresist obtained by exposing and developing a photoresist film. A method, a manufacturing apparatus of a semiconductor device, a control program, and a program storage medium.

종래부터, 반도체 장치 등의 제조 공정에 있어서는, 반도체 웨이퍼 등의 기판에 플라즈마 에칭 등의 에칭 처리를 행하여, 미세한 회로 패턴 등을 형성하는 것이 행해지고 있다. 이러한 에칭 처리 공정에서는, 포토레지스트를 이용한 포토리소그래피(photolithography) 공정에 의해, 에칭 마스크를 형성하는 것이 행해지고 있다.Background Art Conventionally, in a manufacturing process such as a semiconductor device, etching treatment such as plasma etching is performed on a substrate such as a semiconductor wafer to form a fine circuit pattern or the like. In such an etching process, forming an etching mask is performed by the photolithography process using a photoresist.

이러한 포토리소그래피 공정에서는, 형성하는 패턴의 미세화에 대응하기 위해, 여러 종류의 기술이 개발되고 있다. 그 하나로서, 소위 더블 패터닝(double patterning)이 있다. 이 더블 패터닝은, 제1 마스크 패턴 형성 스텝과, 이 제1 마 스크 패턴 형성 스텝의 후에 행해지는 제2 마스크 패턴 형성 스텝의 2단계의 패터닝을 행함으로써, 1회의 패터닝으로 에칭 마스크를 형성하는 경우보다 미세한 간격의 에칭 마스크를 형성할 수 있도록 한 것이다(예를 들면, 특허 문헌 1 참조).In such a photolithography step, various kinds of techniques have been developed to cope with miniaturization of a pattern to be formed. One example is so-called double patterning. This double patterning is performed when the etching mask is formed by one patterning by performing two-step patterning of the first mask pattern forming step and the second mask pattern forming step performed after the first mask pattern forming step. It is made to form the etching mask of finer space | interval (for example, refer patent document 1).

또한, 예를 들면 SiO2막이나 Si3N4막 등을 희생막으로서 사용하고, 1개의 패턴의 양측 측벽 부분에 마스크를 형성하여 사용하는 SWT(side wall transfer)법을 이용하여, 최초로 포토레지스트막을 노광, 현상하여 얻어진 포토레지스트의 패턴보다도 미세한 피치(pitch)로 패터닝을 행하는 것도 알려져 있다. 즉, 이 방법에서는, 우선 포토레지스트의 패턴을 이용하여, 예를 들면 SiO2막의 희생막을 에칭하여 패터닝하고, 이 SiO2막의 패턴의 위에 Si3N4막 등을 형성한 후, SiO2막의 측벽 부분에만 Si3N4막이 남도록 에치백(etch back)하고, 이 이후, 웨트 에칭(wet etching)에 의해 SiO2막을 제거하고, 남은 Si3N4막을 마스크로 하여, 하층의 에칭을 행하는 것이다.For example, a photoresist is first used using a side wall transfer (SWT) method in which a SiO 2 film, a Si 3 N 4 film, or the like is used as a sacrificial film, and a mask is formed on both sidewall portions of one pattern. It is also known to pattern at a finer pitch than the pattern of the photoresist obtained by exposing and developing a film. That is, in this method, first, by using a photo resist pattern is, for example, after a SiO 2 film, etching the sacrificial film is patterned to form a like Si 3 N 4 film on top of the SiO 2 film pattern, SiO 2 film side wall The Si 3 N 4 film is etched back so that only the portion remains, and after that, the SiO 2 film is removed by wet etching, and the underlying layer is etched using the remaining Si 3 N 4 film as a mask.

또한, 성막 기술에 있어서는, 보다 저온에서 성막하는 것이 요구되는 경우가 있으며, 이와 같이 저온에서 성막하는 기술로서는, 가열 촉매체로 성막 가스를 활성화시킨 화학기상성장(chemical vapor deposition)에 의해 행하는 방법이 알려져 있다(예를 들면, 특허 문헌 2 참조).In the film forming technique, it is sometimes required to form a film at a lower temperature. As a technique for forming a film at a lower temperature in this manner, a method of performing the chemical vapor deposition by activating the film forming gas with a heating catalyst body is known. (For example, refer patent document 2).

[특허 문헌 1] 일본공개특허공보 2007-027742호[Patent Document 1] Japanese Patent Application Laid-Open No. 2007-027742

[특허 문헌 2] 일본공개특허공보 2006-179819호[Patent Document 2] Japanese Laid-Open Patent Publication No. 2006-179819

상기한 바와 같이, 종래 기술에 있어서는, 공정수가 많아지고, 공정이 복잡화함과 아울러 제조 비용이 증대하여, 생산성이 악화한다는 과제가 있다. 또한, 종래의 SWT법에서는, 웨트 에칭 공정이 필요하기 때문에, 드라이 에칭(dry etching)과 웨트 에칭이 혼재하는 공정이 되어, 공정이 번잡화하는 요인이 되고 있다.As described above, in the prior art, there is a problem that the number of steps increases, the complexity of the steps increases, the manufacturing cost increases, and the productivity deteriorates. In addition, in the conventional SWT method, since a wet etching process is required, it becomes a process in which dry etching and wet etching are mixed, resulting in a complicated process.

본 발명은, 이러한 종래의 사정에 대처하여 이루어진 것으로, 종래에 비하여 공정의 간략화와 제조 비용의 저감을 도모할 수 있어, 생산성의 향상을 도모할 수 있는 반도체 장치의 제조 방법, 반도체 장치의 제조 장치, 제어 프로그램 및, 프로그램 기억 매체를 제공하려는 것이다.This invention is made in response to such a conventional situation, Comprising: The manufacturing method of the semiconductor device which can aim at the simplification of a process and reduction of a manufacturing cost, and can improve productivity compared with the conventional, The manufacturing apparatus of a semiconductor device It is intended to provide a control program and a program storage medium.

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청구항 7의 반도체 장치의 제조 방법은, 기판 상의 피에칭층을 소정의 패턴으로 에칭하여, 반도체 장치를 제조하는 반도체 장치의 제조 방법으로서, 포토레지스트로 이루어지는 복수의 라인 형상의 제1 패턴을 형성하는 제1 패턴 형성 공정과, 상기 제1 패턴의 위에 SiO2막을 성막하는 제1 성막 공정과, 상기 SiO2막을 상기 포토레지스트의 제1 패턴의 측벽부에만 남도록 에칭하는 제1 에칭 공정과, 상기 제1 패턴을 제거하여 상기 SiO2막의 제2 패턴을 형성하는 제2 패턴 형성 공정과, 상기 제2 패턴을 마스크로 하여 하층의 제1 마스크 구성층을 에칭하는 제2 에칭 공정과, 상기 제1 패턴과 직교하는 방향으로, 포토레지스트의 복수의 라인 형상의 패턴으로 이루어지는 제3 패턴을 형성하는 공정과, 상기 제3 패턴의 위에 SiO2막을 성막하는 제2 성막 공정과, 상기 SiO2막을 상기 제3 패턴의 측벽부에만 남도록 에칭하는 제3 에칭 공정과, 상기 제3 패턴을 제거하여 상기 SiO2막의 제4 패턴을 형성하는 제4 패턴 형성 공정과, 상기 제4 패턴 및 상기 제1 마스크 구성층을 마스크로 하여, 하층의 제2 마스크 구성층을 에칭하는 제4 에칭 공정과, 상기 제1 마스크 구성층과 상기 제2 마스크 구성층을 마스크로 하여, 상기 피에칭층에 홀 형상을 형성하는 제5 에칭 공정을 구비한 것을 특징으로 한다.The manufacturing method of the semiconductor device of Claim 7 is a manufacturing method of the semiconductor device which manufactures a semiconductor device by etching the etching target layer on a board | substrate in a predetermined pattern, Comprising: Forming the several line-shaped 1st pattern which consists of photoresists. a first pattern formation step, the first film-forming step of forming SiO 2 film on the first pattern, and a first etching step of the SiO 2 film is etched to remain only on the side wall of the first pattern of the photoresist, the first A second pattern forming step of removing one pattern to form a second pattern of the SiO 2 film, a second etching step of etching a first mask constituent layer below using the second pattern as a mask, and the first pattern Forming a third pattern comprising a plurality of line-shaped patterns of photoresist in a direction orthogonal to the second; forming a second SiO 2 film on the third pattern; and Group the third etching step, wherein the first and fourth pattern forming step of forming the SiO 2 film, a fourth pattern by removing the third pattern and the fourth pattern and etching to leave only the side wall portion of the third pattern SiO 2 film A fourth etching step of etching the lower layer second mask component layer using the first mask component layer as a mask, and the etching target layer using the first mask component layer and the second mask component layer as a mask. A fifth etching step of forming a hole shape is provided.

청구항 8의 반도체 장치의 제조 방법은, 청구항 7에 기재된 반도체 장치의 제조 방법으로서, 상기 제1 및 제2 성막 공정을, 가열 촉매체로 성막 가스를 활성화시킨 화학기상성장에 의해 행하는 것을 특징으로 한다.The manufacturing method of the semiconductor device of Claim 8 is a manufacturing method of the semiconductor device of Claim 7, The said 1st and 2nd film-forming process is performed by chemical vapor growth which activated the film-forming gas with the heating catalyst body.

청구항 9의 반도체 장치의 제조 방법은, 청구항 7 또는 8에 기재된 반도체 장치의 제조 방법으로서, 상기 제1 성막 공정의 전에, 상기 제1 패턴을 트리밍함과 아울러, 하층의 유기 재료로 이루어지는 반사 방지막을 에칭하는 공정과, 상기 제1 성막 공정의 전에, 상기 제3 패턴을 트리밍함과 아울러, 하층의 유기 재료로 이루어지는 반사 방지막을 에칭하는 공정을 구비한 것을 특징으로 한다.The manufacturing method of the semiconductor device of Claim 9 is a manufacturing method of the semiconductor device of Claim 7 or 8, Comprising: The anti-reflective film which consists of an organic material of a lower layer while trimming the said 1st pattern before the said 1st film-forming process. And a step of etching the antireflection film made of an organic material of the lower layer while trimming the third pattern before the first film forming step and the first film forming step.

청구항 10의 반도체 장치의 제조 방법은, 청구항 7 내지 9 중 어느 한 항에 기재된 반도체 장치의 제조 방법으로서, 상기 제1 마스크 구성층이 실리콘으로 이루어지고, 상기 제2 마스크 구성층이 질화실리콘으로 이루어지는 것을 특징으로 한다.The manufacturing method of the semiconductor device of Claim 10 is a manufacturing method of the semiconductor device of any one of Claims 7-9, Comprising: The said 1st mask structure layer consists of silicon, and The said 2nd mask structure layer consists of silicon nitride. It is characterized by.

청구항 11의 반도체 장치의 제조 장치는, 기판 상의 피에칭층을 소정의 패턴으로 에칭하여, 반도체 장치를 제조하는 반도체 장치의 제조 장치로서, 상기 기판을 수용하는 처리 챔버와, 상기 처리 챔버 내에 처리 가스를 공급하는 처리 가스 공급 수단과, 상기 처리 챔버 내에서 청구항 7 내지 청구항 10 중 어느 한 항에 기재된 반도체 장치의 제조 방법이 행해지도록 제어하는 제어부를 구비한 것을 특징으로 한다.The manufacturing apparatus of the semiconductor device of Claim 11 is a manufacturing apparatus of the semiconductor device which manufactures a semiconductor device by etching the etching target layer on a board | substrate in a predetermined pattern, Comprising: The processing chamber which accommodates the said board | substrate, and a processing gas in the said processing chamber. It is provided with the processing gas supply means which supplies the process, and the control part which controls so that the manufacturing method of the semiconductor device of any one of Claims 7-10 may be performed in the said processing chamber.

제어 프로그램은, 컴퓨터 상에서 동작하고, 실행 시에, 청구항 7 내지 청구항 10 중 어느 한 항에 기재된 반도체 장치의 제조 방법이 행해지도록 반도체 장치의 제조 장치를 제어하는 것을 특징으로 한다.The control program operates on a computer and, when executed, controls the manufacturing apparatus of the semiconductor device so that the manufacturing method of the semiconductor device according to any one of claims 7 to 10 is performed.

청구항 12의 프로그램 기억 매체는, 컴퓨터 상에서 동작하는 제어 프로그램이 기억된 프로그램 기억 매체로서, 상기 제어 프로그램은, 실행 시에 청구항 7 내지 청구항 10 중 어느 한 항에 기재된 반도체 장치의 제조 방법이 행해지도록 반도체 장치의 제조 장치를 제어하는 것을 특징으로 한다.The program storage medium of claim 12 is a program storage medium in which a control program operating on a computer is stored, wherein the control program is a semiconductor such that the method of manufacturing a semiconductor device according to any one of claims 7 to 10 is performed at the time of execution. It is characterized by controlling the manufacturing apparatus of the apparatus.

본 발명에 의하면, 종래에 비하여 공정의 간략화와 제조 비용의 저감을 도모할 수 있어, 생산성의 향상을 도모할 수 있는 반도체 장치의 제조 방법, 반도체 장치의 제조 장치, 제어 프로그램 및, 프로그램 기억 매체를 제공할 수 있다.Advantageous Effects According to the present invention, a semiconductor device manufacturing method, a semiconductor device manufacturing apparatus, a control program, and a program storage medium, which can simplify the process and reduce the manufacturing cost, and can improve the productivity as compared with the prior art. Can provide.

(발명을 실시하기 위한 최량의 형태)Best Mode for Carrying Out the Invention [

이하, 본 발명의 일 실시 형태에 대하여 도면을 참조하여 설명한다.EMBODIMENT OF THE INVENTION Hereinafter, one Embodiment of this invention is described with reference to drawings.

도1 은, 본 발명의 제1 실시 형태에 따른 반도체 웨이퍼의 일부를 확대하여 개략적으로 나타내는, 제1 실시 형태에 따른 반도체 장치의 제조 방법의 공정을 나타내는 것이다. 도1(a) 에 나타내는 바와 같이, 이 제1 실시 형태에서는, 패터닝을 목적으로 하는 피에칭층으로서의 폴리실리콘층(101)의 위에는, 유기 재료로 이루어지는 반사 방지막(BARC)(102)이 형성되어 있으며, 이 반사 방지막(BARC)(102)의 위에 포토레지스트(103)가 형성되어 있다. 포토레지스트(103)는, 노광, 현상 공정에 의해, 패터닝되어, 소정의 형상을 갖는 패턴으로 되어 있다. 또한, 도1 에 있어서 부호(100)는, 폴리실리콘층(101)의 하측에 형성된 하지(base)층을 나타내고 있다.1 shows a step of a method of manufacturing a semiconductor device according to the first embodiment, in which a part of the semiconductor wafer according to the first embodiment of the present invention is enlarged and schematically shown. As shown in Fig. 1 (a), in this first embodiment, an antireflection film (BARC) 102 made of an organic material is formed on the polysilicon layer 101 as the etching target layer for the purpose of patterning. The photoresist 103 is formed on the antireflection film BARC 102. The photoresist 103 is patterned by exposure and development processes to form a pattern having a predetermined shape. In addition, in FIG. 1, the code | symbol 100 has shown the base layer formed under the polysilicon layer 101. As shown in FIG.

도1(b) 는, 상기의 포토레지스트(103)를 트리밍(trimming)하여 선폭을 좁게 함과 아울러, 반사 방지막(BARC)(102)을 에칭한 상태를 나타내고 있다. 이 포토레 지스트(103)의 트리밍 및 반사 방지막(BARC)(102)의 에칭을 행하는 공정은, 예를 들면, 산소 플라즈마 등을 이용한 플라즈마 에칭에 의해 행할 수 있다.FIG. 1B shows a state in which the photoresist 103 is trimmed to narrow the line width and the anti-reflection film BARC 102 is etched. The process of trimming the photoresist 103 and etching the antireflection film (BARC) 102 can be performed by plasma etching using oxygen plasma or the like, for example.

다음으로, 도1(c) 에 나타내는 바와 같이, SiO2막(104)을 성막한다. 이 성막 공정에서는, 포토레지스트(103)의 위에 성막을 행하지만, 일반적으로 포토레지스트(103)는, 고온에 노출되면 쓰러짐이 발생하는 등, 고온에 약하기 때문에, 저온(예를 들면 300℃ 이하 정도)에서 성막하는 것이 바람직하다. 이 경우, 가열 촉매체로 성막 가스를 활성화시킨 화학기상성장에 의해 행할 수 있다.Next, as shown in Fig. 1C, a SiO 2 film 104 is formed. In this film forming step, the film is formed on the photoresist 103. Generally, since the photoresist 103 is weak to high temperature, such as collapse when exposed to high temperature, it is low temperature (for example, about 300 ° C. or less). Film formation is preferred. In this case, it can be performed by chemical vapor growth which activated the film-forming gas with a heating catalyst body.

다음으로, 도1(d) 에 나타내는 바와 같이, SiO2막(104)을 에칭하여, SiO2막(104)이, 포토레지스트(103)의 패턴의 측벽부에만 남은 상태로 한다. 이 에칭은, 예를 들면, CF4, C4F8, CHF3, CH3F, CH2F2 등의 CF계 가스와, Ar 가스 등의 혼합 가스, 또는 이 혼합 가스에 필요에 따라 산소를 첨가한 가스 등을 이용하여 행할 수 있다.Next, as shown in Fig. 1 (d), the SiO 2 film 104 is etched so that the SiO 2 film 104 remains only in the sidewall portions of the pattern of the photoresist 103. This etching is performed by, for example, CF-based gases such as CF 4 , C 4 F 8 , CHF 3 , CH 3 F, and CH 2 F 2 , mixed gas such as Ar gas, or oxygen in the mixed gas as necessary. It can be performed using a gas or the like added.

다음으로, 도1(e) 에 나타내는 바와 같이, 산소 플라즈마를 이용한 애싱(ashing) 등에 의해, 포토레지스트(103)의 패턴을 제거하여, 측벽부에 남은 SiO2막(104)에 의한 패턴을 형성한다.Next, as shown in Fig. 1E, the pattern of the photoresist 103 is removed by ashing or the like using oxygen plasma to form a pattern by the SiO 2 film 104 remaining in the sidewall portion. do.

그리고, 도1(f) 에 나타내는 바와 같이, 상기의 SiO2막(104)에 의한 패턴을 마스크로 하여, 하층의 폴리실리콘층(101)을 에칭한다. 이 에칭은, 예를 들면, HBr 가스 등을 이용하여 행할 수 있다.As shown in Fig. 1 (f), the polysilicon layer 101 of the lower layer is etched using the pattern of the SiO 2 film 104 as a mask. This etching can be performed using HBr gas etc., for example.

상기의 제1 실시 형태에서는, 희생막을 이용하는 일이 없이, SWT법에 의한 미세한 패턴의 형성을 행할 수 있다. 또한, 공정의 도중에 웨트 에칭을 행하는 일이 없이, 에칭 공정은 모두 드라이 에칭 공정에 의해 실시할 수 있다. 따라서, 종래에 비하여 공정의 간략화와 제조 비용의 저감을 도모할 수 있어, 생산성의 향상을 도모할 수 있다.In said 1st Embodiment, the fine pattern by SWT method can be formed, without using a sacrificial film. In addition, all the etching processes can be performed by a dry etching process, without performing wet etching in the middle of a process. Therefore, compared with the conventional method, the process can be simplified and the manufacturing cost can be reduced, and the productivity can be improved.

실제로, 도1(c) 에 나타내는 공정에서 가열 촉매체로 성막 가스를 활성화시킨 화학기상성장에 의해 두께 약 35nm의 SiO2막(104)을 성막하고, 대향 전극의 상부 전극과 하부 전극에 고주파 전력을 공급하여 플라즈마 에칭을 행하는 장치를 이용하여, 이하의 조건으로 각 공정의 에칭을 행한 결과, 폴리실리콘층(101)(두께 약 100nm(하지층이 산화막))을 양호한 형상으로 패터닝할 수 있었다.In fact, in the process shown in Fig. 1C, a SiO 2 film 104 having a thickness of about 35 nm is formed by chemical vapor growth by activating the deposition gas with a heating catalyst body, and high frequency power is applied to the upper and lower electrodes of the counter electrode. As a result of etching each process under the following conditions using an apparatus for supplying and performing plasma etching, the polysilicon layer 101 (thickness of about 100 nm (base layer is an oxide film)) was patterned in a good shape.

(도1(b), (e) 의 포토레지스트(103), 반사 방지막(102)의 에칭)(Etching of the photoresist 103 and the anti-reflection film 102 of Figs. 1B and 1E)

에칭 가스 : O2 (374sccm)Etching Gas: O 2 (374sccm)

압력 : 13.3Pa (100mTorr)Pressure: 13.3Pa (100mTorr)

전력 : 600W (상부) / 30W (하부)Power: 600W (top) / 30W (bottom)

(도1(d) 의 SiO2막(104)의 에칭)(Etching of SiO 2 Film 104 in Fig. 1 (d))

에칭 가스 : Ar/C4F8 (500sccm/20sccm)Etching Gas: Ar / C 4 F 8 (500sccm / 20sccm)

압력 : 5.3Pa (40mTorr)Pressure: 5.3Pa (40mTorr)

전력 : 600W (상부) / 100W (하부)Power: 600W (top) / 100W (bottom)

(도1(f) 의 폴리실리콘층(101)의 에칭)(Etching of Polysilicon Layer 101 in Fig. 1 (f))

(메인 에칭)(Main etching)

에칭 가스 : HBr/O2 (400sccm/2sccm)Etching Gas: HBr / O 2 (400sccm / 2sccm)

압력 : 4.0Pa (30mTorr)Pressure: 4.0Pa (30mTorr)

전력 : 200W (상부) / 150W (하부)Power: 200W (top) / 150W (bottom)

(오버 에칭)(Over etching)

에칭 가스 : HBr/O2 (934sccm/4sccm)Etching Gas: HBr / O 2 (934sccm / 4sccm)

압력 : 20.0Pa (150mTorr)Pressure: 20.0Pa (150mTorr)

전력 : 650W (상부) / 200W (하부)Power: 650W (top) / 200W (bottom)

도2 는, 상기한 제1 실시 형태에 있어서의 폴리실리콘층(101)과 반사 방지막(BARC)(102)과의 사이에, 다른 막, 예를 들면 Si3N4막(120)이 형성되어 있는 제2 실시 형태의 반도체 장치의 제조 공정을 나타내는 것이다. 이 제2 실시 형태의 경우, 도1 에 나타낸 제1 실시 형태의 경우와 동일하게 하여 도2(a)∼(e) 의 공정을 행한다. 그리고 이 이후, SiO2막(104)에 의한 패턴을 마스크로 하여, 하층의 Si3N4막(120)을 에칭하고(f), 이 Si3N4막(120) 등을 마스크로 하여 폴리실리콘층(101)을 에칭한다(g). 또한, 도2 의 경우에 있어서, Si3N4막(120)을 대신하여 SiON(산질화실리콘)막을 이용해도 좋다.Fig. 2 shows another film, for example, a Si 3 N 4 film 120, between the polysilicon layer 101 and the antireflection film (BARC) 102 in the above-described first embodiment. The manufacturing process of the semiconductor device of 2nd Embodiment which exists is shown. In the case of this second embodiment, the processes of Figs. 2 (a) to (e) are performed in the same manner as in the case of the first embodiment shown in Fig. 1. Subsequently, the Si 3 N 4 film 120 is etched using the pattern of the SiO 2 film 104 as a mask (f), and the poly Si 3 N 4 film 120 is used as a mask. The silicon layer 101 is etched (g). In the case of FIG. 2, a SiON (silicon oxynitride) film may be used in place of the Si 3 N 4 film 120.

도3 은, 제3 실시 형태의 반도체 장치의 제조 방법의 공정을 나타내는 것이다. 도3(a) 에 나타내는 바와 같이, 이 제3 실시 형태에서는, 예를 들면, 산화막, 질화막, 폴리실리콘 등으로 이루어지며, 패터닝을 목적으로 하는 피에칭층(131)의 위에는, 유기막(132)이 형성되어 있으며, 이 유기막(132)의 위에, 무기 재료로 이루어지는 반사 방지막으로서 SOG막(또는 LTO막)(133)이 형성되어 있고, 이 SOG막(또는 LTO막)(133)의 위에 포토레지스트(134)가 형성되어 있다. 포토레지스트(134)는, 노광, 현상 공정에 의해, 패터닝되어, 소정의 형상을 갖는 패턴으로 되어 있다.3 shows a step of the manufacturing method of the semiconductor device of the third embodiment. As shown in Fig. 3A, in the third embodiment, the organic film 132 is formed of, for example, an oxide film, a nitride film, polysilicon, or the like to be etched for the purpose of patterning. Is formed, and on this organic film 132, an SOG film (or LTO film) 133 is formed as an antireflection film made of an inorganic material, and on this SOG film (or LTO film) 133 The photoresist 134 is formed. The photoresist 134 is patterned by an exposure process and a developing process to form a pattern having a predetermined shape.

도3(b) 는, 상기의 포토레지스트(134)를 트리밍하여 선폭을 좁게 한 상태를 나타내고 있다. 이 포토레지스트(134)의 트리밍을 행하는 공정은, 예를 들면, 산소 플라즈마 등을 이용한 플라즈마 에칭에 의해 행할 수 있다. 또한, 이 트리밍 공정은, 필요에 따라 행하는 것이며, 포토레지스트(134)가 소망의 선폭으로 되어 있는 경우는 생략된다.FIG. 3B shows a state in which the line width is narrowed by trimming the photoresist 134 described above. The process of trimming this photoresist 134 can be performed by plasma etching using oxygen plasma etc., for example. In addition, this trimming process is performed as needed, and is abbreviate | omitted when the photoresist 134 has a desired line width.

다음으로, 도3(c) 에 나타내는 바와 같이, SiO2막(135)을 성막한다. 이 성막 공정에서는, 포토레지스트(134)의 위에 성막을 행하기 때문에, 전술한 바와 같이, 저온(예를 들면 300℃ 이하 정도)에서 성막하는 것이 바람직하고, 가열 촉매체로 성막 가스를 활성화시킨 화학기상성장 등에 의해 행할 수 있다.Next, as shown in Fig. 3C, a SiO 2 film 135 is formed. In this film forming step, since the film is formed on the photoresist 134, as described above, the film is preferably formed at a low temperature (for example, about 300 ° C. or lower), and a chemical vapor phase in which the film forming gas is activated with a heating catalyst body. By growth or the like.

다음으로, 도3(d) 에 나타내는 바와 같이, SiO2막(135)을 에칭하여, SiO2막(135)이, 포토레지스트(134)의 패턴의 측벽부에만 남은 상태로 한다. 이 에칭은, 예를 들면, CF4, C4F8, CHF3, CH3F, CH2F2 등의 CF계 가스와, Ar 가스 등의 혼합 가스, 또는 이 혼합 가스에 필요에 따라 산소를 첨가한 가스 등을 이용하여 행할 수 있다.Next, as shown in Fig. 3 (d), the SiO 2 film 135 is etched so that the SiO 2 film 135 remains in only the sidewall portion of the pattern of the photoresist 134. Next, as shown in FIG. This etching is performed by, for example, CF-based gases such as CF 4 , C 4 F 8 , CHF 3 , CH 3 F, and CH 2 F 2 , mixed gas such as Ar gas, or oxygen in the mixed gas as necessary. It can be performed using a gas or the like added.

다음으로, 도3(e) 에 나타내는 바와 같이, 산소 플라즈마를 이용한 애싱 등에 의해, 포토레지스트(134)의 패턴을 제거하여, 측벽부에 남은 SiO2막(135)에 의한 패턴을 형성한다.Next, as shown in Fig. 3E, the pattern of the photoresist 134 is removed by ashing using oxygen plasma or the like to form a pattern by the SiO 2 film 135 remaining in the sidewall portion.

이 이후, 도3(f) 에 나타내는 바와 같이, 상기의 SiO2막(135)에 의한 패턴을 마스크로 하여, 하층의 SOG막(또는 LTO막)(133)을 에칭하고, 또한, 도3(g) 에 나타내는 바와 같이, 하층의 유기막(132)을 에칭한다. 그리고, 패터닝된 유기막(132)을 포함하는 마스크를 통하여 하층의 피에칭층(131)을 에칭한다. 이 경우 피에칭층(131)은, 폴리실리콘 등의 외에, 산화막, 질화막 등의 무기 재료로 이루어지는 막이어도 좋다. 또한, SOG막(또는 LTO막)(133)의 에칭은, 전술한 CF계 가스 등으로 이루어지는 혼합 가스를 이용하여 행할 수 있고, 유기막(132)의 에칭은, 산소 또는 질소 등의 가스를 이용하여 행할 수 있다.After that, as shown in Fig. 3 (f), the lower SOG film (or LTO film) 133 is etched using the pattern of the SiO 2 film 135 as a mask, and further, Fig. 3 ( As shown in g), the lower organic film 132 is etched. The lower etching target layer 131 is etched through a mask including the patterned organic layer 132. In this case, the etching target layer 131 may be a film made of an inorganic material such as an oxide film or a nitride film, in addition to polysilicon. The SOG film (or LTO film) 133 can be etched using a mixed gas made of the CF-based gas or the like described above, and the organic film 132 is etched using a gas such as oxygen or nitrogen. This can be done.

도4 는, 상기한 제3 실시 형태에 있어서의 SOG막(또는 LTO막)(133)의 대신에 반사 방지막으로서 SiON막(140)이 형성되어 있는 제4 실시 형태의 반도체 장치의 제조 공정을 나타내는 것이다. 이 제4 실시 형태의 경우, 도3 에 나타낸 제3 실시 형태의 경우의 도3(a)∼(g) 의 공정과 동일하게 하여 도4(a)∼(g) 의 공정을 행한다.Fig. 4 shows a manufacturing process of the semiconductor device of the fourth embodiment in which the SiON film 140 is formed as an antireflection film instead of the SOG film (or LTO film) 133 in the above-described third embodiment. will be. In the case of this fourth embodiment, the processes of FIGS. 4A to 4G are performed in the same manner as the processes of FIGS. 3A to 3G in the third embodiment shown in FIG.

다음으로, 도6 내지 10 을 참조하여, 제5 실시 형태에 대하여 설명한다. 도6(a) 에 나타내는 바와 같이, 이 제5 실시 형태에서는, 패터닝을 목적으로 하는 피 에칭층으로서의 산화실리콘층(500)의 위에, 제2 마스크 구성층으로서의 질화실리콘층(501)이 형성되어 있다. 이 질화실리콘층(501)의 위에는, 제1 마스크 구성층으로서의 아모퍼스(amorphous) 실리콘층(502)이 형성되어 있다. 이 아모퍼스 실리콘층(502)은, 폴리실리콘층이어도 좋다. 이 아모퍼스 실리콘층(502)의 위에, 유기 재료로 이루어지는 반사 방지막(BARC)(503)이 형성되어 있다. 그리고, 이 반사 방지막(BARC)(503)의 위에 포토레지스트(504)가 형성되어 있다. 포토레지스트(504)는, 노광, 현상 공정에 의해, 패터닝되어, 복수의 라인 형상을 갖는 소정의 패턴(제1 패턴)으로 되어 있다. 이 포토레지스트(504)의 라인 형상의 패턴은, 예를 들면, 라인의 폭(선폭)이 60nm, 라인과 라인과의 사이의 간격이 60nm 등으로 된다.Next, with reference to FIGS. 6-10, 5th Embodiment is described. As shown in Fig. 6A, in the fifth embodiment, the silicon nitride layer 501 as the second mask constituent layer is formed on the silicon oxide layer 500 as the etching target layer for patterning. have. On this silicon nitride layer 501, an amorphous silicon layer 502 as a first mask component layer is formed. The amorphous silicon layer 502 may be a polysilicon layer. An antireflection film (BARC) 503 made of an organic material is formed on the amorphous silicon layer 502. The photoresist 504 is formed on the antireflection film BARC 503. The photoresist 504 is patterned by exposure and development processes to form a predetermined pattern (first pattern) having a plurality of line shapes. In the line pattern of the photoresist 504, for example, the line width (line width) is 60 nm, and the interval between the line and the line is 60 nm or the like.

도6(b) 는, 상기의 포토레지스트(504)를 트리밍하여 선폭을 좁게 함(예를 들면, 30nm로 함)과 아울러, 반사 방지막(BARC)(503)을 에칭한 상태를 나타내고 있다. 이 포토레지스트(504)의 트리밍 및 반사 방지막(BARC)(503)의 에칭을 행하는 공정은, 예를 들면, 산소 플라즈마 등을 이용한 플라즈마 에칭에 의해 행할 수 있다.FIG. 6B shows a state in which the anti-reflection film (BARC) 503 is etched while trimming the photoresist 504 to narrow the line width (for example, 30 nm). The process of trimming the photoresist 504 and etching the antireflection film (BARC) 503 can be performed by plasma etching using oxygen plasma or the like, for example.

다음으로, 도6(c) 에 나타내는 바와 같이, 포토레지스트(504)의 위에, SiO2막(505)을 성막하는 제1 성막 공정을 행한다. 이 성막 공정은, 전술한 실시 형태와 동일하게, 가열 촉매체로 성막 가스을 활성화시킨 화학기상성장 등에 의해 행한다.Next, as shown in Fig. 6C, a first film forming step of forming a SiO 2 film 505 on the photoresist 504 is performed. This film forming step is performed by chemical vapor growth or the like in which the film forming gas is activated with the heating catalyst body in the same manner as in the above-described embodiment.

다음으로, 도6(d) 에 나타내는 바와 같이, SiO2막(505)을 에칭하여, SiO2 막(505)이, 포토레지스트(504)의 패턴의 측벽부에만 남은 상태로 하는 제1 에칭 공정을 행한다. 이 에칭은, 예를 들면, CF4, C4F8, CHF3, CH3F, CH2F2 등의 CF계 가스와, Ar 가스 등의 혼합 가스, 또는 이 혼합 가스에 필요에 따라 산소를 첨가한 가스 등을 이용하여 행할 수 있다.Next, as shown in FIG. 6 (d), the SiO 2 film 505 is etched so that the SiO 2 film 505 remains in only the sidewall portion of the pattern of the photoresist 504. Is done. This etching is performed by, for example, CF-based gases such as CF 4 , C 4 F 8 , CHF 3 , CH 3 F, and CH 2 F 2 , mixed gas such as Ar gas, or oxygen in the mixed gas as necessary. It can be performed using a gas or the like added.

다음으로, 도6(e) 에 나타내는 바와 같이, 산소 플라즈마를 이용한 애싱 등에 의해, 포토레지스트(504)의 패턴을 제거하여, 측벽부에 남은 SiO2막(505)에 의한 패턴(제2 패턴)을 형성하는 제2 패턴 형성 공정을 행하고, 이 SiO2막(505)에 의한 패턴을 마스크로 하여 아모퍼스 실리콘층(502)을 에칭하는 제2 에칭 공정을 행한다. 아모퍼스 실리콘층(502)의 에칭은, 예를 들면, HBr 가스 등을 이용하여 행할 수 있다.Next, as shown in Fig. 6E, the pattern of the photoresist 504 is removed by ashing using an oxygen plasma or the like, and the pattern (second pattern) by the SiO 2 film 505 remaining in the sidewall portion. A second pattern forming step of forming a film is performed, and a second etching step of etching the amorphous silicon layer 502 using the pattern by the SiO 2 film 505 as a mask is performed. The etching of the amorphous silicon layer 502 can be performed using HBr gas etc., for example.

그리고, 도6(f) 에 나타내는 바와 같이, 에칭 마스크로서 사용한 SiO2막(505)을 제거한다. 이상의 공정에 의해, 도7 의 평면도에 나타내는 바와 같이, 반도체 웨이퍼를 위에서 보았을 때에, 아모퍼스 실리콘층(502)이 라인 형상(선폭 예를 들면 30nm, 간격 예를 들면 30nm)으로 형성되고, 이들의 아모퍼스 실리콘층(502)의 사이에, 하층의 질화실리콘층(501)이 노출한 상태가 된다. 또한, 도6(f) 는, 도7 의 일점쇄선으로 나타내는 A단면의 단면도이다.As shown in Fig. 6F, the SiO 2 film 505 used as the etching mask is removed. By the above process, as shown in the plan view of FIG. 7, when the semiconductor wafer is viewed from above, the amorphous silicon layer 502 is formed in a line shape (line width, for example, 30 nm, interval, for example, 30 nm). The lower silicon nitride layer 501 is exposed between the amorphous silicon layers 502. 6 (f) is sectional drawing of the A cross section shown by the dashed-dotted line of FIG.

다음으로, 상기한 도6(f) 의 상태로부터, 도8(B1), (C1) 에 나타내는 바와 같이, 반사 방지막(BARC)(513)을 형성하고, 그 위에 도포, 노광, 현상 공정에 의해 패터닝한 포토레지스트(514)(제3 패턴)를 형성하는 제3 패턴 형성 공정을 행한다. 이 포토레지스트(514)는, 도7 에 나타낸 라인 형상의 아모퍼스 실리콘층(502)과 직교하는 방향의 라인 형상의 패턴으로, 예를 들면, 라인의 폭(선폭)이 60nm, 라인과 라인과의 사이의 간격이 60nm의 패턴으로 이루어진다. 또한, 도8 의 좌측에는, 후술하는 도9 에 나타내는 평면도에 있어서의 B단면, 도8 의 우측에는, C단면을 나타내고 있다.Next, as shown in Figs. 8B1 and C1, the antireflection film BARC 513 is formed from the above-described state of Fig. 6F, and the coating, exposure, and development processes are formed thereon. A third pattern forming step of forming the patterned photoresist 514 (third pattern) is performed. The photoresist 514 is a line-shaped pattern in a direction orthogonal to the line-shaped amorphous silicon layer 502 shown in Fig. 7, for example, the line width (line width) is 60 nm, the line and the line; The interval between is made of a pattern of 60 nm. 8, cross section B is shown in the plan view shown in FIG. 9 to be described later, and cross section C is shown on the right side of FIG.

도8(B2), (C2) 는, 상기의 포토레지스트(514)를 트리밍하여 선폭을 좁게 함(예를 들면, 30nm로 함)과 아울러, 반사 방지막(BARC)(513)을 에칭한 상태를 나타내고 있다. 이 포토레지스트(514)의 트리밍 및 반사 방지막(BARC)(513)의 에칭을 행하는 공정은, 예를 들면, 산소 플라즈마 등을 이용한 플라즈마 에칭에 의해 행할 수 있다.8 (B2) and (C2) show a state where the anti-reflection film (BARC) 513 is etched while trimming the photoresist 514 to narrow the line width (e.g., 30 nm). It is shown. The process of trimming the photoresist 514 and etching the antireflection film (BARC) 513 can be performed by, for example, plasma etching using an oxygen plasma or the like.

다음으로, 도8(B3), (C3) 에 나타내는 바와 같이, SiO2막(515)을 성막하는 제2 성막 공정을 행한다. 이 성막 공정은, 전술한 실시 형태와 동일하게, 예를 들면, 가열 촉매체로 성막 가스를 활성화시킨 화학기상성장 등에 의해 행한다.Next, as shown in Fig. 8 (B3), (C3), it performs a second film forming step of forming the SiO 2 film 515. This film forming step is performed by chemical vapor growth or the like in which, for example, the film forming gas is activated with a heating catalyst body, similarly to the above-described embodiment.

다음으로, 도8(B4), (C4) 에 나타내는 바와 같이, SiO2막(515)을 에칭하여, SiO2막(515)이, 포토레지스트(514)의 패턴의 측벽부에만 남은 상태로 하는 제3 에칭 공정을 행한다. 이 에칭은, 예를 들면, CF4, C4F8, CHF3, CH3F, CH2F2 등의 CF계 가스와, Ar 가스 등의 혼합 가스, 또는 이 혼합 가스에 필요에 따라 산소를 첨가한 가스 등을 이용하여 행할 수 있다.Next, as shown in FIGS. 8B4 and 4C, the SiO 2 film 515 is etched so that the SiO 2 film 515 remains in only the sidewall portion of the pattern of the photoresist 514. A third etching step is performed. This etching is performed by, for example, CF-based gases such as CF 4 , C 4 F 8 , CHF 3 , CH 3 F, and CH 2 F 2 , mixed gas such as Ar gas, or oxygen in the mixed gas as necessary. It can be performed using a gas or the like added.

다음으로, 도8(B5), (C5) 에 나타내는 바와 같이, 산소 플라즈마를 이용한 애싱 등에 의해, 포토레지스트(514)의 패턴을 제거하여, 측벽부에 남은 SiO2막(515)에 의한 패턴(제4 패턴)을 형성하는 제4 패턴 형성 공정을 행한다.Next, as shown in FIGS. 8B5 and C5, the pattern of the photoresist 514 is removed by ashing using an oxygen plasma or the like, and the pattern of the SiO 2 film 515 remaining in the sidewall portion ( A fourth pattern forming step of forming a fourth pattern) is performed.

다음으로, 도8(B6), (C6) 에 나타내는 바와 같이, SiO2막(515)에 의한 패턴 및 아모퍼스 실리콘층(502)을 마스크로 하여, 질화실리콘층(501)을 에칭하는 제4 에칭 공정을 행한다. 질화실리콘층(501)의 에칭은, 예를 들면, CF4, C4F8, CHF3, CH3F, CH2F2 등의 CF계 가스와, Ar 가스 등의 혼합 가스, 또는 이 혼합 가스에 필요에 따라 산소를 첨가한 가스 등을 이용하여 행할 수 있다. 이 상태에서는, 도9 의 평면도에 나타내는 바와 같이, 반도체 웨이퍼를 위에서 보았을 때에, 라인 형상의 SiO2막(515)과, 이 라인 형상의 SiO2막(515)의 사이의 직사각 형상의 아모퍼스 실리콘층(502)에 둘러싸여 직사각 형상으로 산화실리콘층(500)이 노출한 영역이 형성된 상태로 되어 있다.Next, as shown in FIGS. 8B6 and C6, the silicon nitride layer 501 is etched using the pattern of the SiO 2 film 515 and the amorphous silicon layer 502 as a mask. An etching process is performed. Etching of the silicon nitride layer 501 is, for example, CF-based gas such as CF 4 , C 4 F 8 , CHF 3 , CH 3 F, CH 2 F 2 , mixed gas such as Ar gas, or a mixture thereof. It can carry out using the gas etc. which added oxygen as needed to gas. In this state, as shown in the plan view of FIG. 9, when viewed from above, the rectangular amorphous silicon between the linear SiO 2 film 515 and the linear SiO 2 film 515. Surrounded by the layer 502, the region in which the silicon oxide layer 500 is exposed in a rectangular shape is formed.

다음으로, 도10 에 나타내는 바와 같이, SiO2막(515)을 제거함과 아울러, 아모퍼스 실리콘층(502) 및 질화실리콘층(501)을 마스크로 하여, 산화실리콘층(500)을 에칭하는 제5 에칭 공정을 행한다. 이상의 공정에 의해, 도10 에 나타내는 바와 같이, 산화실리콘층(500)에 반도체 웨이퍼(W)의 표면이 노출하는 홀(hole) 형상을 형성한다. 또한, 도10(a) 는 평면도, 도10(b) 는, 도10(a) 에 나타내는 일점쇄선(B)을 따른 단면도, 도10(c) 는, 도10(a) 에 나타내는 일점쇄선(C)을 따른 단면도이다.Next, as shown in FIG. 10, the SiO 2 film 515 is removed, and the silicon oxide layer 500 is etched using the amorphous silicon layer 502 and the silicon nitride layer 501 as a mask. 5 An etching process is performed. Through the above steps, as shown in FIG. 10, a hole shape in which the surface of the semiconductor wafer W is exposed is formed in the silicon oxide layer 500. 10 (a) is a plan view, FIG. 10 (b) is a sectional view along the dashed-dotted line B shown in FIG. 10 (a), and FIG. 10 (c) is a dashed-dotted line shown in FIG. 10 (a). Sectional view along C).

상기의 제5 실시 형태에 의하면, 예를 들면, 1변이 30nm 등의 미세한 홀 형상의 패턴을 형성할 수 있다.According to said fifth embodiment, for example, one side can form a fine hole-shaped pattern such as 30 nm.

도5 는, 상기의 반도체 장치의 제조 방법을 실시하기 위한 반도체 장치의 제조 장치의 구성의 일 예를 개략적으로 나타내는 상면도(上面圖)이다. 반도체 장치의 제조 장치(1)의 중앙 부분에는, 진공 반송 챔버(10)가 형성되어 있고, 이 진공 반송 챔버(10)를 따라, 그 주위에는, 복수(본 실시 형태에서는 6개)의 처리 챔버(11∼16)가 설치되어 있다. 이들 처리 챔버는, 내부에서 플라즈마 에칭 및 가열 촉매체로 성막 가스를 활성화시킨 화학기상성장을 행하는 것이다.FIG. 5 is a top view schematically showing an example of the configuration of a semiconductor device manufacturing apparatus for carrying out the above-described method for manufacturing a semiconductor device. FIG. The vacuum conveyance chamber 10 is formed in the center part of the manufacturing apparatus 1 of a semiconductor device, and along this vacuum conveyance chamber 10, the process chamber of the plurality (6 in this embodiment) around it 11 to 16 are provided. These processing chambers perform chemical vapor growth in which the deposition gas is activated by plasma etching and a heating catalyst body therein.

진공 반송 챔버(10)의 바로 앞측(도면 중 하측)에는, 2개의 로드락 챔버(load lock chamber;17)가 형성되고, 이들 로드락 챔버(17)의 더욱 바로 앞측(도면 중 하측)에는, 대기(大氣) 중에서 기판(본 실시 형태에서는 반도체 웨이퍼(W))을 반송하기 위한 반송 챔버(18)가 형성되어 있다. 또한, 반송 챔버(18)의 더욱 바로 앞측(도면 중 하측)에는, 복수매의 반도체 웨이퍼(W)가 수용 가능하게 된 기판 수용 케이스(카세트(cassette) 또는 후프(hoop))가 배치되는 재치부(載置部;19)가 복수(도5 에서는 3개) 형성되어 있고, 반송 챔버(18)의 측방(도면 중 좌측)에는, 오리엔테이션 플랫(orientation flat) 또는 노치(notch)에 의해 반도체 웨이퍼(W)의 위치를 검출하는 오리엔터(orienter;20)가 형성되어 있다.Two load lock chambers 17 are formed immediately in front of the vacuum transfer chamber 10 (lower side in the drawing), and in the front side (lower side in the drawing) of these load lock chambers 17, The conveyance chamber 18 for conveying a board | substrate (in this embodiment, a semiconductor wafer W) is formed in air | atmosphere. Further, on a further front side (lower side in the drawing) of the transfer chamber 18, a mounting portion on which a substrate storage case (cassette or hoop) in which a plurality of semiconductor wafers W can be accommodated is arranged is placed. A plurality of (19) portions (three in FIG. 5) are formed, and a semiconductor wafer (by an orientation flat or notch) is formed on the side (left side in the drawing) of the transfer chamber 18. An orienter 20 for detecting the position of W) is formed.

로드락 챔버(17)와 반송 챔버(18)와의 사이, 로드락 챔버(17)와 진공 반송 챔버(10)와의 사이, 진공 반송 챔버(10)와 처리 챔버(11∼16)와의 사이에는, 각각 게이트 밸브(22)가 형성되어, 이들의 사이를 기밀하게 폐색 및 개방할 수 있도록 되어 있다. 또한, 진공 반송 챔버(10) 내에는 진공 반송 기구(30)가 형성되어 있다. 이 진공 반송 기구(30)는, 제1 픽(pick;31)과 제2 픽(32)을 구비하고, 이들에 의해 2장의 반도체 웨이퍼(W)가 지지 가능하게 구성되어 있고, 각 처리 챔버(11∼16), 로드락 챔버(17)에, 반도체 웨이퍼(W)를 반입, 반출할 수 있도록 구성되어 있다.Between the load lock chamber 17 and the transfer chamber 18, between the load lock chamber 17 and the vacuum transfer chamber 10, and between the vacuum transfer chamber 10 and the processing chambers 11 to 16, respectively. The gate valve 22 is formed, and it is possible to close and open hermetically between them. Moreover, the vacuum conveyance mechanism 30 is formed in the vacuum conveyance chamber 10. This vacuum conveyance mechanism 30 is equipped with the 1st pick 31 and the 2nd pick 32, and is comprised so that two semiconductor wafers W can be supported by these, and each processing chamber ( 11-16 and the load lock chamber 17 are comprised so that the semiconductor wafer W may be carried in and out.

또한, 반송 챔버(18) 내에는, 대기 반송 기구(40)가 형성되어 있다. 이 대기 반송 기구(40)는, 제1 픽(41)과, 제2 픽(42)을 구비하고 있고, 이들에 의해 2장의 반도체 웨이퍼(W)가 지지 가능하게 구성되어 있다. 대기 반송 기구(40)는, 재치부(19)에 올려놓여진 각 카세트 또는 후프, 로드락 챔버(17), 오리엔터(20)에 반도체 웨이퍼(W)를 반입, 반출할 수 있도록 구성되어 있다.In addition, the atmospheric conveyance mechanism 40 is formed in the conveyance chamber 18. This atmospheric conveyance mechanism 40 is equipped with the 1st pick 41 and the 2nd pick 42, and is comprised so that two semiconductor wafers W can be supported by these. The atmospheric conveyance mechanism 40 is comprised so that the semiconductor wafer W may be carried in and out of each cassette or hoop mounted on the mounting part 19, the load lock chamber 17, and the orienter 20.

상기 구성의 반도체 장치의 제조 장치(1)는, 제어부(60)에 의해, 그 동작이 통괄적으로 제어된다. 이 제어부(60)에는, CPU를 구비하여 반도체 장치의 제조 장치(1)의 각 부(部)를 제어하는 프로세스 컨트롤러(61)와, 유저 인터페이스부(62)와, 기억부(63)가 형성되어 있다.As for the manufacturing apparatus 1 of the semiconductor device of the said structure, the operation is controlled by the control part 60 collectively. The control unit 60 includes a process controller 61, a user interface unit 62, and a storage unit 63 that include a CPU to control respective units of the manufacturing apparatus 1 of the semiconductor device. It is.

유저 인터페이스부(62)는, 공정 관리자가 반도체 장치의 제조 장치(1)를 관리하기 위해 커맨드(command)의 입력 조작을 행하는 키보드나, 반도체 장치의 제조 장치(1)의 가동 상황을 가시화하여 표시하는 디스플레이 등으로 구성되어 있다.The user interface unit 62 visualizes and displays the operation state of the keyboard for performing a command input operation for the process manager to manage the manufacturing apparatus 1 of the semiconductor device, or the manufacturing apparatus 1 of the semiconductor device. And a display.

기억부(63)에는, 반도체 장치의 제조 장치(1)에서 실행되는 각종 처리를 프로세스 컨트롤러(61)의 제어로 실현하기 위한 제어 프로그램(소프트웨어)이나 처리 조건 데이터 등이 기억된 레시피(recipe)가 격납되어 있다. 그리고, 필요에 따라, 유저 인터페이스부(62)로부터의 지시 등으로 임의의 레시피를 기억부(63)로부터 불러내어 프로세스 컨트롤러(61)에 실행시킴으로써, 프로세스 컨트롤러(61)의 제어 하에서, 반도체 장치의 제조 장치(1)에서의 소망의 처리가 행해진다. 또한, 제어 프로그램이나 처리 조건 데이터 등의 레시피는, 컴퓨터에서 판독 가능한 프로그램 기억 매체(예를 들면, 하드디스크, CD, 플렉시블 디스크(flexible disk), 반도체 메모리 등) 등에 격납된 상태의 것을 이용하거나, 또는, 다른 장치로부터, 예를 들면 전용 회선을 통하여 수시 전송시켜 온라인에서 이용하거나 하는 것도 가능하다.The storage unit 63 has recipes in which control programs (software), processing condition data, and the like are stored for realizing various processes executed in the manufacturing apparatus 1 of the semiconductor device under the control of the process controller 61. It is stored. Then, if necessary, arbitrary recipes are retrieved from the storage unit 63 by the instruction from the user interface unit 62 and executed in the process controller 61 to control the semiconductor device under the control of the process controller 61. The desired process in the manufacturing apparatus 1 is performed. In addition, recipes, such as a control program and processing condition data, use the thing stored in the computer-readable program storage medium (for example, a hard disk, a CD, a flexible disk, a semiconductor memory, etc.), etc., Alternatively, other devices can be used online, for example, by transferring from time to time on a dedicated line.

상기 구성의 반도체 장치의 제조 장치(1)를 이용하여, 제1∼5 실시 형태에 나타낸 일련의 공정을 실시할 수 있다. 또한, 성막 공정에 대해서는, 일단 반도체 웨이퍼(W)를 상기의 반도체 장치의 제조 장치(1)로부터 반출하여 다른 장치에 의해 행해도 좋다. 또한, 포토레지스트의 도포, 노광, 현상 공정에 대해서는, 다른 도포 장치, 노광 장치, 현상 장치에 의해 행한다.Using the manufacturing apparatus 1 of the semiconductor device of the said structure, a series of process shown to 1st-5th embodiment can be implemented. In addition, about the film-forming process, you may carry out the semiconductor wafer W once from the manufacturing apparatus 1 of said semiconductor device, and may perform it by another apparatus. In addition, the application | coating, exposure, and image development process of a photoresist is performed by another coating apparatus, exposure apparatus, and a developing apparatus.

도1 은 본 발명의 제1 실시 형태의 공정을 개략적으로 나타내는 도면이다.BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the process of 1st embodiment of this invention schematically.

도2 는 본 발명의 제2 실시 형태의 공정을 개략적으로 나타내는 도면이다.2 is a diagram schematically showing a process of a second embodiment of the present invention.

도3 은 본 발명의 제3 실시 형태의 공정을 개략적으로 나타내는 도면이다.3 is a view schematically showing a process of a third embodiment of the present invention.

도4 는 본 발명의 제4 실시 형태의 공정을 개략적으로 나타내는 도면이다.4 is a diagram schematically showing a process of a fourth embodiment of the present invention.

도5 는 본 발명의 일 실시 형태에 사용하는 장치의 개략 구성을 개략적으로 나타내는 도면이다.5 is a diagram schematically showing a schematic configuration of an apparatus used in an embodiment of the present invention.

도6 은 본 발명의 제5 실시 형태의 공정을 개략적으로 나타내는 도면이다.6 is a diagram schematically showing a process of a fifth embodiment of the present invention.

도7 은 본 발명의 제5 실시 형태의 공정에 있어서의 평면 구성을 개략적으로 나타내는 도면이다.FIG. 7 is a diagram schematically showing a planar configuration in a step of the fifth embodiment of the present invention. FIG.

도8 은 본 발명의 제5 실시 형태의 공정을 개략적으로 나타내는 도면이다.8 is a view schematically showing a process of the fifth embodiment of the present invention.

도9 는 본 발명의 제5 실시 형태의 공정에 있어서의 평면 구성을 개략적으로 나타내는 도면이다.9 is a diagram schematically showing a planar configuration in a step of the fifth embodiment of the present invention.

도10 은 본 발명의 제5 실시 형태의 공정에 있어서의 평면 구성 및 단면 구성을 개략적으로 나타내는 도면이다.10 is a diagram schematically showing a planar configuration and a cross-sectional configuration in a step of the fifth embodiment of the present invention.

(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

100 : 하지(base)층100: base layer

101 : 폴리실리콘층101: polysilicon layer

102 : 반사 방지막(BARC)102: antireflection film (BARC)

103 : 포토레지스트103: photoresist

104 : SiO2막104: SiO 2 film

Claims (12)

삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 기판 상의 피에칭층을 소정의 패턴으로 에칭하여, 반도체 장치를 제조하는 반도체 장치의 제조 방법으로서,A method of manufacturing a semiconductor device, in which a etching target layer on a substrate is etched in a predetermined pattern to produce a semiconductor device. 포토레지스트로 이루어지는 복수의 라인 형상의 제1 패턴을 형성하는 제1 패턴 형성 공정과,A first pattern forming step of forming a plurality of line-shaped first patterns made of a photoresist, 상기 제1 패턴의 위에 SiO2막을 성막하는 제1 성막 공정과,A first film forming step of forming a SiO 2 film on the first pattern, 상기 SiO2막을 상기 포토레지스트의 제1 패턴의 측벽부에만 남도록 에칭하는 제1 에칭 공정과,A first etching process of etching the SiO 2 film so that only the sidewall portion of the first pattern of the photoresist remains; 상기 제1 패턴을 제거하여 상기 SiO2막의 제2 패턴을 형성하는 제2 패턴 형성 공정과,A second pattern forming process of removing the first pattern to form a second pattern of the SiO 2 film; 상기 제2 패턴을 마스크로 하여 하층의 제1 마스크 구성층을 에칭하는 제2 에칭 공정과,A second etching step of etching the lower first mask component layer using the second pattern as a mask; 상기 제1 패턴과 직교하는 방향으로, 포토레지스트의 복수의 라인 형상의 패턴으로 이루어지는 제3 패턴을 형성하는 공정과,Forming a third pattern including a plurality of line-shaped patterns of the photoresist in a direction orthogonal to the first pattern; 상기 제3 패턴의 위에 SiO2막을 성막하는 제2 성막 공정과,A second film forming step of forming a SiO 2 film on the third pattern, 상기 SiO2막을 상기 제3 패턴의 측벽부에만 남도록 에칭하는 제3 에칭 공정과,A third etching process of etching the SiO 2 film so that only the sidewall portion of the third pattern remains; 상기 제3 패턴을 제거하여 상기 SiO2막의 제4 패턴을 형성하는 제4 패턴 형성 공정과,A fourth pattern forming process of removing the third pattern to form a fourth pattern of the SiO 2 film; 상기 제4 패턴 및 상기 제1 마스크 구성층을 마스크로 하여, 하층의 제2 마스크 구성층을 에칭하는 제4 에칭 공정과,A fourth etching step of etching the lower layer second mask component layer using the fourth pattern and the first mask component layer as a mask, 상기 제1 마스크 구성층과 상기 제2 마스크 구성층을 마스크로 하여, 상기 피에칭층에 홀(hole) 형상을 형성하는 제5 에칭 공정을 구비한 것을 특징으로 하는 반도체 장치의 제조 방법.And a fifth etching step of forming a hole shape in the etching target layer using the first mask component layer and the second mask component layer as masks. 제7항에 있어서,The method of claim 7, wherein 상기 제1 및 제2 성막 공정을, 가열 촉매체로 성막 가스를 활성화시킨 화학기상성장에 의해 행하는 것을 특징으로 하는 반도체 장치의 제조 방법.The first and second film forming steps are performed by chemical vapor growth in which the film forming gas is activated by a heating catalyst body. 제7항에 있어서,The method of claim 7, wherein 상기 제1 성막 공정의 전에, 상기 제1 패턴을 트리밍함과 아울러, 하층의 유기 재료로 이루어지는 반사 방지막을 에칭하는 공정과,Before the first film forming step, trimming the first pattern and etching an antireflection film made of an organic material of a lower layer; 상기 제2 성막 공정의 전에, 상기 제3 패턴을 트리밍함과 아울러, 하층의 유기 재료로 이루어지는 반사 방지막을 에칭하는 공정을 구비한 것을 특징으로 하는 반도체 장치의 제조 방법.And a step of trimming the third pattern and etching an antireflection film made of an organic material of a lower layer before the second film forming step. 제7항에 있어서,The method of claim 7, wherein 상기 제1 마스크 구성층이 실리콘으로 이루어지고, 상기 제2 마스크 구성층이 질화실리콘으로 이루어지는 것을 특징으로 하는 반도체 장치의 제조 방법.And the first mask constituent layer is made of silicon, and the second mask constituent layer is made of silicon nitride. 기판 상의 피에칭층을 소정의 패턴으로 에칭하여, 반도체 장치를 제조하는 반도체 장치의 제조 장치로서,An apparatus for manufacturing a semiconductor device, wherein the etching target layer on the substrate is etched in a predetermined pattern to manufacture the semiconductor device. 상기 기판을 수용하는 처리 챔버와,A processing chamber containing the substrate; 상기 처리 챔버 내에 처리 가스를 공급하는 처리 가스 공급 수단과,Processing gas supply means for supplying a processing gas into the processing chamber; 상기 처리 챔버 내에서 제7항 내지 제10항 중 어느 한 항에 기재된 반도체 장치의 제조 방법이 행해지도록 제어하는 제어부를 구비한 것을 특징으로 하는 반도체 장치의 제조 장치.A control unit for controlling the semiconductor device according to any one of claims 7 to 10 to be carried out in the processing chamber. 컴퓨터 상에서 동작하는 제어 프로그램이 기억된 프로그램 기억 매체로서,A program storage medium storing a control program that runs on a computer, 상기 제어 프로그램은, 실행 시에 제7항 내지 제10항 중 어느 한 항에 기재된 반도체 장치의 제조 방법이 행해지도록 반도체 장치의 제조 장치를 제어하는 것을 특징으로 하는 프로그램 기억 매체.The said control program controls a manufacturing apparatus of a semiconductor device so that the manufacturing method of the semiconductor device of any one of Claims 7-10 may be performed at the time of execution.
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