KR100967098B1 - Manufacturing method of nonvolatile memory device - Google Patents

Abstract

The present invention is to provide a method of manufacturing a semiconductor device that can prevent the trap site (trap site) is formed in the gate oxide film by the ion implantation process is performed to compensate for the doping concentration of the channel region. The present invention includes forming a tunneling insulating film and a gate conductive film on a substrate having a channel region, etching the conductive film and the tunneling insulating film to expose the substrate, and a protective film on sidewalls of the etched conductive film and the tunneling insulating film. Forming a trench by etching the exposed substrate, implanting impurity ions into the channel region exposed by the trench, and removing the protective layer. It provides a manufacturing method.

Nonvolatile Memory Device, NAND Flash Memory Device, Channel Area, Ion Implantation Process

Description

Manufacturing method of nonvolatile memory device {METHOD FOR MANUFACTURING A NONVOLATILE MEMORY DEVICE}

1A to 1D are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to the prior art.

2A through 2E are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

200 substrate 201 tunneling insulating film

202: conductive film 203: hard mask

204: protective film 205: trench

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a nonvolatile memory device including an ion implantation process performed to compensate for a reduction in the doping concentration of a channel region.

Among the nonvolatile memory devices, NAND type flash memory devices are the most widely used. NAND flash memory devices are devices for high integration, and are mainly expanding their applications to memory devices that can replace memory sticks, universal serial bus drivers, and hard disks.

1A to 1D are cross-sectional views illustrating a method of manufacturing a NAND flash memory device according to the prior art.

First, as shown in FIG. 1A, a tunneling oxide film 101, a polysilicon film 102, and a hard mask 103 are sequentially formed on the semiconductor substrate 100.

Subsequently, as illustrated in FIG. 1B, the hard mask 103A, the polysilicon film 102A, and the tunneling oxide film 101A are locally etched to expose a portion of the semiconductor substrate 100.

Subsequently, as shown in FIG. 1C, the semiconductor substrate 100A exposing the hard mask 103A as an etch barrier layer is etched to form a trench 104 for the isolation layer.

Subsequently, as shown in FIG. 1D, an ion implantation process 105 is performed for the channel region.

As described above, in the method of manufacturing a NAND flash memory device according to the related art, an ion implantation process 105 is performed on the channel region of the semiconductor substrate 100A that is exposed after the trench 104 is formed. The reason is to compensate for the problem that the dopant concentration of the channel region is reduced by the diffusion of impurity ions implanted in the channel region of the semiconductor substrate 100A into the device isolation layer embedded in the subsequent trench 104 to adjust the threshold voltage.

However, in the ion implantation process 105, due to the high aspect ratio—the aspect ratio due to the step difference between the top surface of the hard mask 103A and the bottom of the trench 104—in the channel region of the semiconductor substrate 100 in contact with the trench 104. It is virtually difficult to implant the impurity ions stably, and some of the impurity ions are implanted into the tunneling oxide film 101A formed at the contact with the upper edge of the trench 104 to trap the trap site in the tunneling oxide film 101A. Form.

Accordingly, when a trap site is formed in the tunneling oxide film 101A, charges are trapped in the tunneling oxide film 101A during subsequent program and erase operations of the device, and thus uniform after the device write and erase operations. One threshold voltage distribution cannot be obtained.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, and is a nonvolatile memory capable of preventing the formation of trap sites in the tunneling oxide film during an ion implantation process performed to compensate for the doping concentration of the channel region. Its purpose is to provide a method for manufacturing a device.

According to an aspect of the present invention, there is provided a method of forming a tunneling insulating film and a gate conductive film on a substrate having a channel region, and etching the conductive film and the tunneling insulating film to expose the substrate. Forming a protective film on sidewalls of the etched conductive film and the tunneling insulating film, etching the exposed substrate to form a trench, implanting impurity ions into the channel region exposed by the trench; It provides a method of manufacturing a nonvolatile memory device comprising the step of removing the protective film.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the parts denoted by the same reference numerals throughout the specification represent the same layer, and when the reference numerals include English capital letters, it means that the same layer is partially modified through an etching or polishing process.

Example

2A through 2E are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention. As an example, a method of manufacturing a NAND flash memory device using an ASA-STI (Advanced Self Aligned-Shallow Trench Isolation) process will be described.

First, as shown in FIG. 2A, a triple n-type well (not shown) in a semiconductor substrate 200, such as a p-type substrate, and a p-type well therein. To form.

Subsequently, an ion implantation process for adjusting the threshold voltage is performed in the active region where the channel region is to be formed to form the channel region. For example, the ion implantation process for adjusting the threshold voltage is carried out at a dose of 1.0E13 to 5.0E13ions / cm ² at 10 to 30 KeV ion implantation energy using boron fluoride (BF).

Subsequently, a tunneling insulating film 201 is formed on the substrate 200. In this case, the tunneling insulating film 201 is formed of an oxide film, for example, silicon oxide film (SiO ₂ ), or a silicon oxide film is formed for device characteristics, and a heat treatment process using N ₂ gas is performed to interface the silicon oxide film and the substrate 200. You may further form a nitride layer. The manufacturing method may be a dry oxidation, a wet oxidation process or an oxidation process using radical ions. However, in view of characteristics, it is preferable to perform a dry oxidation and wet oxidation process instead of an oxidation process using radical ions. In addition, the tunneling insulating film 201 may be formed to a thickness of about 50 ~ 100Å.

Subsequently, a conductive film 202 serving as a floating gate is deposited on the tunneling insulating film 201. At this time, the conductive film 202 may be made of any conductive material, for example, may be formed of any one material selected from polysilicon, transition metal or rare earth metal. For example, the polysilicon film may be an un-doped polysilicon film that is not doped with impurities or a doped polysilicon film that is doped with impurities, and in the case of an undoped polysilicon film, subsequent ions Impurity ions are implanted separately through an implantation process. The polysilicon film is formed by a low pressure chemical vapor deposition (LPCVD) method, wherein SiH ₄ is used as a source gas, and PH ₃ , PH ₃ , BCl _3, or B ₂ H ₆ gas is used as a doping gas. As the transition metal, iron (Fe), cobalt (Co), tungsten (W), nickel (Ni), palladium (Pd), platinum (Pt), molybdenum (Mo) or titanium (Ti) and the like are used. Erbium (Er), Ytterium (Yb), Samarium (Sm), Yttrium (Y), Lanthanum (La), Cerium (Ce), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), and Tolium ( Tm), lutetium (Lu) and the like.

Next, a hard mask 203 is formed on the conductive film 202. In this case, the hard mask 203 is a layer formed to compensate for the lack of thickness of the photoresist pattern used as an etching mask in a subsequent shallow trench isolation (STI) etching process, and is formed of a nitride film. For example, the hard mask 203 has a nitrogen (N ₂ ) flow rate of 40 to 60 cc at a temperature of 700 to 800 ° C. and a pressure of 0.3 to 0.4 Torr using an LPCVD process, and uses DCS (Diclorosilane, SiCl ₂ H _2). ) Flow rate is 800 ~ 1000cc and ammonia (NH ₃ ) flow rate is 800 ~ 1000cc.

Meanwhile, a buffer film (not shown) may be further formed on the conductive film 202 before the hard mask 203 is formed, because the conductive film 202 may be formed from the stress applied during the subsequent hard mask 203 forming process. To protect the conductive film 202 from an etching solution such as phosphoric acid (H ₃ PO ₄ ) during the subsequent hard mask 203 removal process. For example, the buffer film is formed of a silicon oxide film (SiO ₂ ) when the hard mask 203 is formed of a silicon nitride film (Si ₃ N ₄ ).

Subsequently, as shown in FIG. 2B, a protective film 204 is formed on sidewalls of the hard mask 203, the conductive film 202, and the tunneling insulating film 201. In this case, the passivation layer 204 is formed to a thickness such that impurity ions do not enter the tunneling insulating layer 201 during the subsequent impurity ion implantation process (206 (see FIG. 2D)). For example, 30-70 microseconds, Preferably it is formed in 50 micrometers in thickness. In addition, the passivation layer 204 is formed of a material having an etching selectivity with the tunneling insulation layer pattern 201. For example, it is formed of a nitride film, preferably a silicon nitride film (Si ₃ N ₄ ).

Subsequently, as shown in FIG. 2C, a portion of the substrate 200A is etched using the protective film 204 as an etch barrier layer. As a result, a trench 205 for device isolation films aligned with the passivation film 204 is formed.

Next, as shown in FIG. 2D, an impurity ion implantation process 206 is performed to compensate for the doping reduction in the channel region while the protective film 204 covers the tunneling insulating film 201. For example, the impurity ion implantation process 206 is repeatedly performed four times by rotating the substrate 200A at 45 °, 135 °, 225 °, and 315 °. The process conditions in each process are carried out at a dose of 0.5E11 to 1.5E12ions / cm ² at 20-40KeV ion implantation energy using boron (B), wherein the ion implantation angle is 10-30 °, Preferably it is carried out at 15 degrees.

Next, as shown in FIG. 2E, the protective film 204 is removed. In this case, the passivation layer 204 may be formed under conditions having a high etching selectivity not only with the tunneling insulating layer 201 but also with the conductive layer 202. For example, when the protective film 204 is formed of a nitride film, the protective film 204 may be removed using phosphoric acid (H ₃ PO ₄ ).

Since the process is the same as the general process, a description thereof will be omitted.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In particular, the embodiment of the present invention has been described for the manufacturing method of the NAND flash memory device applying the ASA-STI process, which is for convenience of description, the self-aligned-shallow trench isolation (SA-STI) process and the existing STI process It can also be applied to the manufacturing method to apply. The present invention can also be applied to a method of manufacturing all nonvolatile memory devices including NOR flash memory devices. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, tunneling is formed by forming a protective film on the sidewall of the tunneling insulating film before the ion implantation process performed to compensate the doping concentration of the channel region, thereby preventing the tunneling insulating film from being exposed during the ion implantation process. It is possible to prevent the trap site from being formed in the insulating film and to prevent deterioration of device characteristics.

Claims (9)

Forming a tunneling insulating film and a gate conductive film on the substrate; Etching the conductive film and the tunneling insulating film to expose the substrate; Forming a protective film on sidewalls of the etched conductive film and the tunneling insulating film; Etching the substrate exposed with the protective layer as a mask to form a trench; Implanting impurity ions into the trench inner wall; And Removing the protective film Method of manufacturing a nonvolatile memory device comprising a. The method of claim 1, And forming the passivation layer to a thickness such that the impurity ions are not injected into the tunneling insulating layer in the step of implanting the impurity ions. The method of claim 1, The protective film is formed of a nitride film and the tunneling insulating film is formed of an oxide film. The method of claim 1, The protective film is a method of manufacturing a nonvolatile memory device formed of a nitride film. The method of claim 1, Implanting the impurity ions is performed using impurity ions having the same conductivity type as impurity ions implanted into the channel region. The method according to claim 1 or 5, The implanting of impurity ions may be performed using a boron (B) at a concentration of 0.5E11 to 1.5E12ions / cm ^{2 and} an ion implantation angle of 10 to 30 ° at 20 to 40 KeV ion implantation energy. Manufacturing method. The method of claim 6, The implanting of impurity ions is performed a total of four times by rotating the substrate to 45 °, 135 °, 225 °, 315 °. The method of claim 1, After removing the protective film, And forming an isolation layer to fill the trench. The method of claim 1, The protective film is a method of manufacturing a nonvolatile memory device to form a thickness of 30 ~ 70Å.

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