KR100965856B1 - Method and system for designing, simulating and debugging digital integrated circuit using procedural high level programming languages - Google Patents

Abstract

The simulation and verification method of the digital integrated circuit of the present invention uses a sequential execution advanced programming language such that one or more logics and one or more registers contained in a top-level function module operate on one or more clocks, respectively, to implement an algorithm. A method of simulating and verifying a digital integrated circuit, the method comprising: (a) activating at least one clock edge of the clock edges of the clock based on the order in which each clock edge appears, (b) output variables of all registers Respectively updating by the value of the input variables of the respective registers, (c) sequentially executing the operations of the respective logics, and (d) the input variables of the registers operating in correspondence with the activated at least one clock edge. Are provided from the respective logics and registers. Each step of updating by the and (e) may include the step of repeating the iteration of (a) to (d) and ends when the verification of the digital integrated circuit.

Description

METHOD AND SYSTEM FOR DESIGNING, SIMULATING AND DEBUGGING DIGITAL INTEGRATED CIRCUIT USING PROCEDURAL HIGH LEVEL PROGRAMMING LANGUAGES}

TECHNICAL FIELD The present invention relates to digital integrated circuit design, and more particularly, to a method for designing, simulating, and verifying digital integrated circuits using a sequential execution advanced programming language.

The development of ASIC chips, as well as general-purpose processors, is a complex task that requires a lot of time and a lot of human resources in different fields. In the development order, the system engineer first develops and verifies the algorithm. The hardware engineer then implements and validates the algorithm at the register transfer level (RTL) using a hardware description language (HDL) tool, such as VHDL, and then uses a gate-level net using a synthesis tool. Synthesize into a list (netlist). Hardware engineers place and route the synthesized circuitry to create a layout that will actually be on the chip, and program it into a field programmable gate array (FPGA) to perform operational tests and verifications. Afterwards, the semiconductor process engineer implements the layout on the actual semiconductor wafer, and the test specialist tests the finished chip.

Among these, netlist synthesis, PNR, layout generation, FPGA programming, and semiconductor chip manufacturing are largely automated. However, algorithm development, test vector development, simulator development, architecture development, and HDL coding / debugging are very time-consuming because engineers must do it themselves. If problems are found in later processes, algorithms or architectures need to be modified, which contributes to project prolongation.

On the other hand, algorithms are typically written in sequentially executed code, and system engineers are typically accustomed to writing algorithms in sequential high-level programming languages such as C and C ++. Typically, test simulations are written in sequential execution languages such as C or C ++. On the other hand, the system architecture is written in HDL codes designed to execute the operation of logical blocks concurrently. The syntax of HDL that hardware engineers are familiar with is different from language grammar such as C or C ++, so communication between hardware engineers and system engineers is not smooth, and the developed and verified algorithms cannot be implemented in hardware to match all aspects. It is known that it is often produced in time without being fully tested.

Attempts to resolve the lack of communication between system engineers and hardware engineers could be approached in two ways. One is for a system engineer, for algorithms written in sequential execution languages such as C or C ++, either to HDL format (C-to-Verilog conversion tool), or to netlist synthesis directly without going through HDL coding (SystemC). , ImpulseC) and, moreover, the approach to implementing hardware architectures automatically (TLM, CatapultC) from algorithms. The other approach is to provide systems engineers with the tools to understand the hardware architecture design and write clocked algorithms.

Each approach has its pros and cons, and the C-to-Verilog conversion tool is limited to automating the conversion behavior, leaving it at a simple translation level. SystemC or ImpulseC is a tool that simulates the compilation of clocked C ++ algorithms. A complex and sophisticated kernel and data store control algorithms and variables. It's still too late to use, there are many limitations in using special compilers, variable declarations, data type declarations, etc., it's hard to track the behavior of algorithms, making it difficult to fix algorithms, hard to understand by hardware engineers, and finding and fixing hardware errors. And revalidation procedures can be lengthy.

The problem to be solved by the present invention is to provide a method of using a C or C ++ language widely used as a high-level programming language while having a syntax similar to that of an HDL language such as verilog or VHDL to design and verify a digital integrated circuit. It's there.

Method for simulating and verifying a digital integrated circuit such that one or more logics and one or more registers each operate according to one or more clocks using a sequential execution advanced programming language in accordance with an aspect of the present invention for solving the above problems. silver,

(a) activating at least one clock edge of the clock edges of the clock in an application order of each clock edge;

(b) updating the output variables of all registers by the value of the input variables of each register, respectively;

(c) sequentially executing operations of respective logics;

(d) updating input variables of registers operating in correspondence with the activated at least one clock edge with results provided from the respective logics and registers, respectively; And

(e) repeating the iterations of (a) to (d) until the verification of the digital integrated circuit is completed.

Advantageously, the iteration may begin with the activation of a clock edge of at least one of the clock edges and end before the next clock edge of at least one of the clock edges is activated.

Advantageously, step (b) must be performed before step (c) if the operation of each of the logics of step (c) is affected by the value of the output variables of the respective registers. Can be.

Advantageously, step (c) must be performed before step (d) if the input of each register of step (d) is affected by the value of the output variables of the respective logics. Can be.

Advantageously, in step (d), operation results provided to registers which do not correspond to the activated at least one clock edge among the operation results of the operation performed in step (c) may be discarded. have.

In accordance with another aspect of the present invention, a digital integrated circuit may be configured such that one or more logic, one or more registers, and one or more sub-function modules contained within a top-level function module operate in accordance with one or more clocks using a sequential execution advanced programming language. How to simulate and verify,

(I) activating at least one clock edge of the clock edges of the clock in the order of application of each clock edge;

(II) updating the output variables of all the registers defined in the top-level function module with the values of the input variables of the respective registers, respectively;

(III) sequentially executing operations of logic in the most significant function module;

(IV) updating input variables of the registers defined in the top-level function module, the registers operating in correspondence with the activated at least one clock edge, by results provided from the respective logics and registers, respectively;

(V) calling and executing the one or more sub function modules;

(VI) repeating the iterations of (I) to (V) until the verification of the digital integrated circuit is terminated.

Advantageously, the iteration may begin with at least one clock edge of the clock edges of the clock being activated and end before the next clock edge of at least one of the clock edges of the clock is activated.

Preferably, the step (II) is necessarily performed if the operation of each logic and sub function module of the step (III) is affected according to the value of the output variables of the respective registers. It may be done earlier.

Preferably, in step (IV), among the calculation results of the operation performed in step (III), calculation results provided to registers which do not correspond to the activated at least one clock edge may be discarded.

Simulation and verification method of the digital integrated circuit,

Prior to step (I), before entering the iteration, set whether the verification of the digital integrated circuit is a floating-point or fixed-point arithmetic verification, and thereby define the input variables and output variables of the wire variables and registers. It may further comprise the step.

Preferably, the step (V) is,

Updating the output variable values of all registers defined in the sub function module with the input variable values of the respective registers;

Sequentially performing operations of logic in the sub function module; And

Operates in response to the activated at least one clock edge among registers defined in the top-level function module connected to the logic or register output defined in the sub-function module and registers defined in the sub-function module. And updating the input variable of the registers according to the operation results of the respective logical operation syntaxes.

Preferably, the high level programming language is a C ++ language,

Simulation and verification method of the digital integrated circuit,

Prior to step (I), before entering the iteration, set whether the verification of the digital integrated circuit is floating point arithmetic or fixed point arithmetic verification, and the wire variables and register input variables to be used in the top-level function module and Further defining output variables,

If the current iteration is the first iteration to perform the sub function module to be called in the step (V), prior to the step (V), the method may further include instantiating the sub function module classes written in the C ++ class. Can be.

Preferably, the step (V) is,

If the current iteration is the first iteration to perform a lower subfunction module, instantiating the lower subfunction module classes written in a C ++ class prior to calling the lower subfunction modules; And

The method may further include calling and executing the lower sub function module.

Preferably, the high level programming language is C language,

Simulation and verification method of the digital integrated circuit,

Prior to step (I), the method may further include defining input variables and output variables of all wire variables and registers to be used in the top-level function module and sub-function modules before entering the iteration.

Preferably, the step (V) is,

Updating output variable values of all registers defined in the sub function module with input variable values of respective registers;

Sequentially performing operations of logics in the sub function module; And

Corresponding to the activated at least one clock edge among the registers defined in the uppermost function module and those connected to the logic or register output defined in the subfunction module and those defined in the subfunction module. Updating the input variable of the operating registers according to the operation results of the respective logics.

According to another aspect of the present invention, a method for simulating and verifying a digital integrated circuit such that one or more logics and one or more registers respectively operate according to one or more clocks using a sequential execution advanced programming language,

(A) activating at least one clock edge of the clock edges of the clock in the order of application of each clock edge;

(B) updating the output variables of the registers corresponding to the activated at least one clock edge by the value of the input variables of the respective registers, respectively;

(C) sequentially executing operations of respective logics;

(D) updating input variables of all the registers respectively with the respective logics and results provided from registers; And

(E) repeating the iterations of (a) to (d) until the verification of the digital integrated circuit is completed.

In accordance with another aspect of the present invention, a method of designing, simulating, and verifying a digital integrated circuit such that one or more logics and one or more registers respectively operate according to one or more clocks using a sequential execution advanced programming language,

For the operation of the respective logics, the syntax in which the output variables of the registers input to each logic are updated by the value of the input variables of the respective registers is located before the operation syntax of each logic, and the input variables of the registers Receiving the phrases through a high-level programming language input such that the syntax, each updated by the arithmetic results provided from the respective logics, is located after the operational syntax of each logic; And

It may include the step of making the input syntax to an executable file through an advanced programming language compiler.

Using embodiments of the present invention, it is possible to design and verify digital integrated circuits using syntaxes similar or substantially identical to HDL languages such as beryllog or VHDL using C or C ++ languages. The simulation time is much shorter, error detection and correction is convenient, and accessible to both system engineers and hardware engineers, greatly reducing development time.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

Although the present invention can be applied at various levels ranging from printed circuit boards (PCBs) to electronic systems as well as digital integrated circuits, the present specification mainly illustrates digital integrated circuits for convenience of description.

Although the present invention can be applied at various levels ranging from printed circuit boards (PCBs) to electronic systems as well as digital integrated circuits, the present specification mainly illustrates digital integrated circuits for convenience of description.

Although the present invention can be applied to digital integrated circuit design using various high-level programming languages, for the sake of convenience of description, the present disclosure mainly illustrates a method of designing, simulating, and verifying in a high-level programming language such as C or C ++. 1B is a block diagram illustrating a conventional simple digital integrated circuit, and FIG. 1B conceptually illustrates the premise for applying a design methodology of a digital integrated circuit using an advanced programming language to the digital integrated circuit of FIG. 1A according to an embodiment of the present invention. FIG. 1C illustrates that the design methodology of a digital integrated circuit using an advanced programming language according to an embodiment of the present invention can be applied to the digital integrated circuit of FIG. 1A even when different clocks are used. Timing diagram.

Referring to FIG. 1A, an example digital integrated circuit includes logic circuit A and logic circuit B. FIG.

Conventionally, when an integrated circuit is implemented in a hardware description language (HDL), variables such as clock signals, input / output of logic circuits, storage bits of registers, as well as wires connecting them to each other are used as variables. Specifies a circuit network in which logic circuits and registers are connected by wires. In the design using HDL, if only the connection of components is accurately described in HDL, the HDL compiler and simulation tool automatically abstracts the behavior of the hardware over time (application of clock signal).

Combinational logic circuits have a characteristic that an output value according to a logic operation is output when an input value changes regardless of a clock signal, and does not include a storage means. At this time, the output value changes after a very short time delay after the input value change. On the other hand, registers are used as storage space because the output value changes according to the input value or clock application, and the value is maintained until the condition changes. There are two main types of registers used: edge triggered D flip-flop, which changes the output value at the edge of the clock, and a latch that changes the output value immediately according to the input value. latch) type.

In general, since a logic circuit is operated by inputting output values of external logic circuits, external input values, stored values of registers, or the like, the values input to the logic circuits and output values to express the logic circuits in a program syntax. Are each defined and used as variables. On the other hand, registers generally store the operation results of logic circuits and their stored values are input to other logic circuits, so that the stored values are defined and used to represent registers in program syntax.

Similarly, in HDL, combinatorial logic circuits are described as 'logic circuit syntax', which is a set of syntaxes that correspond to the operation of the logic circuit, and clock signals, outputs of registers and wires declare and use their values as variables. . When the logic value of the output or wire of the logic circuit in front of the register is input to the register, it is the value output from the register, so the register is represented by one storage space, or one variable.

In FIG. 1A, when a cycle of clock is applied, logic circuit A and logic circuit B each receive the output of the previous register and other input values, and after the completion of their logic operation before the clock ends, the operation result value. To the resistor input terminal D, respectively. Each register stores logic operation result values. This process is repeated. That is, when the clock of the next cycle is subsequently applied, the logic circuits A and B each receive the previous operation result value stored in the previous register and repeat the logic operation.

Specifically, the hardware level operation of the circuit illustrated in FIG. 1A will be described. After the logic operation, the logic circuit A receives the input value IN_A1 and the first output value OUT_B0 output from the register B at the time of applying the clock 1, and after a logic operation. Gives output OUT_A1. The output OUT_A1 is settled and applied to the input terminal D of register A before the end of one clock cycle.

Meanwhile, the logic circuit B receives the output OUT_A0 and the input IN_B1 of the register A output at the time of applying the clock 1 and outputs the output OUT_B1 after the logic operation. The output OUT_B1 is set before the end of one clock cycle and applied to the input terminal D of the register B.

Then, at the time of applying the clock 2, the registers A and B output the output values OUT_A1 and OUT_B1 at their respective output terminals Q, and maintain the values of the output OUT_A1 and the output OUT_B1 throughout the period of the clock 2. With the application of clock 2, logic circuit A receives input value IN_A2 and output value OUT_B1 from register B and outputs output OUT_A2 after logic operation. The logic circuit B receives the output OUT_A1 and the input IN_B2 of the register A output according to the application of the clock 2 and outputs the output OUT_B2 after logic operation.

Outputs OUT_A2 and OUT_B2 are settled before the end of clock 2, respectively, and applied to respective input terminals D of registers A and B.

Registers A and B then retain the value of output OUT_A2 and the value of output OUT_B2 at each output terminal Q, from the beginning of clock 3, through the period of clock 3.

To represent the simulation operation of such an integrated circuit written in HDL together with a clock signal, the operation of hardware according to application of a clock is simulated in such a manner that the algorithm is iterated once.

At this time, iteration is performed by mimicking actual hardware operation during the clock period from immediately after the edge of the current clock to just before the edge of the next clock. Here, suppose the transition of the clock is very short and immediate.

For example, in clock interval 1, iteration of a simulation written in HDL begins with each logic circuit syntax A and B loading input values, so that after the logic circuit syntax A and B is driven, the operation result is This ends with the operations stored in register variables A and B, respectively. In the following clock interval 2, the second iteration also begins by reading the values of register variables A and B and the external input values from logic circuit syntaxes A and B, respectively, so that the result of the operation of logic circuit syntax A and B is register variable respectively. Ends with being stored in A and B

Hardware engineers who describe hardware using these conventional HDLs do not have to worry about the order in which the components are described because the HDL compiler strictly manages the behavior and variables of the components over time.

However, a system engineer using a sequential high-level programming language such as C or C ++ will be able to mimic HDL with a high-level programming language such as C or C ++ because program syntaxes compiled in the high-level programming language operate in the order described. In order to describe the hardware as above, programming statements should always be written keeping in mind the order of operation in time.

For example, register variable B is used redundantly in two or more combinational logic circuit constructs (the output of logic circuit syntax A and the input of logic circuit syntax B), so that the current operation of the preceding logic circuit syntax A is finished. Must be updated and called in logic circuit syntax B on the next operation. Therefore, if you want to program the updating and calling of registers in the C or C ++ language, the engineer must be very careful about the logic circuit syntax or the order in which the statements about the registers are placed. In reality, however, combinatorial logic circuits and registers are intricately intertwined, making it virtually impossible for an engineer to program without errors, taking into account the order of operation.

FIG. 1B is a prerequisite for applying a method of designing and verifying a digital integrated circuit according to an embodiment of the present invention, in which a system engineer can describe hardware in an advanced programming language such as C or C ++ without considering a sequence of operations in time. Explain.

Referring to FIG. 1B, a digital integrated circuit that is substantially similar to FIG. 1A is illustrated. However, in FIG. 1A, the register is represented by one variable, whereas in FIG. 1B, the values of the input terminal D and the output terminal Q of the register are declared and used as variables, respectively.

The start and end of the iteration are also different from those of FIG. 1A. In the prior art of FIG. 1A, iteration starts immediately after a clock is applied, and one iteration is a concept of proceeding with a logic operation, storing a logic operation result in a register variable, and terminating the current clock. In contrast, in the present invention of FIG. 1B, iteration is a concept that proceeds to applying a current clock, updating an output variable of a register, performing a logic operation, and storing a logic operation result in a register input variable.

Furthermore, in the conventional HDL or a simulation written in a high-level programming language that mimics the same, as shown in FIG. 1B, unlike the limitation of the operation order by using one register variable for one register and strictly managing all register variables, Iteration, written in the high-level programming language of the simulation of the invention, separates registers into register input variables (variables for the operation results of the previous logic circuit) and register output variables (variables for input to the next logic circuit). This abstraction eliminates the need to strictly manage register variables.

In the simulation of the present invention, when the current iteration is started, a clock is applied and the input variables of the respective registers (the operation results of each preceding logic circuit syntaxes were stored in the input variables of the respective registers during the previous iteration). Depending on the value, the output variables in each register are updated. Thus, after the output variables of each register are updated, the operation syntax of logic that takes such output variables as input is executed.

In other words, before the codes in the logic circuit statements are executed, the output variables of all the registers used as input of those logic circuit statements must be updated with the input variables of the register at the previous iteration. The result of the calculation of each logic circuit syntax is stored in the input variable of the back registers just before the next clock is applied. The current iteration ends here, and the next iteration is repeated immediately.

In Fig. 1B, the output values Q of the registers A and B are updated by the input values D of the registers A and B of the immediately preceding iteration, immediately after the clock is applied. Thus, subsequent logic circuits A and B can receive the output values of the latest registers A and B and operate as desired. Immediately before the next clock application, the results of the computation of logic circuits A and B are stored in inputs D of registers A and B, respectively.

Thus, in the simulation occurring in FIG. 1B, it is ensured that all registers applied to the input of the logic circuits store and output the latest values before the logic circuits in the integrated circuit enter each operation.

In addition, since each of these operations takes place sequentially, the system engineer can describe the configuration of the integrated circuit at the RTL level corresponding to this operation sequentially using a high-level programming language, as if writing a software algorithm.

Referring to Fig. 1C, when the clock A is applied to the register A and the clock B is applied to the register B, the timing of the signal applied to the input terminals of the registers A and B is illustrated.

Clock B is, for example, a clock having a frequency corresponding to twice the frequency of clock A. Clock B may or may not be a multiple of clock A. Typically, when the two clocks are not a multiple, the additional hardware configuration, such as a buffer, is required between circuits to which different clocks are applied to achieve the desired operation no matter what the relative edge positions of the two clocks are.

However, the simulation of the integrated circuit desired in the present invention is not to verify that the integrated circuit is physically operated at the device level, but to logically and abstractly verify that the integrated circuit is operated at the register and logic circuit levels. Therefore, the simulation of the present invention may not include additional hardware configuration to cope with clock asynchronous.

Note that Figure 1C does not reflect the actual physical time, but rather logically decomposes and combines the operations that take place at the edge of the clock. For example, updating the register output, logic operation, and updating the register input all take place sequentially during the short time that the clock edge is applied.

In Fig. 1C, for example, a 40 MHz clock A is applied to register A and an 80 MHz clock B is applied to register B.

At the time T1, it is understood that clocks A and B are both rising edges, so that both clocks A and B are applied. According to T1, the operation of registers A and B and logic circuits A and B is performed instantaneously.

At the time T1a, the output variables of registers A and B are both updated by the input variable values of each register A and B (i.e., the values input to each register at the previous clock). In the period T1b, the programming codes of logic circuit syntaxes A and B are driven.

At time T1c, since both clock A and clock B are applied at T1, both input variables of registers A and B are updated according to the operation result of logic circuit syntaxes A and B, respectively.

Only the edge of clock B is applied at time T2. At time T2a, the output variables of registers A and B are once again updated by the input variable values of registers A and B respectively.

In the period T2b, the programming codes of logic circuit syntaxes A and B are driven. The input variable in register B is updated by the operation result of logic circuit B. However, since clock A is not applied at time T2, the result of the operation of logic circuit syntax A performed in the period T2b is discarded without being input to the input variable of register A in T2c.

Subsequently, clocks A and B are applied at the time T3, and the operation of the interval between T1-T2 at T3a, T3b, and T3c is repeated.

As described above, an operation in which the input value of the register is transferred to the output value of the register and the output value of the register is updated to the latest value should be performed before the operation of the next logic circuit. In addition, the output value of the updated register must be maintained until the input value of the register is newly updated and the next clock is applied.

Therefore, in one embodiment of the present invention, the output update operation of the register is performed if any clock signal is applied, even if the clock is not applied to the corresponding register. On the other hand, the operation of the logic circuit is transferred to the register input value and the register input value is updated only at the edge of the clock applied to the register.

Alternatively, in another embodiment of the present invention, during one iteration, the register's output variable is updated only when the clock associated with its register operation is applied, while the register's input variable is always updated before the iteration ends. You can also For example, in the application of clock B at time T2, the output variable of register A is not updated unless clock A is applied. However, at time T2c, the input variable of register A is updated according to the operation result of logic circuit A.

In another embodiment of the present invention, T2b may not perform the operation of logic circuit syntax A, whose result is to be discarded anyway. In this case, however, a slight simulation speed increase may be expected, but an algorithm for determining whether to execute logic circuit statements at different clock frequencies may be required regardless of the actual hardware configuration.

Through these methods, embodiments of the present invention can maintain the consistency of the design and verification method even in integrated circuits with different clock frequencies.

2 is a flowchart schematically illustrating a digital integrated circuit design and verification method using an advanced programming language according to an embodiment of the present invention.

Referring to FIG. 2, a digital integrated circuit design, simulation, and verification method using an advanced programming language is achieved by iterations of the following steps S21 to S24.

In the present invention, iteration is a unit of repetitive execution that logically abstracts the operation of real hardware. In this case, when one clock is used, the iteration coincides with a clock period of one period. However, in the case of using a plurality of different clocks, iteration is an interval from the time when an edge of one of the clocks is applied to the time when the edge of any clock is applied first.

An integrated circuit consists of input terminals, output terminals, clock signals, multiple hardware blocks, logics, wires, registers. One hardware block is represented by one function module. The function module includes logics and variable registers for implementing the algorithm that the hardware block performs. Hardware blocks are connected to each other only through at least one register. The registers operate in accordance with one of the respective clock signals, store the operation result of the respective logic and hardware blocks, and are abstracted as input and output variables, respectively. In addition, input terminals, output terminals, clock signals, logics, and wires are each abstracted as one variable.

In step S21, at least one clock edge of the one or more clock edges is activated based on the order in which each clock edge appears.

The clock signal uses a rising edge or a falling edge or both edges, where the expression "clock edge is activated" indicates that the rising edge or falling edge is applied to the integrated circuit, e.g. C In high-level programming languages such as C ++, you can abstract them by incrementing a clock variable, for example using a for statement, or by conditional iteration using a while statement.

Iteration may be repeated based on when there is a clock edge applied to any clock edge. At the start of each iteration, multiple clock edges of the one or more clock edges may be activated simultaneously, or only one clock edge may be activated. For example, if clock 1 is 40 MHz, clock 2 is 80 MHz, and clock 3 is 120 MHz, then clock edges 1, 2, and 3 are all active in the first iteration, clock edge 3 is the third in the second iteration, and Clock edge 2 in the iteration, clock edge 3 in the fourth iteration, and clock edges 1, 2, and 3 are activated in the fifth iteration, respectively.

Preferably, the one or more clocks are in multiples of one another. However, even if not a multiple relationship, there is no problem in performing iteration if the edges of the edges between the one or more clocks are clear. However, there may be a case where an integrated circuit designed so realistically that the gaps between the edges having clear front and back sides are too small to guarantee normal operation, but this may be considered in the logical design and operation verification stage according to the embodiments of the present invention. It's not a problem.

In step S22, the output variables of all the registers are respectively updated by the values of the input variables of the respective registers.

If this is the first iteration, then the value of the input variable in each register will be 0 or the default value, and the value of this input variable is passed to the output variable in that register. If it is not the first iteration, the value of each register's input variable will contain the result of the previous iteration, and the value of this input variable is passed to the register's output variable.

After the output variables of all the registers are updated in this way, in step S23, the operation syntax of the logics is executed sequentially. Here, the meaning of "sequentially executing" is based on a characteristic of sequentially executing a syntax in a high-level programming language used in a digital integrated circuit, and the present invention sequentially processes the operation syntax of logics as described herein. In spite of the implementation, it is possible to simulate the simultaneous operation of the clock across the digital integrated circuit.

In the simulation and verification method of the present invention, the input and output variables of the register are used to connect any two logic. These I / O variables must be predefined in the parent function module that calls both logic. The input variable of a register can be updated by the operation result of one logic, and the output variable of that register can be used as input to several other logics, respectively.

For example, if a result value is to be passed from the first logic to the second logic, the result to be delivered is once carried in an input / output variable of a register defined or declared in the upper function module of these two logics. First, at the first clock edge, the execution result of the first logic is stored in an input variable of the register. At the second clock edge, the output variable of the register in the upper function module is updated by the value of the input variable. The resulting value to be passed can then be used until the second logic calls the updated output variable of the register. If the input / output variables of the registers that serve as the interface of the two logics are defined in the upper function module, and the second logic is executed after storing the result value to which the output variable of the register is passed, the normal operation of the second logic is guaranteed. As such, the operation syntax of the first logic and the operation syntax of the second logic are as long as the updating operation of the register output variable connecting the two logics is satisfied before the operation operation of the logic using the output variable for operation. The side can be executed first.

Thus, if there are any two logic separated by registers, the description order between the logic separated by the registers within one iteration, since the two logics do not affect the operations on each other during the operation within one iteration. And execution order does not matter.

However, a number of logics (ie, logic with no registers between them) between an external input and a register, or between a register and some other register, respectively, are output from the input side. Since they must be executed sequentially, they must be described in the order of execution of such logics.

Furthermore, there may be a function module that does not necessarily have to be performed in the iteration. For example, in the previous example, if a function module is connected to a register set to operate at 40 MHz, each result computed in the first, second, and third iterations is discarded without being stored in the corresponding register input, In these iterations, no operation is required. This function module can be used only when the operation is performed correctly only in the fourth iteration and the result of the operation is stored in the register input, and the register input value is updated to the register output in the fifth iteration. Overall normal operation can be guaranteed. In this case, if the operation is not performed in the first, second and third iterations, the simulation speed may increase.

As such, after operation of each logic is performed in step S23 and respective operation result values are generated, in step S24, the operation result values are stored in an input variable of respective registers connected to the respective logics, or Or discarded.

In other words, in step S24, the input variables of the registers operating in correspondence with the activated at least one clock are updated by the operation result values calculated in logic, and the input variables of the registers not otherwise are not changed.

Specifically, in step S241, it is determined whether the register to which the operation result of the logic is applied corresponds to the activated at least one clock edge. If so, then in step S242 the operation result of the logic is stored in an input variable of the register. If not, the operation result of the logic is discarded in step S243.

At this point, the input variable of the registers stores the result of the current iteration, but the output variable is updated with the start of the current iteration. In other words, within an iteration, the input and output variables of registers may have different values.

Thus, the iteration ends, and in step S25, it is determined whether all the iterations are terminated, and if there is still an iteration to be performed, the process proceeds to step S21 to perform the next iteration. . If all iterations are terminated, terminate the simulation.

3 is a flowchart schematically illustrating a digital integrated circuit design and verification method using an advanced programming language according to another embodiment of the present invention.

Referring to FIG. 3, a digital integrated circuit design, simulation and verification method using an advanced programming language is performed by iteration of iterations consisting of steps S31 to S34.

In step S31, at least one clock edge of the one or more clock edges is activated based on the order in which each clock edge appears. At the start of each iteration, multiple clock edges of the one or more clock edges may be activated simultaneously, or only one clock edge may be activated.

In step S32, the output variables of the registers operating corresponding to the at least one clock edge activated in step S31 of the registers are respectively updated by the values of the input variables of the respective registers.

If this is the first iteration, then the value of the input variable in each register will be 0 or the default value, and the value of this input variable is passed to the output variable in that register. If it is not the first iteration, the value of each register's input variable will contain the result of the previous iteration, and the value of this input variable is passed to the register's output variable.

For each register, if an active clock edge is not applied to any register in the current iteration, then the output variables in that register maintain the value in the previous iteration in the current iteration.

After the output variables of the registers corresponding to the activated clock edge are updated, in step S33, the operations of the logics are sequentially executed.

The logic changes its output by a previous register that yields a changed output value only when the clock edge is activated. If the clock edges applied to the previous registers as well as the input in that iteration are not active, the output of that logic will not change. Thus, although the logic is a combinatorial logic circuit, it is in fact determined whether the logic operates in accordance with the activation of the clock edge. If so, only the output variables of the registers whose clock edges are active in the current iteration are updated, and the output variables of the registers whose clock edges are disabled do not change, but the logic can receive the proper input and operate correctly.

Thus, as in the case of Fig. 2, the logics can be described without worrying about the order, as long as the update operation of the register output variable is preceded by the operation operation of the logic using the output variable for operation.

After operation of each logic is performed in step S33 and respective operation result values are generated, in step S34, the operation result values are stored in input variables of all registers included or connected in the respective logics. .

In step S24 of FIG. 2, only an input variable of a register operating in response to an activated clock edge is updated, whereas step S34 of FIG. 3 is based on an output value of logic in which an input variable of all registers is preceded. Is updated.

Thus, the iteration ends, and in step S35, it is determined whether all of the iterations are terminated. If there is still an iteration to be performed, the flow proceeds to step S31 to perform the next iteration. If all iterations are terminated, terminate the simulation.

4 is a flowchart illustrating a digital integrated circuit design and verification method using an advanced programming language according to another embodiment of the present invention.

Referring to FIG. 4, it can be seen that the description order of the function modules in the present invention does not affect the simulation.

The simulation of FIG. 4 is performed by repeating the iterations made up of steps S41 to S44n.

In step S41, at least one clock edge of the one or more clock edges is activated based on the order in which each clock edge appears. The activation of the clock edge is substantially similar to that described with reference to FIG. 2, and thus description thereof is omitted.

In step S42, the output variables of all the registers are respectively updated by the values of the input variables of the respective registers.

If this is the first iteration, then the value of the input variable in each register will be 0 or the default value, and the value of this input variable is passed to the output variable in that register. If it is not the first iteration, the value of each register's input variable will contain the result of the previous iteration, and the value of this input variable will be passed to the register's output variable.

In step S43a, the operation syntax of the first logic is executed sequentially. In step S44a, the input variable of the register connected to the first logic is updated according to the operation result of the first logic.

In step S43b, the operation syntax of the second logic is executed sequentially this time. Subsequently, in step S44b, the input variable of the register connected to the second logic is updated according to the operation result of the second logic.

In step S43n, the operation syntax of the nth logic is executed sequentially. In step S44n, the input variable of the register connected to the n-th logic is updated according to the operation result of the n-th logic.

Thus, the iteration ends, and in step S45, it is determined whether all of the iterations are terminated. If there is still an iteration to be performed, the flow advances to step S41 to perform the next iteration. If all iterations are terminated, terminate the simulation.

At this time, the syntaxes of the first logic, the second logic to the n-th logic, the output variables of the registers associated with each logic is updated prior to the valid operation operation of each logic, and each operation result is completed when each valid operation operation is completed. It can be described, called, and executed in any order, as long as the rules for storing them in the input variables of each register are followed.

This property is similarly observed between the respective functional modules containing the logic. Thus, in accordance with the present invention, the syntaxes of the functional modules may be described, for example, in an algorithmic logic structure order for the system engineer to understand, but for example the spatial arrangement order of the functional modules for the hardware engineer to understand. It may be described as it is.

5A and 5B are flowcharts illustrating a method for designing and verifying a digital integrated circuit using the C ++ language according to an embodiment of the present invention.

Typically, in the case of integrated circuits that require complex and various kinds of function operations, system engineers describe various sub-function modules as needed in one top-level function module. The top module consists of a combination of one or more logics, one or more registers, and one or more sub function modules. A sub function module can nest other sub function modules within it.

5A and 5B, FIG. 5A is a flowchart of a top-level function module written in C ++, and FIG. 5B is a flowchart of a sub-function module written in a class of C ++ called from the top-level function module.

In FIG. 5A, the simulation is performed by repeating the iterations composed of steps S51 to S55.

In step S51, at least one clock edge of the one or more clock edges is activated based on the order in which each clock edge appears. The activation of the clock edge is substantially similar to that described with reference to FIG. 2, and thus description thereof is omitted.

In step S52, the output variables of all the registers defined in the top function module are respectively updated by the values of the input variables of the respective registers.

If this is the first iteration, then the value of the input variable in each register will be 0 or the default value, and the value of this input variable is passed to the output variable in that register. If it is not the first iteration, the value of each register's input variable will contain the result of the previous iteration, and the value of this input variable is passed to the register's output variable.

In step S53, the operation syntax of the uppermost function module is executed sequentially.

In step S54, the input variables of the registers operating in correspondence with the at least one clock edge activated in step S51 are respectively updated according to the operation result of the uppermost function module.

In step S55, if the top function module includes the sub function module, the included at least one sub function module is called. For example, in FIG. 4, a single large C ++ file including all n function modules is included. In FIGS. 5A and 5B, the top-level function module is included in the top-level file, and the remaining function modules are written separately in each file. This is how it is called in the top-level function module. Subsequently, when the operation of the called sub-function modules is completed, the sub function module returns to the top function module, and the flow proceeds to step S56.

In this way, the iteration ends, and in step S56, it is determined whether all the iterations are terminated. If there is still iteration to be performed, the flow proceeds to step S51 to perform the next iteration. If all iterations are terminated, terminate the simulation.

Referring to FIG. 5B, when a sub function module is called in step S55 of FIG. 5A, in step S551, output variable values of all registers defined in the sub function module are updated as input variable values of respective registers. .

In operation S552, logic operation syntaxes that operate by receiving an output variable of each register are sequentially performed.

In step S553, the input variable of the registers connected to the respective logic operation statements operating in correspondence with the at least one clock edge activated in step S51 is updated according to the operation results of the respective logic operation statements. .

In step S554, if the sub function module includes the sub sub function module again, the sub sub function module may be called.

Subsequently, when the operation result of the lower sub function module returns and the operation of the sub function module ends, the operation result is returned to the upper function module (in this case, the highest function module) in which the sub function module is called.

As with the embodiment of FIGS. 2-4, in the embodiments of FIGS. 5A and 5B, the syntaxes of the top-level function module and the sub-function modules also indicate that all of the output variables of the registers associated with each logic are valid for the valid operation of each logic. Once updated and each valid computational operation has ended, they can be described, called, and executed in any order, as long as the rules that each computational result is stored in the input variable of each register are followed. This feature can also be applied between functional modules.

6A and 6B are flowcharts illustrating in more detail a method for designing and verifying a digital integrated circuit using the C ++ language of FIGS. 5A and 5B according to an embodiment of the present invention.

Referring to FIG. 6A, the simulation in FIG. 6A is performed by repeating the iterations composed of steps S63 to S68.

In step S61, before the start of iteration of the simulation, it is set whether to simulate the calculation level of the simulation, for example, floating point calculation or fixed point calculation. The type of variables and calculations used in the simulation are determined by the setting of this step S61.

On the other hand, in general, fixed-point arithmetic is faster but less accurate, while floating-point arithmetic is slower but more accurate. According to the present invention, if a template of C ++ is used, fixed-point simulation and non-point-simulation simulation can be simultaneously run in parallel in one simulator, and further, the optimum design can be easily and quickly found while contrasting the two simulations.

In step S62, wire variables and register variables included in the top-level function are defined.

In step S63, iteration starts and at least one clock edge of the one or more clock edges is activated based on the order in which each clock edge appears. The activation of the clock edge is substantially similar to that described with reference to FIG.

In step S64, the output variables of all the registers defined in the top function module are respectively updated by the values of the input variables of the respective registers.

If this is the first iteration, then the value of the input variable in each register will be 0 or the default value, and the value of this input variable is passed to the output variable in that register. If it is not the first iteration, the value of each register's input variable will contain the result of the previous iteration, and the value of this input variable is passed to the register's output variable.

In step S65, the operation syntax of the uppermost function module is executed sequentially. In step S66, the input variables of the registers operating in correspondence with the at least one clock edge activated in step S63 are respectively updated according to the operation result of the uppermost function module.

In step S67, prior to calling the sub function modules when the iteration is the first iteration to perform the sub function module to be called in the next step, the sub function module classes written in the C ++ class are instantiated. .

In step S68, the sub function modules are called, and when the operation of the called sub function modules is completed, the sub function module returns to the top function module.

Here, the iteration ends, and in step S69, it is determined whether all the iterations are terminated. If there is still iteration to be performed, the flow proceeds to step S63 to perform the next iteration. If all iterations are terminated, terminate the simulation.

Subsequently, referring to FIG. 6B, for the sub function module written in the C ++ class called in step S68 of FIG. 6A, the output variable values of all the registers defined in the sub function module in step S681 may be determined. Update with an input variable value.

In operation S682, logic operation syntaxes that operate by receiving an output variable of each register are sequentially performed.

In step S683, the input variable of the registers connected to the respective logic operation statements operating in correspondence with the at least one clock edge activated in step S63 is updated according to the operation results of the respective logic operation statements. .

In step S684, prior to calling such subordinate subfunction modules when the iteration is the first iteration to perform another subfunction module to be called in the next step, the child subfunction module written in the C ++ class. Instantiate classes

In step S685, the lower sub function module may be called.

Subsequently, when the operation result of the lower sub function module is returned and the operation of the sub function module is completed, the operation result is returned to the higher function module (in this case, the highest function module) in which the sub function module is called.

7A and 7B are flowcharts illustrating a method for designing and verifying a digital integrated circuit using the C language, according to another embodiment of the present invention.

7A and 7B, unlike the C ++ language illustrated in FIGS. 6A and 6B, the C language is used. Unlike C ++, C-language does not allow object-oriented programming using features such as classes and templates in C ++, but several techniques can achieve similar effects to instantiation in C ++. For example, create several C files with the same function syntax that you want to call repeatedly, each time calling the C file with a different name each time you need it. Furthermore, if the input and output variables of the registers in the calling function are defined as static, respectively, the values of the locally defined registers are retained after the function call ends, thus achieving a similar effect to instantiation in C ++. Can be. The following steps S71 to S76 illustrate the design and syntax verification method of the digital integrated circuit according to the present invention using the above-described tips.

In step S71, wire variables and register variables used in the top function module and the sub function module are defined in the top function.

In step S72, iteration begins and at least one clock edge of the one or more clock edges is activated based on the order in which each clock edge appears. The activation of the clock edge is substantially similar to that described with reference to FIG. 2, and thus description thereof is omitted.

In step S73, the output variables of all the registers defined in the top function module are respectively updated by the values of the input variables of the respective registers.

If it is the first iteration, then the value of the input variable of each register will be 0 or the default value, and the value of this input variable is passed to the output variable of that register. If it is not the first iteration, the value of each register's input variable will contain the result of the previous iteration, and the value of this input variable is passed to the register's output variable.

In step S74, the logic operation syntax of the uppermost function module is executed sequentially. In step S75, the input variables of the registers operating in correspondence with the at least one clock edge activated in step S72 are respectively updated according to the operation result of the uppermost function module.

In step S76, the sub function modules are called, and when the operation of the called sub function modules is completed, the sub function module returns to the top function module. At this time, the call of the sub function module and the declaration of the input variable and the output variable of the registers used in the sub function module are as described above.

Thus, the iteration ends, and in step S77, it is determined whether all the iterations are terminated. If there is still iteration to be performed, the flow proceeds to step S72 to perform the next iteration. If all iterations are terminated, terminate the simulation.

Subsequently, referring to FIG. 7B, for the sub-function module written with the C function called in step S76 of FIG. 7A, the output variable values of all the registers defined in the sub-function module in step S761 may be determined. Update with an input variable value.

In operation S762, logic operation syntaxes that operate by receiving an output variable of each register are sequentially performed.

In step S763, the input variable of the registers connected to the respective logic operation statements operating in correspondence with the at least one clock edge activated in step S72 is updated according to the operation results of the respective logic operation statements. .

In step S764, if necessary, the lower sub function module may be called. The called lower sub function module may perform the operations of steps S761 to S765.

Subsequently, when the operation result of the lower sub function module is returned and the operation of the sub function module is completed, the operation result is returned to the higher function module, that is, the highest function module, which is called.

FIG. 8 is a diagram comparing syntax written in a conventional hardware description language (HDL) with syntax written in an advanced programming language according to an embodiment of the present invention.

Referring to FIG. 8, the left side is a syntax according to Verilog's HDL, and the right side is a syntax according to an integrated circuit design and verification method according to an embodiment of the present invention.

You can see that the HDL statement on the left describes a hardware block after declaring a variable. The syntax according to the embodiment of the present invention on the right is using a C ++ class, which declares a variable, then defines an input / output port to and from the outside of the class, and describes a function module.

Syntax by HDL specifically defines register variables and wire variables, describes logic circuit syntax, and specifically defines the relationship between them by using register variables and wire variables within logic circuit syntax. The HDL compiler automatically manages the operation of logic circuit statements and register variables and wire variables according to the application of the clock edge, regardless of the description order between logic circuit statements.

Although the integrated circuit syntax designed in accordance with an embodiment of the present invention is written in a high-level programming language, it can be seen that it can be written in a similar order and structure as the HDL syntax on the left.

Therefore, by using the integrated circuit design and verification method according to an embodiment of the present invention, the advantage that the system engineer can develop the algorithm in a high-level programming language that is executed sequentially, the advantage of the operation tracking (tracking), error tracking and correction You can also enjoy the advantages of HDL, which allows you to write the syntax of the algorithm, while maintaining ease of use, without reflecting the order of description between the functional modules and reflecting only the connection relationship in hardware design.

In fact, by applying the embodiments of the present invention to simulate the process of developing a PHY of the wireless modem and compared with the conventional experience, it was as Table 1 below.

division 802.11a
(54 Mbps) 802.11b
(11 Mbps) 802.11 pre-11n
(216 Mbps) Nola
(3.6 Gbps) Algorithm engineer 4 people 4 people 0 people 3 people RTL Engineer 4 people 3 people 2 people 1 person Algorithm + RTL
engineer 0 people 0 people 4 people 2 people Total development period 12 months 12 months 13 months 16 months Rain of gates One 0.7 5 60 The amount of work committed One 0.9 1.5 3

Referring to Table 1, the IEEE number of gates of the IEEE 802.11a PHY, which developed the algorithm in C and designed the hardware in Beryllogue, and the amount of work done to achieve the maximum speed of 11 Mbps, respectively, For 802.11b, the gate count was 0.7x and the amount of work devoted to achieving the highest speed of 54 Mbps was 0.9. Each took four months for four algorithm developers and three RTL developers.

On the other hand, when the integrated circuit design and verification method of the present invention predicted the development time of the IEEE 802.11 pre-11n, which designed algorithms and hardware and converted to beryllogue, the gate count was five times and the maximum speed was 216. The amount of work required to complete the development of Mbps chips was 1.5 times, but the total development period was 13 months, with 2 RTL development personnel and 4 manpower for developing both algorithm and RTL. It was almost the same.

Furthermore, the time taken to develop a 3.6 Gbps New Nomadic Local Area Wireless Access (NoLA) modem chip that designed and converted algorithms and hardware into a beryllog using the integrated circuit design and verification method of the present invention is 60 times the number of gates. Although the amount of work required to complete the development of the 3600 Mbps chip was three times, the overall development period was expected to be 16 months, which is not much longer than before. In particular, although there are only six people in total, two engineers can perform algorithms and RTL engineering together to make error detection and correction steps more efficient.

By using the integrated circuit design and verification method of the present invention, it is possible to consider how to be implemented in actual hardware from the algorithm writing stage, and use the syntax of similar structure to facilitate communication between engineers in different fields, Each hardware block can be made small and efficient.

For example, in the development of NoLA multiple-input multiple output (MIMO) radio signal detection block, the inventors consider algorithms and hardware architecture at the same time, dramatically reducing the algorithm to 10,000 lines to 1,400 lines, As a result, the number of gates can be reduced by half, and a MIMO detection block with the same performance can be obtained.

All embodiments of the present invention can typically be performed through computer-based programming, compilation and debugging techniques, and the like.

Embodiments of the present invention have been illustrated above with respect to digital integrated circuits, but may be applied at various levels ranging from printed circuit boards (PCBs) to electronic systems.

While the embodiments of the present invention mainly exemplify a method of designing, simulating, and verifying with a high-level programming language such as C or C ++, it can be applied to digital integrated circuit design using various high-level programming languages.

As described above, although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited to the above-described embodiments, which can be modified by those skilled in the art to which the present invention pertains. Modifications are possible. Accordingly, the spirit of the invention should be understood only by the claims set forth below, and all equivalent or equivalent modifications will fall within the scope of the invention.

In addition, the apparatus according to the present invention can be embodied as computer readable codes on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of the recording medium include a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like, and also include a carrier wave (for example, transmission through the Internet). The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

1A is a block diagram illustrating a conventional digital integrated circuit.

1B is a block diagram illustrating a digital integrated circuit modified to apply a design methodology of a digital integrated circuit using an advanced programming language according to an embodiment of the present invention.

FIG. 1C is a timing diagram illustrating that the methodology of designing a digital integrated circuit using an advanced programming language according to an embodiment of the present invention may be applied to the digital integrated circuit of FIG. 1A even when different clocks are used.

2 is a flowchart schematically illustrating a digital integrated circuit design and verification method using an advanced programming language according to an embodiment of the present invention.

3 is a flowchart schematically illustrating a digital integrated circuit design and verification method using an advanced programming language according to another embodiment of the present invention.

4 is a flowchart illustrating a digital integrated circuit design and verification method using an advanced programming language according to another embodiment of the present invention.

5A and 5B are flowcharts illustrating a method for designing and verifying a digital integrated circuit using the C ++ language according to an embodiment of the present invention.

6A and 6B are flowcharts illustrating in detail a method for designing and verifying a digital integrated circuit using the C ++ language according to an embodiment of the present invention.

7A and 7B are flowcharts illustrating a method for designing and verifying a digital integrated circuit using the C language according to an embodiment of the present invention.

FIG. 8 is a diagram comparing syntax written in a conventional hardware description language (HDL) with syntax written in an advanced programming language according to an embodiment of the present invention.

Claims (17)

1. A method of simulating and verifying a digital integrated circuit such that one or more logics and one or more registers each operate according to one or more clocks using a sequential execution advanced programming language, (a) activating at least one clock edge of the clock edges of the clock in an application order of each clock edge; (b) updating the output variables of all registers by the value of the input variables of each register, respectively; (c) sequentially executing operations of respective logics; (d) updating input variables of registers operating in correspondence with the activated at least one clock edge with results provided from the respective logics and registers, respectively; And (e) repeating the iterations of (a) to (d) until the verification of the digital integrated circuit is finished. The method of claim 1, wherein the iteration At least one of the clock edges starts with activation and ends before the next clock edge of at least one of the clock edges is activated. The method according to claim 1, The step (b) is necessarily performed before the step (c) when the operation of the respective logics of the step (c) is affected by the value of the output variables of the respective registers. Method of simulation and verification of digital integrated circuits. The method according to claim 1, Step (c) is performed before the step (d) when the input of each register of the step (d) is affected by the value of the output variables of the respective logics Method of simulation and verification of digital integrated circuits. The method according to claim 1, wherein in step (d), Method of simulation and verification of a digital integrated circuit, wherein calculation results provided to registers that do not correspond to the activated at least one clock edge among the calculation results of the operation performed in step (c) are discarded. . 1. A method of simulating and verifying a digital integrated circuit such that one or more logic, one or more registers, and one or more sub-function modules within a top-level function module are each operated according to one or more clocks using a sequential execution high-level programming language. (I) activating at least one clock edge of the clock edges of the clock in the order of application of each clock edge; (II) updating the output variables of all the registers defined in the top-level function module with the values of the input variables of the respective registers, respectively; (III) sequentially executing operations of logic in the most significant function module; (IV) updating input variables of the registers defined in the top-level function module, the registers operating in correspondence with the activated at least one clock edge, by results provided from the respective logics and registers, respectively; (V) calling and executing the one or more sub function modules; (VI) repeating the iterations of (I) to (V) until the verification of the digital integrated circuit is finished. The method of claim 6, wherein the iteration At least one of the clock edges of the clock begins with activation and ends before the next clock edge of at least one of the clock edges of the clock is activated. Way. The method according to claim 6, wherein the (II) step, When the operation of each of the logic and sub-function modules of the step (III) is affected by the value of the output variables of the respective registers, the digital integrated circuit, characterized in that is performed before the step (III) Simulation and verification methods. The method according to claim 6, wherein in step (IV), And among the calculation results of the calculation performed in step (III), calculation results provided to registers that do not correspond to the activated at least one clock edge are discarded. The method according to claim 6, Prior to step (I), before entering the iteration, set whether the verification of the digital integrated circuit is a floating-point or fixed-point arithmetic verification, and thereby define the input variables and output variables of the wire variables and registers. Simulation and verification method of a digital integrated circuit further comprising the step of. The method according to claim 6, wherein (V) step, Updating the output variable values of all registers defined in the sub function module with the input variable values of the respective registers; Sequentially performing operations of logic in the sub function module; And Operates in response to the activated at least one clock edge among registers defined in the top-level function module connected to the logic or register output defined in the sub-function module and registers defined in the sub-function module. And updating the input variables of the registers according to the operation results of the respective logical operation syntaxes. The method of claim 11, wherein the high level programming language is a C ++ language, Prior to step (I), before entering the iteration, set whether the verification of the digital integrated circuit is floating point arithmetic or fixed point arithmetic verification, and the wire variables and register input variables to be used in the top-level function module and Further defining output variables, If the current iteration is the first iteration to perform the sub function module to be called in the step (V), prior to the step (V), further comprising the step of instantiating the sub function module classes written in the C ++ class Simulation and verification method of a digital integrated circuit, characterized in that. The method according to claim 11, wherein (V) step, If the current iteration is the first iteration to perform a lower subfunction module, instantiating the lower subfunction module classes written in a C ++ class prior to calling the lower subfunction modules; And Calling and executing the lower sub-function module. The method of claim 6, wherein the high level programming language is C language, Prior to step (I), the method further comprises defining input variables and output variables of all wire variables and registers to be used in the top function module and the sub function modules before entering the iteration. Method of simulation and verification of digital integrated circuits. The method according to claim 14, wherein (V) step, Updating output variable values of all registers defined in the sub function module with input variable values of respective registers; Sequentially performing operations of logics in the sub function module; And Corresponding to the activated at least one clock edge among the registers defined in the uppermost function module and those connected to the logic or register output defined in the subfunction module and those defined in the subfunction module. And updating the input variable of the operative registers in accordance with the operation results of the respective logics. 1. A method of simulating and verifying a digital integrated circuit such that one or more logics and one or more registers each operate according to one or more clocks using a sequential execution advanced programming language, (A) activating at least one clock edge of the clock edges of the clock in the order of application of each clock edge; (B) updating the output variables of the registers corresponding to the activated at least one clock edge by the value of the input variables of the respective registers, respectively; (C) sequentially executing operations of respective logics; (D) updating input variables of all the registers respectively with the respective logics and results provided from registers; And (E) repeating the iterations of (a) to (d) until the verification of the digital integrated circuit is finished. A method of designing, simulating, and verifying a digital integrated circuit such that one or more logics and one or more registers each operate according to one or more clocks using a sequential execution advanced programming language, For the operation of the respective logics, the syntax in which the output variables of the registers input to each logic are updated by the value of the input variables of the respective registers is located before the operation syntax of each logic, and the input variables of the registers Receiving the phrases through a high-level programming language input such that the syntax, each updated by the arithmetic results provided from the respective logics, is located after the operational syntax of each logic; And A method for designing, simulating, and verifying digital integrated circuits, comprising the steps of creating and executing the received syntaxes through an advanced programming language compiler.

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