KR100962640B1 - Method of making TFT - Google Patents

Abstract

The present invention comprises the steps of depositing a source-drain metal on a glass substrate; Applying and etching a first mask having a predetermined source / drain pattern on the source / drain metal layer to form a source / drain pattern for transmitting a data signal; Forming a gate pattern transferring a gate signal on the source / drain pattern using a second mask having a predetermined gate pattern; Depositing a protective film for protecting the source / drain pattern and the gate pattern; Forming a protective film pattern using a third mask having a predetermined protective film pattern; Forming a pixel electrode and a gate data contact on the passivation layer pattern; And forming an ordered pixel electrode by etching the pixel electrode deposited in the pixel electrode and the gate data contact step using a fourth mask. Thereby, the process can be simplified and productivity can be improved.

Description

Thin film transistor manufacturing method {Method of making TFT}

1 is a flow chart showing a thin film transistor manufacturing method according to the prior art,

2a to 2e are views sequentially showing a step of manufacturing a thin film transistor according to a conventional thin film transistor manufacturing method,

3 is a plan view of a thin film transistor substrate manufactured according to the present invention;

4 is an enlarged view of a channel part of FIG. 3;

5 is a cross-sectional view taken along the line VII-VII 'of FIG. 4,

6A through 6C are views sequentially showing steps of manufacturing a thin film transistor according to the method of manufacturing a thin film transistor of the present invention.

* Explanation of symbols for the main parts of the drawings

1: glass substrate 10: gate

15 Source Drain 17 Data Line

19 contact hole 20 insulating layer

25: protective film 30: active layer

32: channel portion 35: N ⁺ a-Si

40: pixel electrode 50a: first mask                 

50b: second mask 50c: third mask

50d: fourth mask 50e: fifth mask

The present invention relates to a method for manufacturing a thin film transistor, and more particularly, to a method for manufacturing a four-mask thin film transistor of a top gate type without using a slit mask by improving a conventional method for manufacturing a five mask thin film transistor.

Liquid crystal display is an application of the electro-optical properties to the display device by changing the arrangement of the liquid crystal molecules at the time of power supply by injecting a liquid crystal, which is an intermediate phase of a liquid and a solid between two thin glass substrates. Liquid crystals, which are organic molecules having fluidity such as liquids, are in a state of being regularly arranged like crystals, and liquid crystal displays are made of a display element using a property in which the molecular arrangement is changed by an external electric field.

The liquid crystal display is not a display using self-emission, but a passive type display using external light. This may be divided into a passive matrix and an active matrix according to the driving method.

In the passive matrix, the common electrode and the data electrode are arranged in an XY shape, and a signal is sequentially applied to the intersection thereof and displayed. Active matrix uses transistors as switches to regulate the voltage supplied to each pixel. Since the pixels are controlled independently, there is no crosstalk caused by line interference and the image quality is displayed clearly.

A typical thin film transistor of the active matrix is composed of a source for inputting current, a drain for exiting the drain, and a gate for shielding the current flow. When a voltage is applied to the gate electrode, a channel is formed to allow a current to flow in the active layer, which is a semiconductor, and data is passed through the channel to the drain electrode and the capacitor. The voltage delivered to the drain stage drives the liquid crystal to turn on and off the light to realize an image.

In general, a thin film transistor manufacturing method uses five masks. 1 is a flowchart illustrating a method of manufacturing a thin film transistor according to the prior art. 2A to 2E illustrate a process of manufacturing a conventional thin film transistor.

2A is a process diagram of manufacturing a thin film transistor using a conventional first mask. In order to form the gate 10, a gate metal is deposited on the glass substrate using a first mask 50a and a gate pattern is formed (S1). The active layer 30 forming the insulating layer 20 and the channel portion for insulating the gate 10 and the source and drain 15 is deposited on the gate pattern by PECVD (s2).

FIG. 2B is a process chart of manufacturing a thin film transistor using a conventional second mask. A pattern of the active layer 30 forming the channel part is formed on the insulating layer 20 and the active layer 30 by using the second mask 50b (s3).

Figure 2c is a process chart of manufacturing a thin film transistor using a conventional third mask. The source and drain metals are sputtered and deposited on the active layer 30, and the deposited source and drain 15 forms a pattern using a third mask 50c (s4).

In the step of using the third mask 50c, in order to facilitate the formation of the channel portion 32, a portion corresponding to the mask layer, the source / drain 15 layer, and the active layer 30 forming the channel portion 32 is formed. A portion of the third mask 50c layer is removed using a slit mask. The dashed lines shown in FIG. 2C illustrate removing part of the third mask 50 layer using a slit mask. In order to form the channel part 32, N ⁺ a-Si is etched (s5) and the protective film 25 is deposited (s6).

2D is a process diagram of manufacturing a thin film transistor using a fourth mask according to the related art. The deposited passivation pattern 25 forms a pattern using the fourth mask 50 (s7). When the pattern of the protective film 25 is formed, a process of forming the contact hole 19 for contacting the gate data and the pixel electrode 40 is performed in the same manner. In addition, a slit mask is used when forming the contact hole 19.

2E is a process chart of manufacturing a thin film transistor using a fifth mask according to the related art. The pixel electrode is deposited on the passivation layer 25, and the deposited pixel electrode forms the trimmed pixel electrode 40 using the fifth mask 50 (S8). The completed thin film transistor was manufactured through the 5 mask process.

Thus, since 5 masks are used according to the conventional manufacturing method, only the slit mask is used to form the channel portion 32 and the contact hole 19, and many mask processes are required, thus increasing the number of processes and the process time. There is also a problem with productivity.

Accordingly, an object of the present invention is to provide a thin film transistor manufacturing method which can simplify the process by not using a four-mask process and a slit mask, thereby improving productivity and reducing manufacturing costs.

According to the present invention, there is provided a thin film transistor manufacturing method comprising the steps of: depositing a source-drain metal on a glass substrate; Applying and etching a first mask having a predetermined source / drain pattern on the source / drain metal layer to form a source / drain pattern for transmitting a data signal; Forming a gate pattern transferring a gate signal on the source / drain pattern using a second mask having a predetermined gate pattern; Depositing a protective film for protecting the source / drain pattern and the gate pattern; Forming a protective film pattern using a third mask having a predetermined protective film pattern; Forming a pixel electrode and a gate data contact on the passivation layer pattern; And forming an ordered pixel electrode by etching the pixel electrode deposited in the pixel electrode and the gate data contact step using a fourth mask.

The method may further include depositing an active layer that forms a channel on the source / drain layer formed on the glass substrate.

In addition, the method may further include depositing an insulating layer on the active layer.                     

Further, the forming of the passivation layer pattern using the third mask may further include forming a contact hole connecting the gate data and the pixel electrode.

Hereinafter, as an embodiment of the method for manufacturing a thin film transistor according to the present invention, a top gate type four mask process will be described with reference to the accompanying drawings.

3 and 4 are plan views and channel portion enlarged views of the thin film transistor substrate, respectively. As shown in FIGS. 3 and 4, the pattern of the gate 10 and the data 17 is orthogonal to each other and formed on the glass substrate 1. React on

6A is a process chart of manufacturing a thin film transistor using the first mask of the present invention. In the first mask process, the source and drain 15 metals are deposited on the substrate through sputtering, and N ⁺ a-Si 35 is deposited by PECVD. The first mask 50a is coated on the N ⁺ a-Si 35 and the photo process is performed. N ⁺ a-Si 35 is removed by dry etching, and the source and drain 15 metal is wet etched to form a source and drain 15 pattern.

In addition, in the present invention, the source / drain metal and N ⁺ a-Si (35) should be ohmic contacts by using the top gate method.

Therefore, it is preferable that Al and N ⁺ a-Si (35) be replaced with Al / Cr, MoW, Al / Mo, etc. in the case of the source / drain 15 metal when Al / Cr is used. If the material is replaced with N ⁺ a-Si (35) is an ohmic contact such as Cr, MoW, Mo and so can solve the problem.

In addition, in the conventional five-mas process, the pattern was formed through the process of using a slit mask for formation of the source-drain 15. FIG. However, the present invention using the top gate method in a four mask process has an advantage that the source and drain 15 can be formed without using a slit mask.

Figure 6b is a process chart of manufacturing a thin film transistor using the second mask of the present invention. In the second mask process, the active layer 30 a-Si is deposited on the source and drain 15 patterns formed by using the first mask 50a by PECVD, and the SiNx, which is the insulating layer 20, is deposited in the same manner. Deposit. The metal of the gate 10 is deposited through sputtering on the insulating layer 20 which insulates the gate 10 and the source and drain 15. As the gate 10 metal, it is preferable to use an alloy or a single metal like the source / drain 15 metal. The photoetch is performed by applying a second mask 50b on the deposited active layer 30, the insulating layer 20, and the metal of the gate 10. The gate 10 metal forms a gate pattern through wet etching.

Figure 6c is a process chart of manufacturing a thin film transistor using a third mask of the present invention. In the third mask process, the passivation layer 25 is deposited on the metal of the gate 10 formed in the second mask 50b.                     

Here, the material of the protective film 25 preferably uses the same SiNx as the material of the insulating layer 20. The third mask 50c is applied to form the pattern of the protective film 25. When the third mask 50c is applied, the contact layer 19 is formed to form the passivation layer 25 pattern and to connect the pixel electrode 40 to the gate and data lines.

The insulating layer 20 and the active layer 30 are all removed by a dry etching process so as to be in contact with the indium zinc oxide (IZO) used as the pixel electrode 40 and the gate data line.

In particular, when the source and drain 15 metals are MoW, the N ⁺ a-Si and the source and drain 15 metals can be etched simultaneously in a single step of dry etching, thereby simplifying the manufacturing process.

In addition, when Al is first deposited and Cr or Mo is deposited, or when a single MoW film is used, a process of etching the entire Al surface for contacting the pixel electrode 40 and the metal after forming the contact hole 19 in the protective layer 25 is performed. There is an advantage that you do not have to.

In the case of using MoW, the diffusion of the metal layers 10 and 15 and the active layer 30 generated when using Al metal and the undercut that may occur due to the change of etching rate during Al etching may occur. You can also solve the problem.

5 is a cross-sectional view taken along the line VIII-VIII '. 5 is a diagram illustrating a thin film transistor completed using a fourth mask 50d. In the fourth mask process, the IZO material, which is the pixel electrode 40, is deposited through sputtering, and then the pixel electrode 40 arranged in the pattern of the fourth mask is formed. IZO, the pixel electrode 40, is removed by wet etching.

As described above, the thin film transistor according to the present invention used a top gate method. In addition, a four-mask process that does not use a slit mask can be expected to simplify the process and reduce production costs.

As described above, according to the present invention, the process using the slit mask can be reduced by using the top gate method, and the process can be simplified by using the four masks, and the manufacturing cost and the productivity are improved. .

Claims (5)

In the thin film transistor manufacturing method, Depositing a source / drain metal on the glass substrate; Attaching and etching a first mask having a source / drain pattern on the source / drain metal layer to form a source / drain pattern for transmitting a data signal; Forming a gate pattern transferring a gate signal on the source / drain pattern using a second mask having a gate pattern; Depositing a protective film for protecting said source / drain and pattern gate pattern; Forming a protective film pattern using a third mask having a predetermined protective film pattern; Directly depositing a pixel electrode on the passivation layer pattern to form a gate and data contact with the pixel electrode; And forming an ordered pixel electrode by etching the pixel electrode deposited in the pixel electrode and the gate and data contacting step using a fourth mask. The method of claim 1, And depositing an active layer forming a channel on the source / drain layer formed on the glass substrate. The method of claim 2, Thin film transistor manufacturing method comprising the step of depositing an insulating layer on the active layer. The method of claim 3, And depositing a gate metal transferring the gate signal on the insulating layer. The method of claim 1, The forming of the passivation layer pattern using the third mask further comprises forming a contact hole connecting the gate data and the pixel electrode.

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