KR100955676B1 - Internal voltage generator - Google Patents

Abstract

The present invention provides an internal voltage driver configured to drive an internal voltage signal in response to a first reference voltage signal and to adjust a level of the internal voltage signal according to a first control signal and a second control signal; An internal voltage including a driving controller configured to generate a first control signal by comparing a second reference voltage signal with the internal voltage signal, and generate the second control signal by comparing a third reference voltage signal with the internal voltage signal; It relates to a generating circuit.

Internal voltage, driving force, dead zone

Description

Internal voltage generating circuit {INTERNAL VOLTAGE GENERATING CIRCUIT}

The present invention relates to a semiconductor device, and more particularly to an internal voltage generation circuit.

Mobile DRAM uses internal power such as VCORE, VPERI, VPP, VBB, VBLP, VCP to improve DRAM performance.

VCORE, VPP, VPERI, and VBB drivers are designed to accurately model the amount of current used by the DRAM and to have sufficient driving force.

VBLP is a power supply used to precharge BL and BLB. It is not only used in the precharge section, but also the VBLP level can be set to the intermediate level between VCORE and VSS without a separate VBLP driver. Account for a small portion. In addition, the VCP is a power supply that holds one node of the cell cap together with the storage node and is maintained at a constant level after the power-up period ends.

On the other hand, the VBLP and VCP power supply must handle the load of BL and BLB and cell cap having a large level, so that the dead zone, which is a constant voltage fluctuation period, is set so as not to react too sensitively. In order to reduce the current consumption, the driver is not operated.

In particular, the VCP power supply is maintained at about 1/2 VCORE level during initial operation, and the storage node is set at 1/2 VCORE level, which is almost the same level as VCP under the influence of VCP through the cell cap. However, problems can occur here.

In an ideal case, the initial storage node goes up to the VCP level and is set to the 1/2 VCORE level. When cell data is input and the sense amplifier operates, the initial storage node is amplified to the VCORE level or 0V. For example, if VCORE is 1.5V and VCP is 0.75V, half the value, the initial storage node will go up to 0.75V in the ideal case, but if it goes below or above about 0.75V, the initial auto refresh after power-up (auto-refresh) can be amplified to 0V or VCORE level.

If the storage node is set to 0.7V and is amplified to 0V during auto refresh, the storage node level fluctuates by about 700mV, and thus the VCP level is lowered due to the coupling effect. Thereafter, the VCP maintains the changed level for a certain time depending on the performance of the VCP driver.

On the contrary, when the storage node is set to 0.8V and amplified to VCORE level during the auto-refresh, the level of the storage node fluctuates by about 700mV. Thus, the coupling effect increases the VCP level and is maintained for a certain time.

Here, the problem may be a case where the read operation or the write operation is performed while the VCP level is rising or falling, not the rising or falling VCP level itself. At this time, since the VCP level which becomes the reference level of the cell cap is changed, there is a problem that it is not known whether the data value becomes '1' or '0'.

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Accordingly, the present invention proposes an internal voltage generation circuit which attempts to stabilize a variable VCP level more quickly by increasing the driving force of the driver using a method of controlling the dead zone of the internal voltage (VCP) driver.

The present invention includes an internal voltage driver configured to drive an internal voltage signal in response to a first reference voltage signal and to adjust a level of the internal voltage signal according to a first control signal and a second control signal; And a driving controller configured to generate a first control signal by comparing a second reference voltage signal with the internal voltage signal, and generate the second control signal by comparing a third reference voltage signal with the internal voltage signal.

The present invention provides a reference voltage generator for outputting first to third reference voltages, a driver for driving an internal voltage signal in response to the first reference voltage signal, and a level of an internal voltage signal output from the driver. An internal voltage driver including an internal voltage adjusting unit to adjust the second voltage and the internal voltage signal to generate a first control signal, and compare the third reference voltage signal with the internal voltage signal to generate a first control signal; And a driving controller for generating a control signal.

As described above, the present invention can stabilize the VCP level changing faster by increasing the driving force of the driver using a method of controlling the dead zone of the internal voltage (VCP) driver.

Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

1 is a block diagram of an internal voltage generation circuit according to the present invention.

As shown in FIG. 1, the present invention provides a reference voltage generator 30 for outputting first to third reference voltages LEVEL, LEVEL + a, and LEVEL-a, and the first reference voltage signal LEVEL. In response to the pull-up signal PU for driving the internal voltage signal VCP and the pull-down signal PD for pull-down driving the internal voltage signal VCP, the pull-up signal PU and the pull-down signal PD are generated. The level is adjusted according to the first control signal CS1 and the second control signal CS2, and the second and third reference voltage signals LEVEL + a and LEVEL-a and the internal voltage. The driving control unit 20 receives the voltage signal VCP and outputs the first control signal CS1 and the second control signal CS2.

Here, the level of the second reference voltage LEVEL + a is higher than the level of the first reference voltage LEVEL by a predetermined amount, and the level of the third reference voltage LEVEL-a is the first reference voltage LEVEL) is lower than a certain level.

FIG. 2 is a circuit diagram of the internal voltage driver of FIG. 1. As illustrated in FIG. 2, the internal voltage driver 10 may include a driver 11 driving the internal voltage signal VCP in response to the first reference voltage signal LEVEL, and the first control signal. And an internal voltage control unit 12 for adjusting the level of the internal voltage signal VCP in response to the pull-up signal PU and the pull-down signal PD whose level is adjusted according to CS1) and the second control signal CS2. do.

The internal voltage controller 12 may include an adjustment signal output unit 121 for adjusting a pull-up signal PU and a pull-down signal PD in response to the first control signal CS1 and the second control signal CS2. . The controller 122 adjusts the level of the internal voltage signal VCP in response to the pull-up signal PU and the pull-down signal PD.

The control signal output unit 121 is turned on or off in response to the first control signal CS1 and the second control signal CS2 to adjust the amount of current (P2, P3, N2, N3). ) And the variable parts P4, P5, N4 and N5 for outputting the pull-up signal PU and the pull-down signal PD whose level is adjusted according to the current control of the variable controllers P2, P3, N2 and N3. It includes.

The adjusting unit 122 includes a PMOS driver P1 for adjusting the level of the internal voltage signal VCP in response to the pull-up signal PU, and the internal voltage signal VCP in response to the pull-down signal PD. NMOS driver (N1) for adjusting the level of).

3A and 3B are circuit diagrams of the drive controller of FIG. 1. As shown in FIG. 3A, the driving controller 20 compares the second reference voltage signal LEVEL + a with the internal voltage signal VCP, and according to the comparison result, the first control signal having a predetermined logic level. Comparing the first control unit 21 outputting CS1 with the third reference voltage signal LEVEL-a and the internal voltage signal VCP as shown in FIG. A second control unit 22 for outputting a logic level control signal CS2 is included.

As shown in FIG. 3A, the first controller 21 may include a first comparator 211 comparing the second reference voltage signal LEVEL + a and the internal voltage signal VCP and the first comparator. And a control signal output unit 212 for outputting a control signal CS1 having a predetermined logic level in response to the output signal 211 and the threshold voltage bias signal Vth. Here, the control signal output unit 212 is a pull-up driving unit for pull-up driving in response to the output signal of the first comparator 211, pull-down driving in response to the threshold voltage bias signal (Vth) And a pull-down driving unit.

As shown in FIG. 3B, the second controller 22 includes a second comparator 221 for comparing the third reference voltage signal LEVEL-a with the internal voltage signal VCP, and the second comparator. The control signal output unit 222 outputs a control signal CS2 having a predetermined logic level in response to the output signal 221 and the threshold voltage bias signal Vth. The control signal output unit 222 may include a pull-up driving unit for pull-up driving in response to an output signal of the second comparator 221 and a pull-down driving unit in response to the threshold voltage bias signal Vth. And a down drive. In addition, the control signal output unit 222 further includes a buffer unit 223 for buffering the output signals of the pull-up driving unit and the pull-down driving unit.

The operation of the internal voltage generating circuit according to the present invention configured as described above will be described in detail with reference to FIGS. 1 to 4.

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As illustrated in FIG. 1, the internal voltage driver 10 may pull-up a signal PU for pull-up driving the internal voltage signal VCP and a pull-down signal PD for pull-down driving in response to the first reference voltage signal LEVEL. The level of the pull-up signal PU and the pull-down signal PD is adjusted according to the first control signal CS1 and the second control signal CS2. The driving controller 20 generates the first control signal CS1 by comparing the second reference voltage signal LEVEL + a and the internal voltage signal VCP, and generates the third reference voltage signal LEVEL-a and the internal voltage. The second control signal CS2 is generated by comparing the signal VCP.

As shown in FIG. 2, the internal voltage adjusting unit 12 of the internal voltage driving unit 10 is turned on or turned off in response to the first control signal CS1 and the second control signal CS2 so that the amount of current is increased. The dead zone is controlled using the variable controllers P2, P3, N2, and N3. Here, the upper PMOS transistors P2 and P3 control the dead zone for + i (VCP), and the lower NMOS transistors N2 and N3 control the dead zone for -i (VCP). That is, the internal voltage controller 12 determines how many PMOS transistors or NMOS transistors are to be used according to the first control signal CS1 and the second control signal CS2 output from the driving controller 20. Here, when the size or number of PMOS transistors or NMOS transistors increases, the dead zone becomes large.

Therefore, in the normal situation, the number of PMOS transistors or NMOS transistors included in the variable control units P2, P3, N2, and N3 will be used to reduce current sensitivity by reducing the operation sensitivity of the internal voltage signal VCP. When receiving an input, the number of PMOS transistors or NMOS transistors can be reduced to make the dead zone less, making the operation of the internal voltage driver sensitive, thereby increasing the driving force.

An operation of the driving controller 20 will be described with reference to FIGS. 3A and 3B as follows.

First, as shown in FIG. 3A, when the internal voltage signal VCP becomes higher than the second reference voltage signal LEVEL + a, the first comparator 211 detects the first control signal and the first control signal. A high level logic signal is output to (CS1). Then, the internal voltage regulator 12 (refer to FIG. 2) turns off the plurality of PMOS transistors P2 and P3 connected in parallel in response to the first control signal CS1, and thus, through the PMOS transistors P2 and P3. As the amount of current decreases, the level of the pull-up signal PU is lowered. Therefore, the PMOS driver P1 pulls up the internal voltage signal VCP in response to the pullup signal PU. That is, the internal voltage regulator 12 reduces the dead zone of + i (VCP) when the number of PMOS transistors used in response to the first control signal CS1 decreases.

In addition, when the internal voltage signal VCP becomes lower than the second reference voltage signal LEVEL + a, the first control unit 21 does not hold a certain low level or high level. CS1) outputs a low level logic signal. Then, the internal voltage controller 12 turns on the PMOS transistors P2 and P3 of the variable controllers P2, P3, N2 and N3 in response to the first control signal CS1. That is, the internal voltage regulator 12 increases the number of PMOSs used, thereby widening the dead zone of + i (VCP).

As shown in FIG. 3B, when the internal voltage signal VCP becomes lower than the third reference voltage signal LEVEL-a, the second comparator 221 senses the second control signal. A low level logic signal is output to (CS2). Then, the internal voltage regulator 12 (see FIG. 2) turns off the NMOS transistors N2 and N3 of the variable controllers P2, P3, N2 and N3 in response to the second control signal CS2. Since the amount of current through the NMOS transistors N2 and N3 is reduced, the level of the pulldown signal PD is increased. Therefore, the NMOS driver N1 pulls down the internal voltage signal VCP in response to the pulldown signal PD. That is, the internal voltage controller 12 reduces the dead zone of -i (VCP) when the number of NMOS transistors used in response to the second control signal CS2 is reduced.

In addition, when the internal voltage signal VCP becomes higher than the third reference voltage signal LEVEL-a, the second control unit 22 detects the second comparator 221 and detects the second control signal CS2 having a high level. Output Then, the internal voltage regulator 12 (see FIG. 2) turns on the NMOS transistors N2 and N3 of the variable controllers P2, P3, N2 and N3 in response to the second control signal CS2. That is, the internal voltage regulator 12 increases the number of NMOS transistors used, thereby widening the dead zone of -i (VCP).

As such, when the level of the internal voltage signal VCP fluctuates within a predetermined range, the present invention operates while maintaining a preset dead zone to reduce the current consumption of the internal voltage signal VCP, and coupling the storage node. When the level of the internal voltage signal VCP rises or falls under the influence, the dead zone of the VCP driver is controlled to quickly stabilize the level of the internal voltage signal VCP.

1 is a block diagram of an internal voltage generation circuit according to the present invention.

FIG. 2 is a circuit diagram of the internal voltage driver of FIG. 1.

3A and 3B are circuit diagrams of the driving controller of FIG. 1.

4 is a view showing that the dead zone (dead zone) is variable by the present invention.

Claims (22)

A pull-up signal for pulling up the internal voltage signal and a pull-down signal for pulling down the internal voltage signal in response to a first reference voltage signal, wherein the level of the pull-up signal and the pull-down signal is controlled by the first control signal and the second control; An internal voltage driver adjusted according to a signal; A driving controller configured to generate a first control signal by comparing a second reference voltage signal with the internal voltage signal, and generate the second control signal by comparing a third reference voltage signal with the internal voltage signal; Internal voltage generation circuit comprising a. The method of claim 1, A reference voltage generator for outputting the first to third reference voltages; Internal voltage generation circuit further comprising. The method of claim 2, And the level of the second reference voltage is higher than the level of the first reference voltage, and the level of the third reference voltage is lower than the level of the first reference voltage. The method of claim 1, wherein the internal voltage driver A driving unit driving the internal voltage signal in response to the first reference voltage signal; An internal voltage controller configured to adjust a level of the internal voltage signal in response to the first control signal and the second control signal; Internal voltage generation circuit comprising a. The method of claim 4, wherein the internal voltage control unit An adjustment signal output unit configured to output a pull-up signal and a pull-down signal in response to the first control signal and the second control signal; An adjusting unit adjusting the level of the internal voltage signal in response to the pull-up signal and the pull-down signal; Internal voltage generation circuit comprising a. The method of claim 5, wherein the control signal output unit A variable controller driving in response to the first control signal and the second control signal; A variable unit configured to variably output the pull-up signal and the pull-down signal according to the driving of the variable controller; Internal voltage generation circuit comprising a. The method of claim 5, wherein the control unit A PMOS driver configured to pull up the internal voltage signal in response to the pullup signal; An NMOS driver that pulls down the internal voltage signal in response to the pulldown signal; Internal voltage generation circuit comprising a. The method of claim 1, wherein the drive control unit A first controller comparing the second reference voltage signal with the internal voltage signal and outputting the first control signal having a predetermined logic level according to the comparison result; A second control unit comparing the third reference voltage signal with the internal voltage signal and outputting the second control signal having a predetermined logic level according to the comparison result; Internal voltage generation circuit comprising a. The method of claim 8, wherein the first control unit A first comparator for comparing the second reference voltage signal with the internal voltage signal; A first control signal output unit outputting the first control signal having a predetermined logic level in response to an output signal of the first comparator and a threshold voltage bias signal; Internal voltage generation circuit comprising a. The method of claim 9, wherein the first control signal output unit A pull-up driving unit configured to pull-up driving in response to an output signal of the first comparator; A pull-down driving unit configured to pull-down drive in response to the threshold voltage bias signal; Internal voltage generation circuit comprising a. The method of claim 8, wherein the second control unit A second comparator for comparing the third reference voltage signal with the internal voltage signal; A second control signal output unit configured to output the second control signal having a predetermined logic level in response to an output signal of the second comparator and a threshold voltage bias signal; Internal voltage generation circuit comprising a. The method of claim 11, wherein the second control signal output unit A pull-up driving unit configured to pull-up driving in response to an output signal of the second comparator; A pull-down driving unit configured to pull-down drive in response to the threshold voltage bias signal; Internal voltage generation circuit comprising a. The method of claim 12, wherein the second control signal output unit A buffer unit for buffering output signals of the pull-up driver and the pull-down driver; Internal voltage generation circuit further comprising. A reference voltage generator for outputting first to third reference voltages; A driver for driving an internal voltage signal in response to the first reference voltage signal, a pull-up signal for pull-up driving the internal voltage signal in response to the first reference voltage signal, and a pull-down signal for pulling down the internal voltage signal; Wherein, the level of the pull-up signal and the pull-down signal is an internal voltage driver including an internal voltage control unit is adjusted according to the first control signal and the second control signal; A driving controller configured to generate the first control signal by comparing the second reference voltage signal with the internal voltage signal, and generate the second control signal by comparing the third reference voltage signal with the internal voltage signal; Internal voltage generation circuit comprising a. The method of claim 14, And the level of the second reference voltage is higher than the level of the first reference voltage, and the level of the third reference voltage is lower than the level of the first reference voltage. The method of claim 14, wherein the internal voltage control unit A variable controller controlling an amount of current in response to the first control signal and the second control signal; A variable unit configured to output the pull-up signal and the pull-down signal under the control of the variable controller; An adjusting unit adjusting the level of the internal voltage signal in response to the pull-up signal and the pull-down signal; Internal voltage generation circuit comprising a. The method of claim 14, wherein the drive control unit A first control unit comparing the second reference voltage signal with the internal voltage signal and outputting the first control signal having a predetermined logic level according to the comparison result; A second control unit comparing the third reference voltage signal with the internal voltage signal and outputting the second control signal having a predetermined logic level according to the comparison result; Internal voltage generation circuit comprising a. The method of claim 17, wherein the first control unit A first comparator for comparing the second reference voltage signal with the internal voltage signal; A first control signal output unit outputting the first control signal having a predetermined logic level in response to an output signal of the first comparator and a threshold voltage bias signal; Internal voltage generation circuit comprising a. The method of claim 18, wherein the first control signal output unit A pull-up driving unit configured to pull-up driving in response to an output signal of the first comparator; A pull-down driving unit configured to pull-down drive in response to the threshold voltage bias signal; Internal voltage generation circuit comprising a. The method of claim 17, wherein the second control unit A second comparator for comparing the third reference voltage signal with the internal voltage signal; A second control signal output unit configured to output the second control signal having a predetermined logic level in response to an output signal of the second comparator and a threshold voltage bias signal; Internal voltage generation circuit comprising a. The method of claim 20, wherein the second control signal output unit A pull-up driving unit configured to pull-up driving in response to an output signal of the second comparator; A pull-down driving unit configured to pull-down drive in response to the threshold voltage bias signal; Internal voltage generation circuit comprising a. The method of claim 21, wherein the second control signal output unit A buffer unit for buffering output signals of the pull-up driver and the pull-down driver; Internal voltage generation circuit further comprising.

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