KR100953337B1 - Manufacturing Method of Semiconductor Device - Google Patents
Manufacturing Method of Semiconductor Device Download PDFInfo
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- KR100953337B1 KR100953337B1 KR1020070136357A KR20070136357A KR100953337B1 KR 100953337 B1 KR100953337 B1 KR 100953337B1 KR 1020070136357 A KR1020070136357 A KR 1020070136357A KR 20070136357 A KR20070136357 A KR 20070136357A KR 100953337 B1 KR100953337 B1 KR 100953337B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title abstract description 8
- 150000004767 nitrides Chemical class 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 229920005591 polysilicon Polymers 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 230000000873 masking effect Effects 0.000 claims abstract description 5
- 230000001681 protective effect Effects 0.000 claims description 2
- 238000002955 isolation Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/213—Channel regions of field-effect devices
- H10D62/221—Channel regions of field-effect devices of FETs
- H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
- H10D62/292—Non-planar channels of IGFETs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
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- Microelectronics & Electronic Packaging (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 반도체 소자의 제조 방법에 관한 것으로, STI 일부 영역에 게이트 전극을 형성하여, 비대칭 게이트를 갖는 트랜지스터를 형성함으로써 게이트의 사이즈를 줄이고자 하는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and to reduce the size of a gate by forming a gate electrode in a portion of the STI and forming a transistor having an asymmetric gate.
이에, 본 발명은 반도체 기판상에 제1 산화물, 제1 질화물, 제2 산화물을 적층한 후, 마스킹 식각으로 반도체 기판의 표면에서 일정 깊이까지 식각되는 트랜치를 형성하는 단계와, 반도체 기판 및 트랜치가 매립되도록 제2 질화물 및 제3 산화물을 차례로 증착하고, CMP 공정을 수행하여 STI 영역을 형성하는 단계와, STI의 일부 영역에 포토 레지스트를 도포한 후, 에칭공정을 수행하여 포토 레지스트와 제1 질화물을 제거하는 단계와, STI 영역에서 제3 산화물이 제거된 부분의 제2 질화막을 제거하고, 반도체 기판 상면에 제4 산화물을 형성한 후, 제4 산화물 상면에 폴리 실리콘을 증착하는 단계 및 폴리 실리콘을 식각하여 트랜지스터의 게이트를 형성하는 단계를 포함한다.Accordingly, the present invention is a step of forming a trench that is etched to a certain depth on the surface of the semiconductor substrate by masking etching after the first oxide, the first nitride, and the second oxide on the semiconductor substrate, and the semiconductor substrate and the trench Depositing a second nitride and a third oxide in order to be buried, and performing a CMP process to form an STI region, applying a photoresist to a portion of the STI, and performing an etching process to perform a photoresist and a first nitride. Removing the second oxide film of the portion where the third oxide is removed from the STI region, forming a fourth oxide on the upper surface of the semiconductor substrate, and then depositing polysilicon on the upper surface of the fourth oxide; and Etching to form a gate of the transistor.
반도체 소자, STI, 게이트, 비대칭 Semiconductor Devices, STI, Gate, Asymmetric
Description
본 발명은 반도체 소자에 관한 것으로, 더욱 상세하게는 동일한 채널 길이를 유지하면서 실제 게이트 사이즈를 줄일 수 있도록 하는 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device to reduce the actual gate size while maintaining the same channel length.
일반적으로, 반도체 기판상에 트랜지스터와 커패시터 등을 형성하기 위하여 반도체 기판에는 전기적으로 통전이 가능한 활성영역(Active Region)과 전기적으로 통전되는 것을 방지하고자 소자를 서로 분리하도록 하는 소자 분리영역(Isolation region)을 형성하게 된다.In general, in order to form transistors and capacitors on the semiconductor substrate, an isolation region for separating the devices from each other in order to prevent electrical conduction with an active region that is electrically energized in the semiconductor substrate. Will form.
이와 같이, 소자를 분리시키기 위하여 패드 산화막을 성장시켜 형성되는 필드 산화막을 형성시키기 위한 공정에는 반도체 기판에 패드 산화막과 나이트 라이드막을 마스킹 공정으로 나이트 라이드막을 식각하고, 그 식각된 소자 분리영역이 형성될 부위에 필드 산화막을 형성시키는 LOCOS 공정(Local Oxidation of silicon)이 있으며, 그 외에 상기 LOCOS 공정의 패드 산화막과 나이트 라이드막 사이에 버퍼 역할을 하는 폴리 실리콘 막을 개재하여 완충 역할을 하여 필트 산화막을 성장시키는 PBL(Poly Buffered LOCOS)공정 등이 사용되고 있다.As such, in the process for forming the field oxide film formed by growing the pad oxide film to separate the devices, the nitride film is etched by masking the pad oxide film and the nitride film on the semiconductor substrate, and the etched device isolation region is formed. There is a LOCOS process (Local Oxidation of silicon) to form a field oxide film on the site, and in addition to the growth of the filter oxide film by acting as a buffer between the pad oxide film and the nitride film of the LOCOS process through a polysilicon film that serves as a buffer PBL (Poly Buffered LOCOS) process is used.
또한, 반도체 기판에 일정한 깊이를 갖는 트렌치(Trench)를 형성하고, 이 트렌치에 산화막을 증착시키고서 화학기계적 연마공정(Chemical Mechanical Polishing) 고정으로 이 산화막의 불필요한 부분을 식각하므로 소자 분리영역을 반도체 기판에 형성시키는 STI(Shallow Trench Isolation)공정이 최근에 많이 이용되고 있다.In addition, a trench having a predetermined depth is formed in the semiconductor substrate, an oxide film is deposited on the trench, and an unnecessary portion of the oxide film is etched by fixing the chemical mechanical polishing process, thereby forming a device isolation region. The Shallow Trench Isolation (STI) process, which is formed on the substrate, has been widely used in recent years.
도 1은 종래 반도체 소자의 트랜지스터 제조방법을 설명하기 위한 도면으로, 먼저, 활성 영역(미도시) 및 필드 영역(미도시)이 구비된 실리콘 기판을 제공한 다음, 실리콘 기판의 필드 영역에는 공지의 STI(Shallow Trench Isolation)공정을 통해 소자 분리막(1)을 형성한다.FIG. 1 is a view for explaining a transistor manufacturing method of a conventional semiconductor device. First, a silicon substrate having an active region (not shown) and a field region (not shown) is provided. The
이어서, 실리콘 기판의 활성 영역 상에 게이트 산화막과 게이트 폴리 실리콘막의 적층구조로 이루어지고, 그 양측벽에는 스페이서를 갖는 게이트 전극(2)을 형성한다. 그리고, 게이트 전극(2) 양측 하부 기판에 소스/드레인 영역을 형성한다.Subsequently, a gate electrode film and a gate polysilicon film are laminated on the active region of the silicon substrate, and
이와 같이, 반도체 기판에 소자 분리막을 형성한 후, 활성영역에 게이트 산화막과 게이트 폴리층을 적층한 후, 마스킹 식각으로 게이트 전극을 대칭적으로 형성하였다. As described above, after the device isolation layer was formed on the semiconductor substrate, the gate oxide layer and the gate poly layer were stacked in the active region, and then the gate electrode was symmetrically formed by masking etching.
그러나, 종래의 STI형 소자분리막은 채널 폭에 따라 활성영역에 있는 채널 농도의 감소를 가져오게 되고, STI와 게이트가 대칭적으로 형성됨으로써 사이즈를 줄이는데 한계가 있었다.However, the conventional STI device isolation film has a decrease in the channel concentration in the active region according to the channel width, and there is a limit in reducing the size by forming the STI and the gate symmetrically.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 STI 일부 영역에 게이트 전극을 형성하여, 비대칭 게이트를 갖는 트랜지스터를 형성하고자 하는 반도체 소자의 제조 방법을 제공함에 있다.The present invention is to solve the above problems, an object of the present invention is to provide a method for manufacturing a semiconductor device to form a transistor having an asymmetric gate by forming a gate electrode in a portion of the STI.
전술한 본 발명의 목적을 달성하기 위한 반도체 소자의 제조 방법은, 반도체 기판상에 제1 산화물, 제1 질화물, 제2 산화물을 적층한 후, 마스킹 식각으로 반도체 기판의 표면에서 일정 깊이까지 식각되는 트랜치를 형성하는 단계와, 반도체 기판 및 트랜치가 매립되도록 제2 질화물 및 제3 산화물을 차례로 증착하고, CMP 공정을 수행하여 STI 영역을 형성하는 단계와, STI의 일부 영역에 포토 레지스트를 도포한 후, 에칭공정을 수행하여 포토 레지스트와 상기 제1 질화물을 제거하는 단계와, STI 영역에서 상기 제3 산화물이 제거된 부분의 제2 질화막을 제거하고, 반도체 기판 상면에 제4 산화물을 형성한 후, 제4 산화물 상면에 폴리 실리콘을 증착하는 단계 및 폴리 실리콘을 식각하여 트랜지스터의 게이트를 형성하는 단계를 포함한다.In the method of manufacturing a semiconductor device for achieving the above object of the present invention, the first oxide, the first nitride, and the second oxide are laminated on a semiconductor substrate, and then etched to a predetermined depth on the surface of the semiconductor substrate by masking etching. Forming a trench, depositing a second nitride and a third oxide so that the semiconductor substrate and the trench are buried, and performing a CMP process to form an STI region, and then applying a photoresist to a portion of the STI. Removing the photoresist and the first nitride by performing an etching process, removing the second nitride film of the portion where the third oxide is removed in the STI region, and forming a fourth oxide on the upper surface of the semiconductor substrate, Depositing polysilicon on the fourth oxide top surface and etching the polysilicon to form a gate of the transistor.
여기서, 제3 산화물은 소자와 소자를 분리하는 STI이고, 제2 질화물은 STI의 일부 영역을 에칭할 시, 방지막으로 사용되는 것을 특징으로 한다.Here, the third oxide is an STI that separates the device from the device, and the second nitride is used as a protective film when etching a portion of the STI.
또한, 제2 질화물은 활성 영역의 산화막 로스(Loss)를 방지하는 것을 특징으로 한다.In addition, the second nitride is characterized in that the oxide film loss of the active region is prevented.
이때, 제4 산화물은 트랜지스터의 유전체 역할을 하는 것을 특징으로 한다.In this case, the fourth oxide may serve as a dielectric of the transistor.
그리고, 게이트는 활성영역과 SIT를 동시에 걸쳐 비대칭적으로 형성되는 것 을 특징으로 한다.And, the gate is characterized in that the asymmetrical formation over the active region and the SIT at the same time.
위와 같이 설명된 본 발명에 따르면, STI형 소자 분리막 상에 비대칭적으로 게이트 전극을 형성하여 트랜지스터를 제조함으로써 동일한 채널 길이를 가지면서 실제 게이트의 사이즈를 감소시킬 수 있는 효과가 있다.According to the present invention as described above, by forming a gate electrode asymmetrically on the STI-type device isolation film has the effect of reducing the size of the actual gate while having the same channel length.
이하, 본 발명의 일실시예에 따른 반도체 제조 방법에 대하여 도면을 상세하게 설명한다.Hereinafter, a semiconductor manufacturing method according to an embodiment of the present invention will be described in detail.
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도 3a 내지 도 3j는 본 발명의 일실시예에 따른 반도체 소자의 제조 방법을 순서대로 나타낸 도면이다.3A to 3J are diagrams sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
도 3a를 살펴보면, 반도체 기판상(10)에 제1 산화막(12) 및 제1 질화막(14)을 적층하고, 다시 제2 산화물(16)을 적층한 후, 마스킹 식각으로 반도체 기판의 표면에서 일정 깊이까지 식각되는 트랜치(20)를 형성한다.Referring to FIG. 3A, the
이후, 도 3b에 도시된 바와 같이, 트랜치(20)가 형성된 반도체 기판에 제2 질화물(18)을 도포하고, 제2 질화물(18)을 포함하여 트랜치(20) 내부에 제3 산화물(30)을 매립하여 적층한다. Thereafter, as illustrated in FIG. 3B, the
이때, 제3 산화물(30)은 소자와 소자를 분리하는 STI이고, 제2 질화물(18)은 후속 공정에서 STI의 일부 영역을 에칭할 때 에치 방지막으로 사용된다.In this case, the
이후, 도 3c를 살펴보면, CMP 공정을 통해 전면을 식각하여 불필요한, 질화물과 산화물을 제거한다. 3C, the entire surface is etched through the CMP process to remove unnecessary nitrides and oxides.
계속해서, 도 3d를 살펴보면, STI 일부 영역에 포토 레지스트(19)를 도포하고, 에칭 공정을 통하여 트랜치 내부에 형성된 제3 산화물(30)의 일부분을 제거한다.Subsequently, referring to FIG. 3D, the
이때, 제2 질화막(18)은 활성영역의 산화막 로스(Loss)를 방지한다.In this case, the
그리고, 도 3e에 도시된 바와 같이, 반도체 기판상에 형성된 감광막(19)과 질화막(14)을 차례로 제거한다. 3E, the
이후, 도 3f에서와 같이, STI영역에서 트랜치 내부의 제3 산화물(30)이 제거된 부분에 형성된 제2 질화막(18)을 제거한다.Thereafter, as shown in FIG. 3F, the
그리고, 도 3g와 같이, 반도체 기판상(10)에 제4 산화물(23)을 산화시킨다. 여기서, 제4 산화물(23)은 트랜지스터의 유전체 역할을 한다.Then, as shown in FIG. 3G, the
이후, 도 3h를 살펴보면, 제4 산화물(23) 상부에 폴리 실리콘(24)을 증착하고, 건식 식각을 사용하여 트랜지스터의 게이트(25)를 형성시킨다.3H,
그리고, 도 3i에서와 같이, 게이트(25)가 활성영역과 STI를 동시에 걸치 트랜지스터를 형성한다. As shown in FIG. 3I, the
이후, 도 3j에서와 같이, 게이트(25) 측면에 스페이서(40)를 형성함으로써 비대칭적인 게이트 구조를 갖는 트랜지스터가 형성된다.Thereafter, as shown in FIG. 3J, a transistor having an asymmetric gate structure is formed by forming the
이때, 소스와 드레인의 배선 연결시, 일부분 게이트가 STI 상부 쪽으로 연결되는 것이 바람직하다.At this time, when wiring of the source and the drain, it is preferable that the partial gate is connected to the upper side of the STI.
이상에서는 본 발명의 바람직한 실시예에 대하여 도시하고 또한 설명하였으나, 본 발명은 상기한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 본 발명이 속하는 분야에서 통상의 지식을 가진자라면 누구든지 다양한 변형실시가 가능한 것을 물론이고, 그와 같은 변경은 기재된 청구범위 내에 있게 된다.Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the above-described embodiments, and the present invention is not limited to the above-described embodiments without departing from the spirit of the present invention as claimed in the claims. Of course, any person skilled in the art can make various modifications, and such changes are within the scope of the claims.
도 1은 종래 기술에 따른 반도체 소자의 트랜지스터를 나타낸 도면, 1 is a view showing a transistor of a semiconductor device according to the prior art,
도 2는 본 발명의 일실시예에 따라 형성된 반도체 소자의 트랜지스터를 나타낸 도면,2 illustrates a transistor of a semiconductor device formed according to an embodiment of the present invention;
도 3a 내지 도 3j는 본 발명의 일실시예에 따른 반도체 제공 방법을 순서대로 나타낸 도면이다.3A to 3J are diagrams sequentially illustrating a method for providing a semiconductor according to an embodiment of the present invention.
Claims (5)
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| KR20030000437A (en) * | 2001-06-25 | 2003-01-06 | 주식회사 하이닉스반도체 | Method for manufacturing isolation of semiconductor device |
| US6686624B2 (en) | 2002-03-11 | 2004-02-03 | Monolithic System Technology, Inc. | Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region |
| US6841821B2 (en) | 1999-10-07 | 2005-01-11 | Monolithic System Technology, Inc. | Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same |
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| US6841821B2 (en) | 1999-10-07 | 2005-01-11 | Monolithic System Technology, Inc. | Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same |
| KR20030000437A (en) * | 2001-06-25 | 2003-01-06 | 주식회사 하이닉스반도체 | Method for manufacturing isolation of semiconductor device |
| US6686624B2 (en) | 2002-03-11 | 2004-02-03 | Monolithic System Technology, Inc. | Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region |
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