KR100948641B1 - Manufacturing method of printed circuit board - Google Patents
Manufacturing method of printed circuit board Download PDFInfo
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- KR100948641B1 KR100948641B1 KR1020070099230A KR20070099230A KR100948641B1 KR 100948641 B1 KR100948641 B1 KR 100948641B1 KR 1020070099230 A KR1020070099230 A KR 1020070099230A KR 20070099230 A KR20070099230 A KR 20070099230A KR 100948641 B1 KR100948641 B1 KR 100948641B1
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- printed circuit
- insulating layer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 238000003825 pressing Methods 0.000 claims abstract description 23
- 230000003746 surface roughness Effects 0.000 claims abstract description 19
- 239000011248 coating agent Substances 0.000 claims abstract description 7
- 238000000576 coating method Methods 0.000 claims abstract description 7
- 238000007906 compression Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 229920001721 polyimide Polymers 0.000 claims description 8
- 229920000106 Liquid crystal polymer Polymers 0.000 claims description 6
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 claims description 6
- 229920001774 Perfluoroether Polymers 0.000 claims description 6
- 239000004642 Polyimide Substances 0.000 claims description 6
- 239000005023 polychlorotrifluoroethylene (PCTFE) polymer Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 229920000840 ethylene tetrafluoroethylene copolymer Polymers 0.000 claims description 5
- CHBCHAGCVIMDKI-UHFFFAOYSA-N [F].C=C Chemical group [F].C=C CHBCHAGCVIMDKI-UHFFFAOYSA-N 0.000 claims description 4
- 229920007925 Ethylene chlorotrifluoroethylene (ECTFE) Polymers 0.000 claims description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims description 3
- 239000004812 Fluorinated ethylene propylene Substances 0.000 claims description 3
- 229910021578 Iron(III) chloride Inorganic materials 0.000 claims description 3
- 229920001577 copolymer Polymers 0.000 claims description 3
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000010884 ion-beam technique Methods 0.000 claims description 3
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 claims description 3
- 229920009441 perflouroethylene propylene Polymers 0.000 claims description 3
- 238000009832 plasma treatment Methods 0.000 claims description 3
- 229920000131 polyvinylidene Polymers 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- -1 Ethylene-Tetra Fluoro Ethylene Chemical group 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 22
- 239000011889 copper foil Substances 0.000 abstract description 16
- 238000002788 crimping Methods 0.000 abstract description 7
- 238000010030 laminating Methods 0.000 abstract description 6
- 238000009413 insulation Methods 0.000 abstract 1
- 239000002994 raw material Substances 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 4
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- RNFJDJUURJAICM-UHFFFAOYSA-N 2,2,4,4,6,6-hexaphenoxy-1,3,5-triaza-2$l^{5},4$l^{5},6$l^{5}-triphosphacyclohexa-1,3,5-triene Chemical compound N=1P(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP=1(OC=1C=CC=CC=1)OC1=CC=CC=C1 RNFJDJUURJAICM-UHFFFAOYSA-N 0.000 description 1
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- QHSJIZLJUFMIFP-UHFFFAOYSA-N ethene;1,1,2,2-tetrafluoroethene Chemical group C=C.FC(F)=C(F)F QHSJIZLJUFMIFP-UHFFFAOYSA-N 0.000 description 1
- 239000003063 flame retardant Substances 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000000844 transformation Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/067—Etchants
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/027—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/09—Treatments involving charged particles
- H05K2203/092—Particle beam, e.g. using an electron beam or an ion beam
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
인쇄회로기판의 제조방법이 개시된다. 압착판의 일면에 표면조도를 형성하는 단계, 압착판 일면에 절연층을 코팅하는 단계, 프리프레그의 양면에 각각 절연층을 적층하고 열압착하는 단계, 절연층과 압착판을 제거하는 단계 및 프리프레그에 회로패턴을 형성하는 단계를 포함하는 인쇄회로기판의 제조방법은, 인쇄회로기판의 제조비용을 낮출 수 있으며, 동박 없이 원하는 두께의 프리프레그에 미세회로패턴을 구현할 수 있다.Disclosed is a method of manufacturing a printed circuit board. Forming a surface roughness on one surface of the pressing plate, coating an insulating layer on one surface of the pressing plate, laminating and thermally compressing the insulating layer on both sides of the prepreg, removing the insulating layer and the pressing plate, and prepregs The method of manufacturing a printed circuit board including forming a circuit pattern on a leg may lower the manufacturing cost of the printed circuit board and implement a fine circuit pattern on a prepreg having a desired thickness without copper foil.
압착판, 표면조도, 절연층, 열압착, 무동박 Crimping Plate, Surface Roughness, Insulation Layer, Thermo-Compression, Copper-Free
Description
본 발명은 인쇄회로기판의 제조방법에 관한 것이다. The present invention relates to a method of manufacturing a printed circuit board.
인쇄회로기판(Printed Circuit Board;PCB)의 원재료인 동박적층판(Copper Clad Laminated;CCL)은 각 제품별 기존 절연자재인 에폭시 계열 FR-4(Flame Retardant composition 4) 프리프레그, BT(Bismaleimide-Triazine) 프리프레그, 기타 프리프레그를 사용한다. Copper Clad Laminated (CCL), a raw material of Printed Circuit Board (PCB), is epoxy-based Flame Retardant composition 4 (FR-4) prepreg and BT (Bismaleimide-Triazine) Use prepregs and other prepregs.
CCL(Copper Clad Laminated)은 동박 사이에 프리프레그를 원하는 두께로 배열하고 핫 프레스(Hot press) 공정을 거쳐 형성되며, 에폭시 계열은 일반적으로 리지드(Rigid) PCB로 제작되고, 폴리이미드 필름(PI film)은 플렉시블(Flexible) PCB로 제작된다. 다음으로, CCL에 서브트랙티브(Subtractive), SAP(Semi Additive Process), MSAP(Modified Semi Additive Process)공법을 적용하여 회로를 구현할 수 있다. Copper Clad Laminated (CCL) is formed by arranging prepregs to a desired thickness between copper foils and through a hot press process. Epoxy series is generally made of rigid PCBs and polyimide films (PI film). ) Is made of Flexible PCB. Next, a circuit may be implemented by applying a subtractive, a semi additive process (SAP), or a modified semi additive process (MSAP) method to the CCL.
점차적으로 PCB기판의 경박 단소화로 인하여 미세회로를 구현하고, 고기능 절연 자재를 사용함으로써 회로상의 시그널 스피드(Signal speed)가 향상되는 데 중점을 두고 있다.Increasingly, the miniaturization of PCB substrates has resulted in the implementation of microcircuits and the use of high-performance insulating materials to improve signal speed on circuits.
도 1은 종래의 인쇄회로기판의 제조방법이다. CCL 제작 방식은 동박(3)과 원자재인 프리프레그(prepreg)(1)를 원하는 두께로 레이 업(lay up)하고, 스테인리스 스틸(SUS)(5) 사이에 lay up한 원자재를 플레이트(7)를 이용하여 핫 프레스(hot press) 시켜 적층한다.1 is a manufacturing method of a conventional printed circuit board. The CCL manufacturing method lays up the copper foil (3) and the raw material prepreg (1) to a desired thickness, and lays up the raw material layed between the stainless steel (SUS) (5) and the plate (7). It is laminated by hot pressing (hot press) using.
원자재인 프리프레그(1) 종류에 따라 에폭시 계열은 FR-4 CCL, 폴리이미드필름은 FCCL(Flexible Copper Clad Laminated), PTFE(Poly Tetra Fluorine ethylene)은 PTFE CCL로 명칭한다. 동박은 절연층 외곽층에 놓이게 되고 회로를 형성하는 도체로 사용되어지며, Subtractive공법에 의해 회로 패턴을 형성할 수 있다.According to the kind of prepreg (1), the epoxy series is FR-4 CCL, the polyimide film is FCCL (Flexible Copper Clad Laminated), and PTFE (Poly Tetra Fluorine ethylene) is called PTFE CCL. The copper foil is placed on the outer layer of the insulating layer and is used as a conductor for forming a circuit, and a circuit pattern can be formed by a subtractive method.
종래의 CCL 제작 방식은 동박(3)과 동박(3)사이에 프리프레그(1)를 lay up하고 이러한 배열을 SUS(5)와 SUS(5) 사이에 배열하여 반복적으로 1 패널(panel)에서 10 panel이 제작되도록 배열하여 핫 프레스 시킨다. In the conventional CCL manufacturing method, the
그러나, 종래의 방법으로 제조된 CCL을 SAP 공정으로 진행하기 위해서, 동박층을 에칭하고 무전해 화학동이나 건식공정인 진공증착을 통하여 회로를 형성하면, 회로의 선폭을 미세하게 구현할 수 없을 뿐만 아니라, 동박의 제조비용과 에칭공정 비용이 증가하게 된다.However, in order to proceed the CCL manufactured by the conventional method to the SAP process, when the copper foil layer is etched and the circuit is formed through vacuum deposition, which is an electroless chemical copper or a dry process, the line width of the circuit cannot be minutely realized. As a result, the manufacturing cost and the etching process cost of the copper foil are increased.
또한, CCL 제작 시 동박을 제거한 프리프레그를 레이 업 하여 적층공정을 진행할 경우, SUS에 절연자재의 레진(resin)이 달라붙게 되어 원하는 두께의 원자재를 제작할 수 없는 문제점이 있다.In addition, when laminating the prepreg from which the copper foil is removed during the CCL manufacturing process, the resin of the insulating material adheres to the SUS, and thus there is a problem in that a raw material having a desired thickness cannot be manufactured.
본 발명은 인쇄회로기판의 제조비용을 낮출 수 있으며, 동박 없이 원하는 두께의 프리프레그에 미세회로패턴을 구현할 수 있는 인쇄회로기판의 제조방법을 제공한다.The present invention can reduce the manufacturing cost of a printed circuit board, and provides a method of manufacturing a printed circuit board that can implement a fine circuit pattern on a prepreg of a desired thickness without copper foil.
본 발명의 일측면에 따르면, 압착판의 일면에 표면조도를 형성하는 단계, 압착판 일면에 절연층을 코팅하는 단계, 프리프레그의 양면에 각각 절연층을 적층하고 열압착하는 단계, 절연층과 압착판을 제거하는 단계 및 프리프레그에 회로패턴을 형성하는 단계를 포함하는 인쇄회로기판의 제조방법이 제공된다.According to one aspect of the invention, the step of forming a surface roughness on one surface of the pressing plate, coating an insulating layer on one surface of the pressing plate, laminating an insulating layer on both sides of the prepreg and thermo-compression bonding, the insulating layer and Provided is a method of manufacturing a printed circuit board, including removing a crimping plate and forming a circuit pattern on the prepreg.
표면조도를 형성하는 단계 이전에, 압착판의 일면을 에칭용액을 이용하여 부식시키는 단계를 더 포함할 수 있다.Prior to forming the surface roughness, the surface of the pressing plate may be further corroded using an etching solution.
에칭용액은, 염화 제2철 용액 또는 구리 염화물 용액일 수 있고, 표면조도를 형성하는 단계에서, 표면조도는 0.2㎛ 내지 10㎛의 범위일 수 있다.The etching solution may be a ferric chloride solution or a copper chloride solution, and in the step of forming the surface roughness, the surface roughness may be in the range of 0.2 μm to 10 μm.
절연층을 코팅하는 단계에서, 절연층은 PTFE(Poly Tetra Fluorine Ethylene), PI(Polyimide), LCP(Liquid Crystal Polymer), TPI(Thermal Polyimide), FEP(Fluorinated Ethylene Propylene copolymer), FA(PerFluoroAlkoxy), ETFE(Ethylene-Tetra Fluoro Ethylene), PVDF(PolyVinyliDen Fluoride), ECTFE(Ethylene-ChloroTriFluoroEthylene), PCTFE(Poly- chlorotrifluoro Ethylene) 및 PFA(Perfluoroalkoxy Fluororesins)로 이루어질 수 있다.In the step of coating the insulating layer, the insulating layer is PTFE (Poly Tetra Fluorine Ethylene), PI (Polyimide), LCP (Liquid Crystal Polymer), TPI (Thermal Polyimide), FEP (Fluorinated Ethylene Propylene copolymer), FA (PerFluoroAlkoxy), Ethylene-Tetra Fluoro Ethylene (ETFE), PolyVinyliDen Fluoride (PVDF), Ethylene-ChloroTriFluoroEthylene (ECTFE), Poly-chlorotrifluoro Ethylene (PCTFE) and Perfluoroalkoxy Fluororesins (PFA).
절연층을 코팅하는 단계 이후에, 절연층의 표면에 플라즈마 처리 또는 이온빔 처리하는 단계를 더 포함할 수 있다.After coating the insulating layer, the method may further include plasma treatment or ion beam treatment on the surface of the insulating layer.
열압착하는 단계는, 150℃ 내지 400℃의 온도범위로 열을 가하여 수행될 수 있다.The step of thermocompression may be performed by applying heat to a temperature range of 150 ° C to 400 ° C.
회로패턴을 형성하는 단계는, 프리프레그에 포토레지스트를 적층하는 단계, 회로패턴을 형성할 위치에 상응하여 포토레지스트의 일부를 선택적으로 제거하는 단계, 프리프레그에 금속층을 증착하는 단계 및 프리프레그에 잔류하는 포토레지스트를 제거하는 단계를 포함할 수 있으며, 금속층을 증착하는 단계는, 전해도금 또는 스퍼터링함으로써 수행될 수 있다.Forming a circuit pattern includes laminating a photoresist on the prepreg, selectively removing a portion of the photoresist corresponding to the position where the circuit pattern is to be formed, depositing a metal layer on the prepreg, and And removing the remaining photoresist, and depositing the metal layer may be performed by electroplating or sputtering.
본 발명에 따른 인쇄회로기판의 제조방법은, 인쇄회로기판의 제조비용을 낮출 수 있으며, 동박 없이 원하는 두께의 프리프레그에 미세회로패턴을 구현할 수 있다.The method of manufacturing a printed circuit board according to the present invention can lower the manufacturing cost of the printed circuit board and implement a fine circuit pattern on a prepreg having a desired thickness without copper foil.
본 발명은 다양한 변환을 가할 수 있고 여러 가지 실시예를 가질 수 있는 바, 특정 실시예들을 도면에 예시하고 상세한 설명에 상세하게 설명하고자 한다. 그러나, 이는 본 발명을 특정한 실시 형태에 대해 한정하려는 것이 아니며, 본 발명의 사상 및 기술 범위에 포함되는 모든 변환, 균등물 내지 대체물을 포함하는 것으로 이해되어야 한다. 본 발명을 설명함에 있어서 관련된 공지 기술에 대한 구체적인 설명이 본 발명의 요지를 흐릴 수 있다고 판단되는 경우 그 상세한 설명을 생략한다.As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.
제1, 제2 등의 용어는 다양한 구성요소들을 설명하는데 사용될 수 있지만, 상기 구성요소들은 상기 용어들에 의해 한정되어서는 안 된다. 상기 용어들은 하나의 구성요소를 다른 구성요소로부터 구별하는 목적으로만 사용된다. Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.
본 출원에서 사용한 용어는 단지 특정한 실시예를 설명하기 위해 사용된 것으로, 본 발명을 한정하려는 의도가 아니다. 단수의 표현은 문맥상 명백하게 다르게 뜻하지 않는 한, 복수의 표현을 포함한다. 본 출원에서, "포함하다" 또는 "가지다" 등의 용어는 명세서상에 기재된 특징, 숫자, 단계, 동작, 구성요소, 부품 또는 이들을 조합한 것이 존재함을 지정하려는 것이지, 하나 또는 그 이상의 다른 특징들이나 숫자, 단계, 동작, 구성요소, 부품 또는 이들을 조합한 것들의 존재 또는 부가 가능성을 미리 배제하지 않는 것으로 이해되어야 한다.The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.
이하, 본 발명의 실시예를 첨부한 도면들을 참조하여 상세히 설명하기로 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명의 일 실시예에 따른 인쇄회로기판의 제조방법을 나타낸 순서도이고, 도 3 내지 도 10은 본 발명의 일 실시예에 따른 인쇄회로기판의 제조방법 을 나타낸 단면도이다.2 is a flowchart illustrating a method of manufacturing a printed circuit board according to an embodiment of the present invention, and FIGS. 3 to 10 are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an embodiment of the present invention.
도 3 내지 도 10을 참조하면, 압착판(102), 절연층(104), 프리프레그(106), 포토레지스트(108), 금속층(110) 및 회로패턴(112)이 도시되어 있다.3 to 10, the
본 발명은 동박 없이 원하는 두께의 프리프레그를 레이 업하여 적층하고 무동박 형태의 원자재 계면과 금속과의 밀착력을 확보하여 미세회로패턴을 구현할 수 있는 것을 특징으로 한다.The present invention is characterized in that it is possible to implement a fine circuit pattern by laying up and laminating a prepreg of a desired thickness without copper foil and securing adhesion between the raw material interface and the metal in the form of a copper foil.
이를 위해 먼저, 압착판(102)의 일면을 에칭용액을 이용하여 부식시킨다(S10). 여기서, 압착판(102)은 적층 부자재를 의미하고, 본 실시예에서는 스테인리스 스틸 플레이트(SUS Plate)를 사용한다. To this end, first, one surface of the
또한, 압착판(102)의 일면은 압착판(102)과 원자재인 레진(resin)이 접촉할 부분을 의미한다. 레진은 본 실시예에서 프리프레그(106)라고 명명한다. 따라서, 압착판(102)과 원자재인 프리프레그(106)가 맞 닿는 부분을 에칭용액을 이용하여 부식시킨다. 이 공정은 압착판(102)에 후술할 절연층(104)의 코팅을 원활하게 해 줄 수 있다.In addition, one surface of the
사용하는 에칭용액은, 염화 제2철(FeCl2) 용액 또는 구리 염화물(CuCl2) 중 어느 하나로 이루어 질 수 있다.The etching solution to be used may be made of either ferric chloride (FeCl 2) solution or copper chloride (CuCl 2).
다음으로, 도 3에 도시된 바와 같이, 압착판(102)의 일면에 표면조도를 형성한다(S20). 표면조도 형성 공정은 압착판(102) 표면을 브러쉬 롤러(brush rolle)를 이용하여 가공한다. 따라서, 압착판(102) 표면의 마이크로 조도(micro roughness)를 원하는 Ra, Rz값으로 형성하도록 한다. Next, as shown in Figure 3, to form a surface roughness on one surface of the pressing plate 102 (S20). In the surface roughness forming process, the surface of the
이때 표면조도는 Ra 값을 기준으로 0.2㎛ 내지 10㎛의 범위인 것이 바람직하다. 압착판(102)의 표면을 원하는 조도로 형성하면, 압착판(102)에 적층될 원자재인 프리프레그(106)의 표면 조도를 조절할 수 있기 때문에, 프리프레그(106)에 형성될 미세회로패턴인 금속층(110)과의 밀착력을 조절할 수 있다.At this time, the surface roughness is preferably in the range of 0.2㎛ 10㎛ based on Ra value. When the surface of the
다음으로, 도 4에 도시된 바와 같이, 표면조도가 형성된 압착판(102) 일면에 절연층(104)을 코팅한다(S30). 이때, 절연층(104)은 PTFE(Poly Tetra Fluorine Ethylene), PI(Polyimide), LCP(Liquid Crystal Polymer), TPI(Thermal Polyimide), FEP(Fluorinated Ethylene Propylene copolymer), FA(PerFluoroAlkoxy), ETFE(Ethylene-Tetra Fluoro Ethylene), PVDF(PolyVinyliDen Fluoride), ECTFE(Ethylene-ChloroTriFluoroEthylene), PCTFE(Poly-chlorotrifluoro Ethylene) 및 PFA(Perfluoroalkoxy Fluororesins)로 이루어 질 수 있다. 상기 절연층(104)은 유리전이 온도가 높으며 고온에서 완전 경화 시킨다.Next, as shown in FIG. 4, the
완전 경화 시키기 전에, 절연층(104)의 표면을 플라즈마 처리 또는 이온빔 처리하여 표면조도를 조절 할 수 있다(S40).Before fully curing, the surface roughness may be adjusted by plasma treatment or ion beam treatment on the surface of the insulating layer 104 (S40).
다음으로 도 5에 도시된 바와 같이, 프리프레그(106)의 양면에 각각 절연층(104)을 적층하고 열압착하여 프리프레그(106)를 고온에서 완전 경화시킨다(S50). 이때, 150℃ 내지 400℃의 온도범위로 열을 가하여 수행될 수 있는데, 경화 온도 조건이 150℃ 미만일 경우, 프리프레그(106)의 경화가 완전히 이루어지지 않고 경화되는데 시간이 오래 걸리는 문제점이 있다. 또한, 경화 온도 조건이 400℃를 초과할 경우, 프리프레그(106)가 녹을 수 있는 문제점이 있다.Next, as shown in FIG. 5, the
이로써, B-stage 상태인 에폭시 계열의 프리프레그(106)를 원하는 두께로 레이 업하고, 표면조도가 형성된 압착판(102)을 부자재로 하여 프리프레그(106)와 절연층(104)이 코팅된 압착판(102)을 적층함으로써, 프리프레그(106)를 C-stage 상태인 무동박 기판(unclad CCL)으로 제조할 수 있다.As a result, the
형성된 무동박 기판에 SAP 공정을 이용한 미세회로패턴을 형성하기 위하여 금속과의 밀착력을 높이기 위해, 프리프레그의 표면조도를 0.1㎛ 내지 10㎛의 범위로 조절할 수 있다.The surface roughness of the prepreg may be adjusted in the range of 0.1 μm to 10 μm in order to increase the adhesion with the metal in order to form a fine circuit pattern using the SAP process on the formed copper foil substrate.
다음으로, 도 6에 도시된 바와 같이, 절연층(104)과 압착판(102)을 제거하고(S60), 프리프레그(106)에 회로패턴(112)을 형성하기 위하여, 도 7에 도시된 바와 같이, 프리프레그(106)에 포토레지스트(108)를 적층한다(S72). 포토레지스트(108)는 드라이필름(dry film)일 수 있다.Next, as shown in FIG. 6, in order to remove the
다음으로, 도 8에 도시된 바와 같이, 회로패턴(112)을 형성할 위치에 상응하여 포토레지스트(108)의 일부를 선택적으로 제거하고(S74), 도 9에 도시된 바와 같이, 프리프레그(106)에 전해도금 또는 스퍼터링(sputtering) 방법을 이용하여 금속층(110)을 증착시킨다(S76). Next, as shown in FIG. 8, a portion of the
프리프레그(106)의 표면조도를 조절하였기 때문에 프리프레그(106)에 형성되는 미세 금속층(110)은 원활하게 증착될 수 있다.Since the surface roughness of the
마지막으로, 도 10에 도시된 바와 같이, 프리프레그(106)에 잔류하는 포토레지스트(108)를 제거한다(S78). 이로써, 동박이 없는 프리프레그(106)인 무동박 기판에 미세회로패턴(112)을 형성할 수 있다(S70). 따라서, 프리프레그(106)에 동박 이 형성되고 에칭되는 공정이 필요하지 않아 기판의 제조비용을 절감할 수 있다. Finally, as shown in FIG. 10, the
상기에서는 본 발명의 바람직한 실시예를 참조하여 설명하였지만, 해당 기술 분야에서 통상의 지식을 가진 자라면 하기의 특허 청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.
도 1은 종래의 인쇄회로기판의 제조방법.1 is a manufacturing method of a conventional printed circuit board.
도 2는 본 발명의 일 실시예에 따른 인쇄회로기판의 제조방법을 나타낸 순서도.2 is a flowchart illustrating a method of manufacturing a printed circuit board according to an embodiment of the present invention.
도 3 내지 도 10은 본 발명의 일 실시예에 따른 인쇄회로기판의 제조방법을 나타낸 단면도.3 to 10 are cross-sectional views showing a method of manufacturing a printed circuit board according to an embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
102 : 압착판 104 : 절연층102: pressing plate 104: insulating layer
106 : 프리프레그 108 : 포토레지스트106: prepreg 108: photoresist
110 : 금속층 112 : 회로패턴110: metal layer 112: circuit pattern
Claims (9)
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10247780A (en) | 1997-03-04 | 1998-09-14 | Ibiden Co Ltd | Multilayer wiring board and manufacture thereof |
| JPH10313177A (en) * | 1997-05-14 | 1998-11-24 | Nec Toyama Ltd | Manufacture of multilayered printed wiring board |
| JP2001177253A (en) * | 1999-12-21 | 2001-06-29 | Hitachi Ltd | Method for manufacturing multilayer printed circuit board |
| JP2002076628A (en) | 2000-08-28 | 2002-03-15 | Sumitomo Metal Electronics Devices Inc | Manufacturing method of glass ceramic substrate |
-
2007
- 2007-10-02 KR KR1020070099230A patent/KR100948641B1/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10247780A (en) | 1997-03-04 | 1998-09-14 | Ibiden Co Ltd | Multilayer wiring board and manufacture thereof |
| JPH10313177A (en) * | 1997-05-14 | 1998-11-24 | Nec Toyama Ltd | Manufacture of multilayered printed wiring board |
| JP2001177253A (en) * | 1999-12-21 | 2001-06-29 | Hitachi Ltd | Method for manufacturing multilayer printed circuit board |
| JP2002076628A (en) | 2000-08-28 | 2002-03-15 | Sumitomo Metal Electronics Devices Inc | Manufacturing method of glass ceramic substrate |
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