KR100948575B1 - Metal-Insulator-Metal Capacitor Using Silicon Wet Etch and Method of Manufacturing the Same - Google Patents

Abstract

The present invention is a metal-insulator-metal (MIM) capacitor of a novel structure implemented on a multi-chip module (MCM-D) substrate, a mask for forming a mask pattern for a metal-insulator-metal capacitor on a silicon substrate And a thin film forming step of wet etching the substrate, controlling the mask pattern, and sequentially forming a metal layer, an insulating film, and a metal layer in the etched region.

MIM Capacitor, Wet Etch, Silicon Single Crystal, Inverted Pyramid Groove

Description

MIM Capacitor Assisted by Silicon Wet Etching and manufacturing method

The present invention is a novel metal-insulator-metal (MIM) capacitor implemented on a multi-chip module (MCM-D) substrate, which is a decoupling capacitor in silicon-based System-on-Package (SOP) technology. Can be used as

Recent trends in electronic systems can be summarized as a decrease in power supply, an increase in current, and an increase in clock speed, making it increasingly difficult to distribute noise-free power throughout the system. Decoupling capacitors solve this problem, whereas surface mount capacitors are not efficient for decoupling due to parasitic inductance, while embedded capacitors have much lower parasitic inductance, which can be useful for decoupling high power chips.

Recently, researches on making embedded decoupling capacitors in the form of metal-insulating film-metal (MIM) have been actively conducted. In order to realize high capacitance (about 1-100 nF) required for decoupling, the capacitance per unit area of the embedded capacitor is increased. Efforts to increase have been successful in delivering high-density capacitances of tens to tens of nF / mm2. However, these conventional techniques have been implemented in a three-dimensional structure through a multi-layer metal-insulating layer-metal stack (MIM stack) or silicon deep etching, which is complicated and expensive to manufacture devices. It has a disadvantage.

1 is a cross-sectional view of a three-dimensional MIM capacitor developed by NXP Semiconductors. Deep etching the silicon substrate through a process called Bosch dry etching and forming MIM capacitors on the surface, which greatly increases the effective capacitance per unit area, resulting in a high capacity capacitance of about 25 nF / mm2. It was.

However, the process of performing deep etching at such a high aspect ratio is an expensive process having a very low etching rate and a very low throughput because of a single wafer process.

SUMMARY OF THE INVENTION An object of the present invention is to provide a metal-insulator-metal capacitor which can be manufactured in a simple and inexpensive process and can secure a high capacity at a small capacity.

Another object of the present invention is to provide a method for manufacturing an embedded decoupling metal-insulator-metal capacitor, which is implemented in a multichip module-deposited (MCM-D) method in a fast process.

It is still another object of the present invention to provide a method for fabricating a metal-insulator-metal capacitor which is carried out simultaneously in the formation of other elements or structures so that the process is not added separately.

The object of the present invention is a mask pattern step of forming a mask pattern for a metal-insulator-metal capacitor on a <100> silicon substrate, an etching step of wet etching the substrate, removing the mask pattern and the etched A metal-insulator-metal capacitor manufacturing method comprising a thin film forming step of sequentially forming a metal layer, an insulating film, and a metal layer in a region. Preferably, the mask pattern has a net shape in which a plurality of rectangular windows are aligned, and in the etching step, the silicon substrate is etched until an inverted pyramid-shaped groove region is formed in each rectangular window of the mask pattern. In addition, the mask is preferably a nitride film or an oxide film.

Another object of the present invention is achieved by a metal-insulator-metal capacitor composed of at least one inverted pyramidal groove formed in a silicon substrate, a metal layer formed on the groove, an insulating film on the metal layer and a metal layer on the insulating film. Here, it is preferable that the reverse pyramid-shaped grooves each have a slope of 52 ° to 58 °.

The metal-insulator-metal capacitor according to the present invention has the advantage of being manufactured in a simple and inexpensive process while ensuring a high capacity at a small capacity.

In addition, the metal-insulator-metal capacitor according to the present invention has the advantage that it can be embedded in a multichip module (MCM-D, multichip module-deposited) in a fast and simple process.

In addition, the metal-insulator-metal capacitor manufacturing method according to the present invention is performed at the same time when forming the other device or structure has the advantage of high efficiency by not adding a separate process.

The terms or words used in this specification and claims are not to be construed as being limited to their ordinary or dictionary meanings, and the inventors may appropriately define the concept of terms in order to best describe their invention. It should be interpreted as meaning and concept corresponding to the technical idea of the present invention based on the principle that the present invention.

Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A and 2B are conceptual views illustrating a method of manufacturing a metal-insulator-metal (MIM) capacitor according to an embodiment of the present invention.

An etching mask pattern 201 as shown in FIG. 2A is formed in a region where a metal-insulator-metal (MIM) capacitor is to be formed on a silicon single crystal substrate having a <100> plane. The etching mask pattern 201 may use an oxide film, a nitride film, or the like, which may be used as a wet etching mask of silicon. The etching pattern is a form in which rectangular windows 202 are arranged to form one or a plurality of inverted pyramidal grooves, and each window 202 is preferably square.

The silicon substrate is wet etched through the etching mask pattern 201. For wet etching, an etching solution such as potassium hydroxide (KOH), which can etch a silicon single crystal substrate, is used. Since the silicon substrate has a <100> plane, the etching is performed along the <111> plane of the silicon crystal as the etching proceeds. Is done. When the etching process is completed, inverse pyramid-shaped grooves as shown in FIG. 2B are formed in regions corresponding to the respective windows. The wet etching process is faster than the conventional trench capacitor because the etching rate is faster than the dry etching process used for etching silicon single crystal substrate.

The etching process is not performed through an additional mask or etching process in the existing process, it is using the mask and the etching process used in the existing MCM-D substrate process as it is. That is, in the conventional MCM-D substrate process, the ground bump structure shown in FIG. 3 is formed through silicon wet etching for easy ground connection. In this case, the capacitor structure of the present invention is formed on the same mask to simultaneously form the groove structure in the same process. Can be formed. Therefore, the manufacture of the capacitor using the silicon wet etching proposed in the present invention can be said to be an efficient method without additional manufacturing cost or time.

The above etching mask 201 is removed to form a metal layer 303 (see FIG. 3) that will form the lower electrode of the capacitor in the region where the etched metal-insulator-metal (MIM) capacitor will be formed. An insulating film 302 (see FIG. 3), which is a dielectric layer of the capacitor, is formed on the metal layer 303 (see FIG. 3), and a metal layer 301 (see FIG. 3), which will form the upper electrode of the capacitor, is formed on the insulating film. The upper lower metal layer 303 (see FIG. 3), the insulating layer 302 (see FIG. 3), and the upper metal layer 301 (see FIG. 3) require separate masks. The upper metal layers may be formed of a metal such as aluminum or copper, or polysilicon doped with a high concentration of impurities, and in particular, the lower metal layer may be formed by doping a high concentration of impurities on the surface of the substrate itself. As the insulating film 302 (see FIG. 3), a silicon oxide film, a nitride film, a composite layer thereof, or another high dielectric material may be used. After the metal-insulator-metal (MIM) capacitor is formed, a benzocyclobutene (BCB) layer is formed, planarized, and a via hole for electrical contact is formed to connect each metal layer of the capacitor with the signal line ( 3).

3 is a structural diagram of a metal-insulator-metal (MIM) capacitor according to an embodiment of the present invention. As described above, the flip chip bonding S-I bump 305 is formed together with the capacitor groove 304 in the contact portion with the signal line. Typical thin-film multichip module-deposited (MCM-D) technology consisting of silicon substrate 300, benzocyclobutene (BCB), multilayered metals 301 and 303, and insulating film 302 The implementation of the embedded capacitor in the form of MIM. The metal-insulator-metal (MIM) capacitor according to the present embodiment is different from the conventional technique introduced in FIG. 1 in that, in forming a three-dimensional (3D) structure for increasing the capacitance per unit area of the capacitor, dry etching Wet etching was used instead of dry etching. That is, the silicon substrate is wet-etched with potassium hydroxide (KOH) solution to form a structure in which the reverse pyramid-type grooves are arranged, and then a MIM capacitor is implemented on the surface thereof.

Figure 4 is a scanning electron microscope (Scanning Electron Microscopy, SEM) cross-sectional photograph taken a reverse pyramid type groove structure formed when the <100> silicon substrate used in the present invention is etched with a potassium hydroxide (KOH) solution. A metal and an insulating film are deposited along the inclined surface of the groove structure formed as described above to manufacture the MIM capacitor.

FIG. 5 is a photograph of a 3D MIM capacitor fabricating a device having a structure as shown in FIG. 3 through a subsequent process such as deposition of a metal, an insulating film, and a via after the silicon wet etching process of FIG. 4.

The capacitance of the MIM capacitor according to the present invention is calculated by the following equation.

C = εA / d

(ε: dielectric constant of the insulating film constituting the capacitor (dielectric constant)

A: the area of the metal plate constituting the capacitor

d: thickness of the insulating film constituting the capacitor)

When the MIM capacitor is fabricated on the wet etched surface of the silicon substrate as shown in FIG. This increases and the capacitance C value increases by the increase amount. At this time, there is no change in the area where the capacitor is viewed from above, that is, the area occupied by the capacitor in the plane of the substrate, so that the increased effective area is converted into the gain of capacitance per unit area.

6 shows how the groove structure formed by silicon wet etching increases the effective capacitance area of the MIM capacitor. In the example of FIG. 6,

Effective Area: (17x25) x4 = 1700

Fitted Area: (17x2) x (17x2) = 1156

Capacitance gain per unit area: 1700/1156 ≒ 1.5

to be. That is, as shown in FIG. 6, the potassium hydroxide (KOH) solution etches the <100> silicon substrate at an angle of 54.75 °, thereby increasing the area of the silicon substrate by 1.5 times through wet etching. Therefore, when the MIM capacitor is manufactured through the deposition process of the metal and the insulating film along the inclined surface, the capacitance per unit area is 1.5 times higher than that when the MIM capacitor is manufactured on the plane without wet etching.

7 is a result of measuring the capacitance per unit area of the MIM capacitor and the conventional 2D capacitor according to the present invention manufactured in various sizes. Capacitors fabricated with wet-etched quasi-3D structures have capacitance values per unit area about 1.5 times higher in all sizes than capacitors fabricated without etching, which is consistent with the theoretically calculated results in Figure 5. do.

Although the present invention has been shown and described with reference to the preferred embodiments as described above, it is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Various modifications and variations are possible without departing from the spirit of the present invention and equivalents of the claims to be described below.

1 is a cross-sectional view of a conventional MIM capacitor,

Figure 2a is a mask pattern arrangement for manufacturing a metal-insulator-metal capacitor according to an embodiment of the present invention,

2B is a perspective view illustrating a groove structure formed according to a mask pattern for manufacturing a metal-insulator-metal capacitor according to an embodiment of the present invention;

3 is a structural diagram of a metal-insulator-metal capacitor according to an embodiment of the present invention;

4 is a scanning micrograph of the groove structure of Figure 2b,

5 is a photograph of a metal-insulator-metal capacitor according to an embodiment of the present invention, which is completed;

6 is a conceptual diagram illustrating an effective area increase amount of a metal-insulator-metal capacitor according to an embodiment of the present invention;

7 is a comparison diagram for comparing capacitance per unit area of a metal-insulator-metal capacitor and a conventional 2D capacitor according to an embodiment of the present invention.

<Code Description of Main Parts of Drawing>

201: mask pattern 202: window

300: silicon substrate 301: upper metal layer

302: insulating film 303: lower metal layer

304: groove structure 305: ground bump

Claims (6)

A mask pattern step of forming a mask pattern for the metal-insulator-metal capacitor on the <100> silicon substrate; An etching step of wet etching the substrate; Removing the mask pattern; And And a thin film forming step of sequentially forming a metal layer, an insulating film, and a metal layer in the etched region. The mask pattern is characterized in that the net shape is arranged a plurality of rectangular windows In the etching step, the silicon substrate is etched until an inverted pyramid-shaped groove region is formed in each rectangular window of the mask pattern. delete delete The method of claim 1, The mask pattern is a nitride film or oxide film, characterized in that the metal-insulator-metal capacitor manufacturing method. At least one inverse pyramid groove formed in the silicon substrate; A metal layer formed on the groove; An insulating film on the metal layer; And A metal layer on the insulating film Metal-insulator-metal capacitor. The method of claim 5, wherein The inverted pyramid groove is a metal-insulator-metal capacitor each side has a slope of 54.75 °.

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