KR100941629B1 - Method for manufacturing semiconductor device using dual damascene process - Google Patents

Abstract

The present invention provides a method for manufacturing a semiconductor device using a dual damascene process that can prevent via hole open defects caused by resist poisoning when forming trenches in the dual damascene process. Sequentially forming an insulating film, an etch stop film, and a low dielectric constant film on the substrate; Forming a first hard mask pattern on the low dielectric constant layer to define a trench region; Forming a second hard mask pattern on the first hard mask to define a via hole predetermined area to overlap the trench predetermined area; Forming a via hole exposing the conductive layer by sequentially etching the low dielectric constant layer, the etch stop layer, and the insulating layer using the second hard mask pattern as an etch mask; Forming a dual damascene structure by removing the first hard mask to form a trench exposing the etch stop layer; And forming a metal wiring electrically connected to the conductive layer exposed to the dual damascene structure.

Dual damascene, via holes, trenches, resist poisoning, metallization, trenches, SADD, VFDD, TFDD, hard mask.

Description

Method for manufacturing semiconductor device using dual damascene process {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING DUAL DAMASCENE PROCESS}             

1A to 1D are cross-sectional views schematically showing the dual damascene process by the via first method.

FIG. 2 is a SEM photograph showing the process cross section of FIG. 1C. FIG.

3 is a cross-sectional SEM photograph showing the process cross section of FIG. 1d.

4A to 4E are cross-sectional views illustrating a semiconductor device manufacturing process using a dual damascene process according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

40: conductive layer 41: insulating film

42: etch stop film 43: low dielectric constant film

44: first hard mask 46: second hard mask

47: photoresist pattern

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using a dual damascene process.

In general, in the manufacture of semiconductor devices, metal wiring is used to electrically connect the devices and the devices, or the wiring and the wiring.

Aluminum (Al) or tungsten (W) is widely used as the metallization material, but due to low melting point and high resistivity, it is no longer applicable to ultra-high density semiconductor devices. As ultra-high integration of semiconductor devices requires the use of materials with low specific resistance and highly reliable materials such as electromigration (hereinafter referred to as EM) and stress migration (hereinafter referred to as SM). Copper has recently been of interest as a suitable material.

The reason why copper is used as a metal wiring material is not only that the melting point of copper is relatively high as 1080 ° C. (aluminum: 660 ° C., tungsten: 3400 ° C.), but the specific resistance is 1.7 μm cm, aluminum (2.7 μΩ cm) and tungsten (5.6 μΩ). It is because it is much lower than cm).

However, the wiring process using copper has a problem that the etching is difficult and the corrosion is diffused, and thus, there is a considerable difficulty in practical use.

The single damascene process or the dual damascene process is applied to improve and put this into practical use. In particular, the dual damascene process is mainly applied.

Here, the damascene process is to form a trench by patterning a dielectric layer through a photolithography process, the conductive material such as tungsten (W), aluminum (Al), copper (Cu), etc. The conductive material other than the necessary wiring is filled in by using a technique such as etching back or chemical mechanical polishing (hereinafter referred to as CMP) to form the wiring in the trench shape formed earlier.

The damascene process, in particular the dual damascene process, is mainly used for forming bit lines, word lines, and metal interconnections such as DRAMs. In particular, the upper and lower metal interconnections are connected in a multilayer metal interconnection. Not only can the via holes to be formed at the same time, but also can eliminate the step caused by the metal wiring has the advantage of facilitating subsequent processes.

The dual damascene process is mainly referred to as Via First Dual Damascene (hereinafter referred to as VFDD), Trench First Dual Damascene (hereinafter referred to as TFDD) and Self-Align Dual Damascene (hereinafter referred to as SADD). 1A to 1D are cross-sectional views schematically illustrating a dual damascene process using a via first method, which will be described with reference to the drawings.

Referring to FIG. 1A, a first etch stop layer 11, a first insulating layer 12, a second etch stop layer 13, and a second insulating layer 14 may be formed on a conductive layer 10 such as a plug or a metal wiring. And a third etch stop layer 15, and a photoresist pattern 16 for defining a via hole is formed thereon. Here, 'V' illustrated represents a via hole planned area.

Here, the above-described first and second insulating films 12 and 14 include a multi-layered structure, and currently, low-k materials are mainly used due to RC delay, and the first to third etch stop films. (11, 13, 15) uses a nitride film series such as a silicon nitride film or a silicon oxynitride film.

In addition, a plurality of etch stop films of a nitride film-based layer serving as an etch stop layer are formed between the insulating films and on the conductive layer 10 to prevent damage to the conductive layer 10 and each insulating film according to an etching process and to obtain an etching profile. It is.

As shown in FIG. 1B, the first and second insulating layers 12 and 14 and the second and third etch stop layers 13 and 15 are selectively etched by using the photoresist pattern 12 as an etch mask. The etch stop is performed on the film 11 and then removed through a subsequent etching process to form a via hole 17 exposing the surface of the conductive layer 10, and then a photoresist pattern through a photoresist strip process. (16) is removed and the etching residue is removed by a cleaning process.

Subsequently, as shown in FIG. 1C, an anti-reflection film 18 is formed on the entire structure in which the via holes 17 are formed, which serves to prevent diffuse reflection upon exposure of the photoresist and to form the via holes 17. In order to serve as a barrier for preventing damage due to the subsequent trench etching process of the exposed conductive layer 10, the via hole 17 is formed to a thickness sufficient to fill the via hole 17.                         

The photoresist is coated on the antireflection film 18 to a predetermined thickness, and then a predetermined portion of the photoresist is selectively selected using an exposure source (not shown) such as ArF or KrF and a predetermined reticle (not shown). The photoresist pattern 19 for defining the trench structure is formed by exposing and leaving portions exposed or unexposed through the exposure process through the developing process, and then removing the etching residue through the post-cleaning process or the like. . 'T' shown represents the trench formation region. At this time, the via hole 17 region is overlapped in the trench formation region.

On the other hand, a resist poisoning phenomenon such as '20a' occurs at the top of the antireflection film 18 embedded in the via hole 17.

The resist poisoning phenomenon 20a is a NH compound (Evolving) generated from the second insulating film 14 using the low dielectric constant film in the photolithography process for forming the photoresist pattern 19 for trench formation. Caused by).

The poisoning phenomenon 20a by this poisoning mechanism serves as an etch barrier in an etching process for subsequent trench formation.

Subsequently, as illustrated in FIG. 1D, the trench 21 is formed by selectively etching the antireflection film 18 and the second insulating film 14 using the photoresist pattern 19 as an etch mask. In the via first dual damascene process, the conductive layer 10 exposed by the via hole 17 is protected by the antireflection film 18.

However, as described above, the poisoning phenomenon 20a due to the N-H-based compound serves as an etching barrier as shown by reference numeral 20b in the trench 21 etching process.

Therefore, the conductive layer 10 in the via hole 17 region is not exposed, causing device failure.

FIG. 2 is an SEM photograph showing the process cross section of FIG. 1C, and FIG. 3 is an SEM photograph showing the process cross section of FIG. 1D.

Referring to FIG. 2, in the photolithography process for forming the trench-forming photoresist pattern 19, an anti-reflection film filling the via hole 17 by NH-based compound emitted from the second insulating film 14 using the low dielectric constant film. (18) The state where the resist poisoning 20a has occurred can be confirmed at the upper end.

Referring to FIG. 3, as described in FIG. 1D, an etching barrier 20b is generated by the poisoning phenomenon, and thus, the via hole 17 is not opened.

The present invention is to solve the problems of the prior art, to provide a semiconductor device manufacturing method using a dual damascene process that can prevent via hole open defects due to resist poisoning phenomenon when forming the trench in the dual damascene process. Its purpose is to.

The present invention for achieving the above object, the step of sequentially forming an insulating film, an etch stop film and a low dielectric constant film on the conductive layer; Forming a first hard mask pattern on the low dielectric constant layer to define a trench region; Forming a second hard mask pattern on the first hard mask pattern to define a via hole predetermined area to overlap the trench predetermined area; Forming a via hole exposing the conductive layer by sequentially etching the low dielectric constant layer, the etch stop layer, and the insulating layer using the second hard mask pattern as an etch mask; Forming a dual damascene structure by removing the second hard mask pattern to form a trench to expose the etch stop layer; And forming a metal wiring electrically connected to the conductive layer exposed to the dual damascene structure.

According to an embodiment of the present invention, after a trench forming process for forming a pattern for a portion where a metal wiring is to be formed and a via forming process for forming a via hole through a double hard mask forming process, the plasma between the double hard mask pattern and the underlying interlayer insulating film is formed. After etching, the dual damascene process is effectively performed using the selective dry etching characteristics, and then the barrier metal and copper metal are deposited, and the metallization process is completed by using the nitride film used as the first hard mask layer as the CMP barrier. do.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

4A to 4E are cross-sectional views illustrating a semiconductor device manufacturing process using a dual damascene process according to an embodiment of the present invention, which will be described later in detail.

Referring to FIG. 4A, an oxide film-based insulating film 41, a nitride film-based etch stop film 42, and a low dielectric constant film 43 are formed on a conductive layer 40 such as a plug or metal wiring. A first hard mask 44 is formed in the trench to form a trench, and the photoresist pattern 45 used to form a pattern of the first hard mask 44 defining the trench region is formed on the hard mask 44. This is shown by the dotted line. Here, 't' illustrated represents a trench planned region.

On the other hand, the insulating film 41 is a BSG (Boro Silicate Glass) film, BPSG (Boro Phospho Silicate Glass) film, PSG (Phospho Silicate Glass) film, TEOS (Tetra Ethyl Ortho Silicate) film, HDP (High Density Plasma) oxide film Or USG (Undoped Silicate Glass) film or the like having a multi-layer structure, as shown in the conductive layer 40 according to the etching process between the insulating film 41 and the low dielectric constant film 43 and the conductive layer 40 above And a plurality of nitride stop films 42 serving as etch stops are formed to prevent damage to the insulating film 41 and the low dielectric constant film 43 and to obtain an etch profile. Only one stop film 42 is shown.

Here, the first hard mask 44 uses a nitride film series such as a silicon nitride film or a silicon oxynitride film.

As shown in FIG. 4B, the photoresist pattern 45 is removed through a PR strip process, a polysilicon film for a second hard mask is deposited on the entire surface, and then the photoresist pattern 47 for forming a via hole. ) And a second hard mask 46 defining the via hole predetermined region V by selectively etching the polysilicon film for the second hard mask using the photoresist pattern 47 as an etching mask.

At this time, it is important that the via hole planning area V overlaps the trench planning area t.

As the material of the second hard mask 46, a polysilicon film is used as described above, and both a doped polysilicon and an undoped polysilicon can be used.

The low dielectric constant film 46, the etch stop film 42, and the insulating film 41 are sequentially etched using the second hard mask 46 as an etch mask to form a via hole 48 exposing the surface of the conductive layer 40.

On the other hand, the nitride layer-based etch stop film is typically used on the conductive layer 40, but is omitted for simplicity of explanation.

4C shows a cross section in which the via hole 48 is formed.

In the conventional case, in the photolithography process for forming a photoresist pattern, a poisoning phenomenon due to the NH compound emitted from the low dielectric constant layer 43 occurred on the antireflective layer filling the via hole, but in the embodiment of the present invention, And the second hard masks 44 and 46 as etch masks, and photoresist patterns are formed thereon to prevent external exposure of the low dielectric constant film 43 during the photoresist pattern formation. Therefore, the poisoning phenomenon can be prevented.

Next, the trench 49 is formed by removing the second hard mask 46.

FIG. 4D shows a process cross section in which the trench 49 and the via hole 48 are formed simultaneously to form a dual damascene structure.

FIG. 4E illustrates a cross-section in which a conductive film pattern for filling the via hole 48 and the trench 49 is formed, in which the barrier film 50 and the metal wiring 51 are stacked to form a low dielectric constant film 43 through the CMP. And flattened as an example.

Here, the barrier layer 50 is formed using at least one material selected from the group consisting of TiW, Ti, TiN, WN, TaW, and TaN, and the metal wiring 51 is formed of Al, Ag, Au, W, or Cu. Use of substance.

Meanwhile, in the above-described example, the conductive metal pattern 50 is formed by laminating the barrier metal film 50 and the metal wiring 51. However, the conductive film pattern includes TiW, Ti, TiN, WN, TaW, Al, W, Cu, and TaN. It is also possible to have a structure in which at least one selected from the group constitutes one metal wiring.

On the other hand, when depositing the above-described Al, W or Cu and the like (Electroless), Metal Organic Chemical Vapor Deposition (hereinafter referred to as MOCVD) method, Physical Vapor Deposition (hereinafter referred to as PVD) ) And the like.

According to the present invention made as described above, in order to overcome the problem caused by the poisoning phenomenon of the low dielectric constant film in the via first dual damascene process, the first and second hard masks are defined to define the via holes and the trenches, respectively, to obtain a low dielectric constant. It has been found through examples that the film is not directly exposed to a process resulting from photoresist pattern formation, thereby preventing the non-hole open defect caused by the poisoning phenomenon of the low dielectric constant film.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention can prevent the phenomenon of poisoning of the low dielectric constant film in the dual damascene process, and ultimately, an excellent effect of improving the yield and reliability of the semiconductor device can be expected.

Claims (6)

Sequentially forming an insulating film, an etch stop film, and a low dielectric constant film on the conductive layer; Forming a first hard mask pattern on the low dielectric constant layer to define a trench region; Forming a second hard mask pattern on the first hard mask pattern to define a via hole predetermined area to overlap the trench predetermined area; Forming a via hole exposing the conductive layer by sequentially etching the low dielectric constant layer, the etch stop layer, and the insulating layer using the second hard mask pattern as an etch mask; Forming a dual damascene structure by removing the second hard mask pattern to form a trench to expose the etch stop layer; And Forming a metal interconnect conductive to the conductive layer exposed to the dual damascene structure, The first hard mask pattern is a nitride film-based, and the second hard mask pattern is a polysilicon film, characterized in that the semiconductor device manufacturing method using a dual damascene process. delete delete The method of claim 1, The metal wiring is a semiconductor device manufacturing method using a dual damascene process, characterized in that using any one of Al, Ag, Au, W or Cu. The method of claim 4, wherein And a barrier film disposed between the metallization and the exposed conductive layer, the barrier layer using at least one selected from the group consisting of TiW, Ti, TiN, WN, TaW, and TaN. Semiconductor device manufacturing method. The method of claim 1, The metal wiring is a semiconductor device manufacturing method using a dual damascene process, characterized in that using at least one selected from the group consisting of TiW, Ti, TiN, WN, TaW, Al, W, Cu and TaN.

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