KR100940568B1 - Liquid crystal display device, thin film transistor array panel used therein - Google Patents

Abstract

The thin film transistor according to the present invention includes an insulating substrate, a gate line and a storage electrode line formed on the insulating substrate, a gate insulating film formed on the gate line, a semiconductor layer formed on the gate insulating film, and formed on the gate insulating film and intersect with the gate line. At least a portion of the passivation layer and a passivation layer having a contact line exposing the drain electrode, the semiconductor layer or the data line, the at least part of the data line being in contact with the semiconductor layer, and at least partially covering the semiconductor layer; The pixel electrode connected to the drain electrode through the contact hole, the pixel region surrounded by the gate line and the data line, has an opening, and the portion defining the opening includes a black matrix overlapping the storage electrode line or the data line or the gate line.

Organic, Black Matrix, Thin Film Transistor Display Board

Description

Liquid crystal display, and thin film transistor array panel for use

1 is a layout view illustrating a structure of a thin film transistor array panel according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the liquid crystal display including the thin film transistor array panel of FIG. 1 taken along the line II-II ';

3A, 4A, 5A, 6A, and 7A are layout views illustrating a method of manufacturing a thin film transistor array panel according to a first embodiment of the present invention according to a process sequence thereof.

FIG. 3B is a cross-sectional view of the thin film transistor array panel of FIG. 3A taken along the line IIIb-IIIb ',

FIG. 4B is a cross-sectional view of the thin film transistor array panel of FIG. 4A taken along the line IVb-IVb ′.

FIG. 5B is a cross-sectional view of the thin film transistor array panel of FIG. 5A taken along a line Vb-Vb ′,

FIG. 6B is a cross-sectional view of the thin film transistor array panel of FIG. 6A taken along the line VIb-VIb ′.

FIG. 7B is a cross-sectional view of the thin film transistor array panel of FIG. 7A taken along the line VIIb-VIIb ′,

8A is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 8B is a cross-sectional view of the liquid crystal display including the thin film transistor array panel of FIG. 8A taken along the line VIIIb-VIIIb ′ of FIG. 8A;

9A is a layout view at an intermediate stage of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention.

FIG. 9B is a cross sectional view taken along line IXb-IXb ′ of FIG. 9A;

10 is a cross-sectional view at the next step of FIG. 9B,

FIG. 11A is a layout view at the next step of FIG. 10;

FIG. 11B is a cross sectional view taken along line XIb-XIb ′ of FIG. 11A;

12A is a layout view of the next step of FIG. 11A,

12B is a cross-sectional view taken along the line XIIb-XIIb ′ of FIG. 12A.

FIG. 13A is a layout view at the next step of FIG. 12A, and FIG.

FIG. 13B is a cross sectional view taken along line XIIIb-XIIIb ′ of FIG. 13A;

14 is a cross-sectional view of a liquid crystal display according to a third exemplary embodiment of the present invention.

※ Explanation of symbols on main parts of drawing ※

110, 210: insulated substrate 121: gate line

123: gate electrode 140: gate insulating film

151, 154, 157, 159: semiconductor layer                 

161, 163, 165, 167, 169: source resistive contact region

171: data line 173: source electrode

175: drain electrode 180: protective film

181, 182: contact hole 190: pixel electrode

220: black matrix 270: common electrode

The present invention relates to a liquid crystal display device and a thin film transistor array panel used therein.

The liquid crystal display device includes a color filter display panel on which a color filter and a black matrix are formed, a thin film transistor array panel facing the color filter display panel, on which a thin film transistor, a pixel electrode, and the like are formed, and a liquid crystal filled therebetween.

The liquid crystal display may be used as a display device of various products such as a computer, a TV, a medical device, a mobile phone, a laptop, and the like. However, as these devices become higher quality, they require ever higher brightness.

Therefore, there is a method of increasing the aperture ratio of the liquid crystal display by forming a protective film of the liquid crystal display with a low dielectric constant organic material for high luminance. This has a lower dielectric constant than the conventional inorganic material, so that the pixel electrode can be expanded to a region overlapping with the data line, thereby achieving a high opening rate.                         

However, when forming the protective film using the organic material, the yield is reduced due to the difficulty in maintaining the uniformity of the organic film and minimizing the defective rate due to impurities caused by the organic film. In addition, due to the characteristics of the organic film itself, there is a problem in that the transmittance of light is decreased and luminance does not increase.

Meanwhile, the black matrix formed on the color filter display panel is formed of a chromium / chromium oxide film or the like, and the black matrix positioned at the edge of the liquid crystal display reflects light of the backlight. The reflected light is irradiated to the thin film transistor at the edge, and thus a thin film transistor made of amorphous silicon is deteriorated by the light, causing the pixels of the portion to appear brighter.

Accordingly, an object of the present invention is to solve the above problems and to provide a liquid crystal display device having a high aperture ratio and a thin film transistor display panel used therein, which can realize high luminance.

Further, another object of the present invention is to provide a liquid crystal display device capable of preventing the phenomenon in which pixels are displayed brighter.

In an exemplary embodiment of the present invention for achieving the above object, a black matrix is formed on a thin film transistor array panel using an organic material including a black pigment. At this time, the sidewalls of the black matrix are patterned into a tapered structure having a gentle inclination angle, and the tapered sidewalls overlap the signal lines.

More specifically, the thin film transistor according to the present invention may be formed on an insulating substrate, a gate line and a sustain electrode line formed on the insulating substrate, a gate insulating film formed on the gate line, a semiconductor layer formed on the gate insulating film, and an upper portion of the gate insulating film. A protective film having a data line contacting the gate line, at least a portion of which is separated from the data line, and at least a portion of which covers the drain electrode, the semiconductor layer or the data line, which is in contact with the semiconductor layer, and exposes the drain electrode. And a pixel electrode formed on the passivation layer and connected to the drain electrode through the contact hole, and having an opening in the pixel region surrounded by the gate line and the data line, and the portion defining the opening is overlapped with the storage electrode line or the data line or the gate line. Metric It includes.

The storage electrode line may include first and second storage electrode lines positioned at upper and lower edges of the pixel area and storage electrodes connected to the first and second storage electrode lines and positioned at edges of the pixel area. At this time, the sidewalls of the black matrix are formed to be inclined, and the sidewalls preferably overlap the storage electrode lines.

And the black matrix is preferably made of an organic material containing a black pigment. In addition, the storage electrode line is preferably electrically connected to the gate line of the front end.

In accordance with another aspect of the present invention, a liquid crystal display device includes a first insulating substrate, an upper panel including a common electrode formed on the first insulating substrate, a second insulating substrate facing the upper display panel, and a second insulating layer. A gate line and a data line insulated and intersected on the substrate, a thin film transistor electrically connected to the gate line and the data line, and a pixel electrode connected to the thin film transistor and a pixel electrode in a pixel region surrounded by the gate line and the data line. A lower display panel including a storage electrode line constituting a storage capacitor, a liquid crystal filled between the upper display panel and the lower display panel, and having an opening in the pixel area, and a portion defining the opening is at least a gate line or a data line or a storage electrode line. It includes a black matrix overlapping with.

The storage electrode line may include first and second storage electrode lines positioned at upper and lower edges of the pixel area and storage electrodes connected to the first and second storage electrode lines and positioned at edges of the pixel area.

The sidewalls of the black matrix are formed to be inclined, and the sidewalls preferably overlap the storage electrode lines.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is directly above another part, there is no other part in the middle.

It will now be described in detail with reference to the drawings with reference to embodiments of the present invention.

[First Embodiment]

A liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of a liquid crystal display including a thin film transistor array panel according to the first exemplary embodiment of the present invention. For example, the II-II 'line of FIG. 1 is cut out and shown.

The liquid crystal display according to the first exemplary embodiment of the present invention includes a thin film transistor array panel 100, a color filter panel 200 facing the thin film transistor panel 100, and a liquid crystal layer (not shown) injected between them. Is done.

First, the thin film transistor array panel according to the first embodiment of the present invention will be described in more detail.

1 and 2, in the thin film transistor array panel 100 according to the first embodiment of the present invention, a gate line 121 extending in one direction is formed on a transparent lower insulating substrate 110. One portion or branched portion of the gate line 121 is used as the gate electrode 123 of the thin film transistor. One end 125 of the gate line 121 may be wider than the width of the gate line 121 to receive a signal transmitted from a gate driving circuit (not shown).

First and second storage electrodes 133a and 133b and first and second storage electrode lines 131a and 131b are formed on the lower insulating substrate 110 to increase the storage capacitance of the pixel. The storage electrode lines 131a and 131b are substantially parallel to the gate line 121 and are positioned at upper and lower edges of the pixel area. The first and second storage electrodes 133a and 133b are disposed at edges of the pixel area in the form of branches of the storage electrode lines 131a and 131b, and extend in parallel with the data line 171 to be described later. The storage electrode lines 131a and 131b are connected.

In this case, the storage electrode lines 131a and 131b are separated from the gate line 121, and a common electrode voltage applied to the common electrode 270 facing the pixel electrode 190, which will be described later, may be applied. The gate signal may be transmitted by being connected to the gate line 121 of the front end transmitting the gate signal to the row.

The gate insulating layer 140 is formed on the gate line 121 and the storage electrode lines 131a and 131b to cover them.

In the predetermined region of the gate insulating layer 140, semiconductor layers 151 and 154 made of amorphous silicon that are not doped with impurities are formed. The semiconductor layers 151 and 154 include a data line semiconductor layer 151 and a channel semiconductor layer 154.

The data line resistive contact layer 161, the source resistive contact layer 163, and the drain resistive contact layer 165 are formed on the semiconductor layers 151 and 154. The source and drain ohmic contact layers 163 and 165 are spaced apart from the gate electrode 123 by a predetermined distance, and the semiconductor layer 154 therebetween is a channel part that forms a channel of the thin film transistor.

The data line 171 crossing the gate line 121 is formed on the data line ohmic contact layer 161. One end 179 of the data line 171 is preferably wider than the width of the data line 171 in order to receive a signal transmitted from a data driving circuit (not shown).

The data lines 171 and 179 are formed of branches thereof, and have a source electrode 173 partially overlapping with the source ohmic contact layer 163. The data lines 171 and 179 overlap the source electrode 173 around the gate electrode 123. On the side, a drain electrode 175 is formed to be opposed to the source electrode 173 at a predetermined distance and overlap a portion of the resistive ohmic contact layer 165.

The passivation layer 180 covering the semiconductor layer 154 is formed on the entire surface of the substrate including the data line 171 and the drain electrode 175.

The black layer 220 is formed of an organic material including a black pigment on the passivation layer 180 and has an opening in the pixel area. The black matrix 220 is formed to be wider than the width of the data line 171 and the gate line 121, and the boundary line is disposed on the storage electrodes 133a and 133b and the storage electrode lines 131a and 131b. The side wall of the black matrix 220 has a tapered structure having a gentle inclination angle in order to minimize distortion of the liquid crystal molecules due to the step in the subsequent rubbing process.                     

In this case, the liquid crystal molecules may be distorted due to the step of the black matrix 220. As a result, light leakage may occur because the light leakage and the black matrix have a gentle inclination angle, and thus the light leakage may not be sufficiently blocked at the portion where the thickness is reduced. The silver overlaps with the sustain electrodes 133a and 133b and the sustain electrode lines 131a and 131b so that light leakage is sufficiently covered by these 131a, 131b, 133a and 133b.

In the passivation layer 180, the first contact hole 181 exposing the drain electrode 175, the second contact hole 182 exposing one end 125 of the gate line 121, and the data line 171. A third contact hole 183 exposing one end portion 179 of the is formed.

In addition, the passivation layer 180 may include the gate line and the data through the pixel electrode 190 and the second and third contact holes 182 and 183, which are connected to the drain electrode 175 through the first contact hole 181. Contact assisting members 95 and 97 are connected to one end 125 and 179 of the line. In this case, the edge of the pixel electrode 190 overlaps the storage electrode lines 131a and 131b and the data line 171 with the black matrix 220 therebetween.

As described above, in the present invention, the black matrix 220 is formed on the thin film transistor array panel, and the pixel electrode 190 has the black matrix 220 having a low dielectric constant interposed therebetween with the data line 171 and the storage electrode line 131a, respectively. Overlap with 131b) to maximize the aperture ratio and at the same time minimize the coupling capacity that may occur between them.

In addition, in the structure according to the exemplary embodiment of the present invention, the organic material is removed from the pixel region, thereby maintaining high luminance while maintaining a high aperture ratio.                     

Next, a color filter display panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 1.

As illustrated in FIG. 1, red 230R, green 230G, and blue (not shown) color filters are formed on the transparent insulating substrate 210. The red 230R, the green 230G, and the blue color filters are sequentially disposed in the pixel area surrounded by the gate line 121 and the data line 171, respectively, and are formed long along the pixel column in the embodiment of the present invention. The red color 230R, the green color 230G, and the blue color filter (not shown) are alternately formed in the pixel column. The boundaries between the red 230R, the green 230G, and the blue color filter and the color filter overlap or are formed at predetermined intervals. At this time, the predetermined interval is smaller than the black matrix width.

An overcoat layer 250 made of an organic material or an inorganic material such as silicon nitride is formed on the color filter, and a common electrode 270 formed of a transparent conductive material such as ITO or IZO is formed on the overcoat layer 250. Formed.

Next, a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 3A is a layout view at an intermediate stage of manufacturing a thin film transistor array panel according to a first exemplary embodiment of the present invention, FIG. 3B is a cross-sectional view taken along line IIIb-IIIb 'of FIG. 3A, and FIG. 4A is at a next step of FIG. 3A. 4B is a cross-sectional view of the IVb-IVb 'line of FIG. 4A, FIG. 5A is a layout of the next step of FIG. 4A, FIG. 5B is a cross-sectional view of the Vb-Vb' line of FIG. 5A, and FIG. FIG. 6A is a layout view of the next step of FIG. 5A, FIG. 6B is a cross sectional view taken along the line VIb-VIb ′ of FIG. 6A, FIG. 7A is a layout view of the next step of FIG. 6A, and FIG. 7B is VIIb-VIIb of FIG. 7A. 'Is a cross-sectional view of the line.

First, as shown in FIGS. 3A and 3B, metals such as aluminum, chromium, and molybdenum are deposited on the insulating substrate 110 and patterned by a photolithography process using a mask to form gate lines 121 and 125 and a gate electrode 123. ), Sustain electrodes 133a and 133b and sustain electrode lines 131a and 131b are formed. Their side walls are formed to be tapered so that the layers formed thereon can be adhered well, and the taper inclination angle is preferably in the range of 20 to 80 degrees.

Next, as shown in FIGS. 4A and 4B, the gate insulating layer 140 is formed to cover the gate line 121 and the storage electrode lines 131a and 131b. The gate insulating layer 140 is formed of silicon oxide (SiO 2), silicon nitride (SiN x), or the like.

After that, an amorphous silicon layer not doped with impurities, an amorphous silicon layer doped with impurities are stacked on the gate insulating layer 140, and then patterning an amorphous silicon layer doped with impurities and an amorphous silicon layer not doped with impurities by a photolithography process. Thus, the ohmic contacts 161 and 160A and the semiconductor layers 151 and 154 to which the channel parts are connected are formed.

Next, as illustrated in FIGS. 5A and 5B, a single layer or a multilayer layer of aluminum or an alloy including the alloy, chromium, molybdenum, or the like including the same is stacked on the substrate and patterned by a photolithography process to form the data line 171 and the drain electrode ( 175). In this case, the sidewalls of the data lines 171, 179, the source electrode 173, and the drain electrode 175 are also inclined, and the tapered inclination angle is in a range of 20 to 80 degrees.                     

Thereafter, the channel portions of the ohmic contact layer 160A are removed using the data wires 171, 173, 175, and 179 as a mask to complete the ohmic contacts 161, 163, and 165.

As shown in FIGS. 6A and 6B, an inorganic insulating film such as silicon nitride is deposited to cover the data line 171 and the drain electrode 175 to form a protective film 180.

In addition, a black organic material is coated on the passivation layer 180 to form an organic layer, and then the organic layer is patterned by a photo process to form the black matrix 220. The organic material for forming the black matrix 220 may be formed by mixing red, green, and blue organic materials forming the color filter of the color filter display panel, for example.

Next, as shown in FIGS. 7A and 7B, one end of the first contact hole 181 and the gate lines 12 and 125 exposing the drain electrode 175 by etching the passivation layer 180 by a photolithography process. Second and third contact holes 182 and 183 exposing one end portion 179 of the portion 125 and the data line 171 are formed.

1 and 2, a transparent metal film such as indium tin oxide (ITO), indium zinc oxide (IZO), and the like is formed on the passivation layer 180 and then patterned to form the first contact hole 181. Auxiliary contact member 95 connected to one end portion 125 and 179 of the gate line and the data line through the pixel electrode 190 connected to the drain electrode 175 and the second and third contact holes 182 and 183, respectively. , 97).

Second Embodiment

8A is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 8B is a cross-sectional view of the thin film transistor array panel taken along a line VIIIb-VIIIb ′.

As shown, unlike the first embodiment, the data line 171, the drain electrode 175, and the ohmic contact layers 161, 163, 165, and 169 have the same planar pattern. The ohmic contacts 161, 163, 165, and 169 are formed in the same planar pattern except for a predetermined region of the semiconductor layers 151, 154, and 159. The predetermined region is a portion that forms a channel between the source electrode 173 and the drain electrode 175.

A method of manufacturing a thin film transistor array panel for a liquid crystal display according to the second embodiment will be described with reference to the accompanying drawings.

FIG. 9A is a layout view at an intermediate stage of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention, FIG. 9B is a cross-sectional view taken along line IXb-IXb ′ of FIG. 9A, and FIG. 10 is at a next step of FIG. 9B. 11A is a layout view of the next step of FIG. 10, FIG. 11B is a cross-sectional view of the XIb-XIb ′ line of FIG. 11A, FIG. 12A is a layout view of the next step of FIG. 11A, and FIG. 12B is FIG. 12A Is a cross sectional view taken along the line XIIb-XIIb ', FIG. 13A is a layout view in the next step of FIG. 12A, and FIG. 13B is a cross sectional view taken along the line XIIIb-XIIIb' in FIG. 13A.

First, as shown in FIGS. 9A to 9B, a metal such as chromium, molybdenum, aluminum, silver, or an alloy thereof is deposited on the transparent insulating substrate 110, and then patterned by a photolithography process to form a gate line on the substrate 110. (121, 125), gate electrode 123, sustain electrodes 133a and 133b, and sustain electrode lines 131a and 131b are formed. Their side walls are formed to be tapered so that the layers formed thereon can be adhered well, and the taper inclination angle is preferably in the range of 20 to 80 degrees.

Next, an insulating material such as silicon nitride is deposited to cover the gate lines 121 and 125 and the storage electrode lines 131a and 131b to form the gate insulating layer 140.

In addition, the amorphous silicon layer doped with impurities and the amorphous silicon layer doped with impurities are deposited on the gate insulating layer 140 to sequentially form the amorphous silicon layer 150 without the impurities and the amorphous silicon layer 160 doped with the impurities. Then, a metal layer 170 is formed on the amorphous silicon layer 160 doped with impurities by depositing a metal such as aluminum, silver, chromium, molybdenum or an alloy thereof by sputtering or the like.

As shown in FIG. 10, the photoresist films having different thicknesses are formed on the metal layer 170. The photoresist pattern PR may include a channel portion of the thin film transistor, that is, a portion (A: A region) disposed between the source electrode 173 and the drain electrode 175 to form the data lines 171, 173, 175, and 179. The thickness becomes smaller than the portion located in the portion (B: B region), and all the photoresist of the other portion (C: C region) is removed. At this time, the ratio of the thickness of the photoresist film remaining in the region A to the thickness of the photoresist film remaining in the region B should be different depending on the process conditions in the etching process to be described later. It is desirable to.

As such, there may be various methods of varying the thickness of the photoresist film according to the position. For example, the photoresist film may be formed using a slit or a semitransparent film in the form of a lattice. In addition, a photoresist film made of a reflowable material is applied and exposed using a conventional mask that is divided into a part that can completely transmit light and a part that can't completely transmit light, and then develop and reflow. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain.

As shown in FIGS. 11A and 11B, the metal layer 170 in the C region, the amorphous silicon layer 160 doped with impurities, and the amorphous silicon layer 150 not doped with impurities are formed using the photoresist pattern PR as a mask. Etching is sequentially performed to form the data line, the ohmic contact layer, and the semiconductor layers 151, 154, and 159 in which the channel portion is not separated. At this time, the photosensitive film pattern formed in the region A is removed to expose the metal layer positioned in the region A, and the semiconductor layers 151, 154, and 159 are completed.

Then, the metal layer and the ohmic contact layer positioned in the A region are removed using the remaining photoresist pattern as a mask to complete the data wirings 171, 173, 175, and 179 and the ohmic contact layers 161, 163, 165, and 169. Subsequently, ashing removes photoresist residues remaining on the surface of the metal layer in region A. In this case, the sidewalls of the data lines 171, 179, the source electrode 173, and the drain electrode 175 are also inclined, and the tapered inclination angle is in a range of 20 to 80 degrees.

As shown in FIGS. 12A and 12B, an inorganic material such as silicon nitride is coated to cover the data lines 171, 173, and 175 to form the passivation layer 180.

After the organic material including the black pigment is coated on the passivation layer 180, the black matrix 220 is formed on the passivation layer 180 by patterning by a photolithography process. The organic material for forming the black matrix 220 may be formed by mixing red, green, and blue organic materials forming the color filter of the color filter display panel, for example.

As shown in FIGS. 13A and 13B, one end of the first contact hole 181 and the gate lines 121 and 125 exposing the drain electrode 175 by etching the passivation layer 180 by a photolithography process. 125 and second and third contact holes 182 and 183 exposing one end portion 179 of the data lines 171 and 179 are formed.

Next, as illustrated in FIGS. 8A and 8B, a transparent metal film, such as ITO or IZO, is formed on the passivation layer 180 and then patterned to be connected to the drain electrode 175 through the first contact hole 181. 190, contact auxiliary members 95 and 97 connected to one end portion 125 and 179 of the gate line and the data line through second and third contact holes 182 and 183, respectively.

Third Embodiment

14 is a cross-sectional view of a liquid crystal display according to a third exemplary embodiment of the present invention.

As shown, in the third embodiment, unlike the first and second embodiments, red 230R, green 230G, and blue (not shown) color filters are formed on the passivation layer 180 of the thin film transistor array panel. . The black matrix 220 and the pixel electrode 190 are formed on the color filter.

Therefore, unlike the upper panel 200 of the first and second embodiments, the upper panel of the third embodiment includes an insulating substrate 210 and a common electrode 270 formed on the insulating substrate 210.

Except for the parts described above, they are formed in the same structure as in the first embodiment.                     

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, in the present invention, the black matrix is formed on the thin film transistor array panel, and the pixel electrode is formed so as to overlap the data line and the sustain electrode line with the black matrix having a low dielectric constant therebetween to maximize the aperture ratio. Coupling capacity that can occur between can be minimized.

In the structure according to the exemplary embodiment of the present invention, the organic material is removed from the pixel area, thereby maintaining a high aperture ratio and maintaining high luminance.

In addition, by forming a color filter together with the black matrix on the thin film transistor array panel, the process for forming a conventional upper panel can be simplified.

Claims (8)

Insulation board, A gate line and a storage electrode line formed on the insulating substrate; A gate insulating film formed on the gate line, A semiconductor layer formed on the gate insulating film, A data line formed on the gate insulating layer and intersecting with the gate line and in contact with the semiconductor layer, a drain electrode separated from the data line and in contact with the semiconductor layer; A protective film covering the semiconductor layer or the data line and having a contact hole exposing the drain electrode; A pixel electrode formed on the passivation layer and connected to the drain electrode through the contact hole; The black matrix has an opening and is formed on the passivation layer, and the portion defining the opening overlaps the storage electrode line or the data line or the gate line. Thin film transistor array panel comprising a. In claim 1, The passivation layer is a thin film transistor array panel made of an inorganic material. In claim 2, A boundary line of the pixel electrode is disposed on the black matrix. In claim 1, The black matrix is a thin film transistor array panel made of an organic material containing a black pigment. In claim 1, The opening of the thin film transistor array panel overlapping the pixel electrode. An upper display panel including a first insulating substrate and a common electrode formed on the first insulating substrate; A second insulating substrate facing the upper panel, a gate line and a data line insulated from and intersecting the second insulating substrate, a thin film transistor electrically connected to the gate line and the data line, and connected to the thin film transistor. A lower panel including a pixel electrode and a storage electrode line overlapping the pixel electrode to form a storage capacitor; A liquid crystal filled between the upper panel and the lower panel, And a black matrix overlapping the gate line, the data line, or the storage electrode line. In claim 6, The storage electrode line may include first and second storage electrode lines extending in the same direction as the gate line; And a storage electrode connecting the first and second storage electrode lines to be adjacent to the data line. In claim 7, The boundary line of the pixel electrode is positioned on the black matrix.

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