KR100939110B1 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a recess gate and a bit line, and a method of manufacturing the semiconductor device, wherein the semiconductor device includes a plurality of active regions defined by an isolation layer and recesses formed in a gate predetermined region. ; A gate electrode embedded in the recess such that a surface is planarized with the semiconductor substrate; A capping layer covering the gate electrode; And a bit line having a protrusion connected to the bit line junction region of the active region while extending in the direction of the active region between the active regions and between the active regions. By forming the gate electrode embedded in the semiconductor substrate during the recess gate process, the misalignment problem is fundamentally solved, and by using the recess gate of this type, the landing plug contact process and the bit line contact process are omitted and the bit line is immediately Since the forming process may be performed, the process may be simplified, and problems such as contact resistance may be improved, thereby improving electrical characteristics of the device.

Recess Gate, Bitline, Landing Plug Contact, Bitline Contact

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}

1 is a cross-sectional view for explaining a semiconductor device having a recess gate according to the prior art.

2A to 2C are cross-sectional views for explaining a bit line forming method according to the prior art.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

4 is a plan view illustrating a bit line formed in a cell region according to an exemplary embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

30 semiconductor substrate 31 device isolation film

32: recess 33: gate electrode

34 capping insulating film 35 photoresist pattern

34 ': capping film 36: bit line

37: Bitline spacer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a semiconductor device having a recess gate and a bitline, and a method of manufacturing the same.

As the semiconductor devices are highly integrated, the short channel effect of reducing the threshold voltage is caused as the channel length of the transistors constituting the semiconductor memory device such as DRAM is rapidly reduced. In particular, due to the reduction of the design rule (leakage) is increased due to the short-channel effect and the increase of the ion implantation, there is a problem that the refresh (refresh) characteristics are reduced. Therefore, as a way to solve these problems, a recess gate process that increases the channel length of a transistor has recently been proposed.

1 is a cross-sectional view illustrating a semiconductor device having a recess gate according to the prior art.

As shown in FIG. 1, an isolation layer 11 is formed on a semiconductor substrate 10 to define an active region, and a recess 12 is formed by etching a gate predetermined region of the active region to a predetermined depth.

Subsequently, a gate insulating film (not shown) is formed on the surface of the semiconductor substrate 10 including the recess 12.

Subsequently, the first gate electrode conductive film 13a filling the recess 12 is formed on the entire structure, and the second gate electrode conductive film 13b is formed on the first gate electrode conductive film 13a. After the gate hard mask 13c is sequentially formed, the gate pattern 13 is patterned to form the gate pattern 13.

Subsequently, source / drain ion implantation is performed on the substrate resultant to form a junction region (not shown) in the semiconductor substrate 10 on both sides of the gate pattern 13.

In such a recess gate process, an effective channel length may be increased by forming a gate pattern 13 that partially recesses its lower portion in the recess 12 and protrudes over the surface of the semiconductor substrate 10. However, there is a high possibility of misalignment between the recess 12 and the gate pattern 13, and this causes a problem of lowering the electrical characteristics of the device, such as leakage current and operating speed. In addition, the protrusion of the gate pattern 13 also makes it difficult to planarize a subsequent upper layer.

Meanwhile, after the gate process, a bit line is formed as a subsequent process, and in general, in a semiconductor memory device such as a DRAM, a landing plug contact (LPC) process and a bitline contact (bitline contact) before the bit line is formed. BLC) process must be followed sequentially. Hereinafter, these processes will be described in more detail with reference to FIGS. 2A to 2C.

2A to 2C are diagrams illustrating a bit line forming method according to the related art.

As shown in FIG. 2A, the semiconductor substrate 20 has an active region defined by the device isolation film 21. In this case, as is well known, the semiconductor substrate 20 is largely divided into a cell region and a peripheral region.

Subsequently, the gate pattern 22 and the gate spacer 23 on the sidewall thereof are formed on the semiconductor substrate 20 by a known method. In this case, the gate pattern 22 includes a gate electrode 22a and a gate capping layer 22b. In addition, although not shown in the drawing, the gate pattern 22 may be the above-described recess gate.

Subsequently, source / drain ion implantation is performed to form a junction region (not shown) in the active region of the semiconductor substrate 20 between the gate patterns 22. In this case, the junction area is divided into a "bit line junction area" to which a subsequent bit line is connected and a "storage node junction area" to which a subsequent storage node is connected.

As shown in FIG. 2B, after the first interlayer insulating film 24 is formed over the entire structure of the resultant product, the first interlayer insulating film 24 is exposed to expose the semiconductor substrate 20 between the gate patterns 22 of the cell region. 24) self-aligned contact (SAC) etching to form an opening.

Subsequently, after the conductive material filling the openings is formed, the planarization process is performed until the gate capping film 22b is exposed to form the conductive plug 25 connected to the junction region of the cell region.

Subsequently, a second interlayer insulating layer 26 is formed on the first interlayer insulating layer 24.

As shown in FIG. 2C, the second interlayer insulating layer 26 is selectively etched to form contact holes 27 for bit line contacts. More specifically, the first contact hole 27a exposing the conductive plug 25 connected to the bit line junction region of the cell region as the contact hole 27 for the bit line contact, and the active region of the peripheral circuit region are exposed. The second contact hole 27b and the third contact hole 27c exposing the gate electrode 22a in the peripheral circuit region are formed, respectively.

Subsequently, the bit line barrier metal 28, the bit line conductive layer 29, and the bit line hard mask (not shown) are sequentially formed on the entire surface including the contact hole 27, and then patterned. To form a bit line.

However, since the bit line forming process is performed under the assumption of the landing plug contact process and the bit line contact process, there is a complicated process, and in particular, a contact not-open problem and a contact resistance problem occur. Deteriorates the electrical properties of In order to solve the problem of contact resistance, additionally performing an ion implantation process, etc. further complicates the process and increases the process around time (TAT).

The present invention has been proposed in order to solve the above problems of the prior art, and by solving the problem of misalignment at the source by forming the gate electrode embedded in the semiconductor substrate during the recess gate process, and also to solve the recess gate of this type The semiconductor device and its manufacture can improve the electrical characteristics of the device by simplifying the process and improvement of the problems such as contact resistance by eliminating the landing plug contact process and the bit line contact process can be performed immediately. The purpose is to provide a method.

A semiconductor device of the present invention for achieving the above object is a semiconductor substrate comprising a plurality of active regions defined by the device isolation film and the recess formed in the gate predetermined region; A gate electrode embedded in the recess such that a surface is planarized with the semiconductor substrate; A capping layer covering the gate electrode; And a bit line extending over the semiconductor substrate between the active regions in a direction of an active region and having a protrusion connected to a bit line junction region of the active region.

In addition, another semiconductor device of the present invention for achieving the above object is a semiconductor device having a cell region and a peripheral circuit region, including a plurality of active regions defined by the device isolation film and the recess formed in the gate predetermined region A semiconductor substrate having; A gate electrode embedded in the recess such that a surface is planarized with the semiconductor substrate; A capping layer covering the gate electrode of the cell region and the gate electrode of the peripheral circuit region, except for the bit line connection gate electrode of the peripheral circuit region; And a bit line extending from an upper portion of the semiconductor substrate between an active region (hereinafter, referred to as a cell active region) of the cell region toward a cell active region and passing over the bit line connection gate electrode of the peripheral circuit region. Here, the bit line of the cell region has a protrusion connected to the bit line junction region of the cell active region.

A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a recess by etching a semiconductor substrate having a plurality of active regions a predetermined depth; Embedding a conductive film in the recess to form a gate electrode having a surface flattened with the semiconductor substrate; Performing source / drain ion implantation to form a junction region in the semiconductor substrate active region between the gate electrodes; Forming a capping layer covering an upper portion of the gate electrode; And forming a bit line on the semiconductor substrate between the active regions, the bit line having a protrusion connected to a bit line junction region of the active region while extending in an active region direction.

In addition, another method of manufacturing a semiconductor device of the present invention for achieving the above object, in the method of manufacturing a semiconductor device having a cell region and a peripheral circuit region, by etching a semiconductor substrate having a plurality of active regions to a predetermined depth. Forming a set; Embedding a conductive film in the recess to form a gate electrode having a surface flattened with the semiconductor substrate; Performing source / drain ion implantation to form a junction region in the semiconductor substrate active region between the gate electrodes; Forming a capping layer covering the gate electrode of the cell region and the gate electrode of the peripheral circuit region, except for the bit line connection gate electrode of the peripheral circuit region; And forming a bit line extending from an upper portion of the semiconductor substrate between the active regions (hereinafter, referred to as a cell active region) of the cell region toward a cell active region and passing over the bit line connection gate electrode of the peripheral circuit region. Wherein the bit line of the cell region has a protrusion connected to the bit line junction region of the cell active region.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. In general, a semiconductor substrate is largely divided into a cell region and a peripheral circuit region. In the present specification, a method of manufacturing a semiconductor device will be described based on the cell region, and only a portion of the peripheral circuit region that is different from the cell region is separately illustrated. Let's explain. 3A to 3F basically illustrate a method of manufacturing a semiconductor device in the cell region, and the same process may be performed in the peripheral circuit region unless otherwise described or added.

As shown in FIG. 3A, an isolation layer 31 is formed on the semiconductor substrate 30 to define an active region.

Subsequently, the gate predetermined region of the semiconductor substrate 30 is etched to a predetermined depth to form the recess 32, and then a gate insulating film (not shown) is applied to the surface of the semiconductor substrate 30 including the recess 32. Form.

As shown in FIG. 3B, the polysilicon film for the gate electrode is formed to a thickness such that the recess 32 is not buried in accordance with the profile of the resultant product in which the recess 32 is formed, and then an etchback process is performed. To form a polysilicon gate electrode 33a separated from each other.

As shown in FIG. 3C, a tungsten film for the gate electrode is formed to a thickness such that the recess 32 is buried in the upper part of the entire structure including the polysilicon gate electrode 33a, and then an etch back process is performed. Thus, the tungsten gate electrodes 33b are separated from each other.

That is, as a result of performing the process of FIGS. 3B and 3C, the gate electrode 33 including the polysilicon gate electrode 33a and the tungsten gate electrode 33b is embedded in the recess 32, and the gate electrode 33 The surface is planarized with the surface of the semiconductor substrate 30. In this case, the polysilicon gate electrode 33a is formed along the profile of the recess 32, and the tungsten gate electrode 33b is formed to fill the recess 32 inside the polysilicon gate electrode 33a.

As such, by forming a gate electrode embedded in the recess, the misalignment problem between the recess and the gate can be solved at the source, and it is advantageous for the planarization of the upper layer formed by a subsequent process and prevents the bridge between word lines. You can achieve various effects. In addition, this allows skipping of the landing plug contact process and the bitline contact process as a subsequent process, which will be described in more detail in the corresponding drawings below.

Subsequently, source / drain ion implantation is performed to form a junction region (not shown) in the active region of the semiconductor substrate 30 between the gate electrodes 33. In this case, the junction area is divided into a "bit line junction area" to which a subsequent bit line is connected and a "storage node junction area" to which a subsequent storage node is connected.

As shown in FIG. 3D, a capping insulating film 34 for capping the gate electrode 33 is formed on the entire structure of the resultant product in which the gate electrode 33 is formed. In this case, as the capping insulating film 34, an oxide film or a nitride film-based material is used to form a thin layer having a thickness of about 200 to 400 kPa.

Next, a photoresist pattern 35 covering the gate electrode 33 is formed on the capping insulating layer 34. Here, as described above, the bit line contact of the prior art is connected to the bit line junction region of the cell region, the active region of the peripheral circuit region, and the gate electrode of the peripheral circuit region. The object of the present invention is to omit the bit line contact and to make the bit line directly connected to the above-mentioned region, that is, the bit line junction region of the cell region, the active region of the peripheral circuit region and the gate electrode of the peripheral circuit region. Accordingly, the photoresist pattern 35 is formed to cover all of the gate electrodes 33 in the cell region, while the gate electrodes 33 connected to the conventional bit line contacts among the gate electrodes 33 in the peripheral circuit region are formed. Except for the other gate electrode 33 is formed. Hereinafter, the gate electrode 33 connected to the conventional bit line contact among the gate electrodes 33 in the peripheral circuit region is referred to as a "bit line connection gate electrode".

As shown in FIG. 3E, the capping insulating layer 34 is etched using the photoresist pattern 35 as an etching mask to form a capping layer 34 ′ covering the gate electrode 33 on the semiconductor substrate 30. do. In this case, since the etching of the capping insulating layer 34 must be performed until the semiconductor substrate 30 is completely exposed, the semiconductor substrate 30 is thus lost to some extent. As described above, the capping film 34 ′ is formed to cover all the gate electrodes 33 in the cell region, and the peripheral circuit region covers the gate electrodes 33 except for the gate electrodes for bit line connection. By opening the gate electrode for bit line connection in this way, it is possible to directly connect the bit lines in the subsequent bit line forming process.

Next, the photoresist pattern 35 is removed.

As shown in FIG. 3F, the bit line 36 forming process is performed by a known method without performing the landing plug contact process and the bit line contact process on the semiconductor substrate 30. More specifically, the bit line barrier metal 36a, the bit line conductive layer 36b, and the bit line hard mask 36c are sequentially formed on the entire surface of the resultant, and then patterned to form the bit line 36. . Subsequently, the bit line spacers 37 are formed on the sidewalls of the bit lines 36.

At this time, the bit line 36 of the cell region should be connected to the bit line junction region of the cell region. In general, since the bit line of the cell region is formed in the direction crossing the word line, that is, the active region, on the semiconductor substrate between the active regions, the bit line junction region of the cell region (for example, the center of the active region between the gate electrodes) is formed. Part of the bit line must protrude toward the bit line junction area of the active area. 4 is a plan view illustrating a bit line formed in a cell region in order to explain this. As shown in Fig. 4, the bit line has a protrusion for connecting with the center of the cell active region, that is, the bit line junction region. 3F is a cross sectional view taken along the line II ′ of FIG. 4.

On the other hand, since the bit line 36 of the peripheral circuit region is connected to the active region and the gate electrode of the peripheral circuit region, the bit line 36 is formed without a separate protrusion, and in particular, is formed on the bit line connection gate electrode of the peripheral circuit region. It is directly connected to the bit line connection gate electrode of the peripheral circuit area without a contact.

That is, the landing plug contact process may be omitted by forming a gate electrode embedded in the semiconductor substrate through the recess gate process described above, and a bridge between the word line and the bit line may be prevented by forming a capping layer on the gate electrode. Can be. In addition, the bit line of the cell region may have a protrusion connected to the bit line junction region, thereby eliminating the bit line contact process, and the bit line of the peripheral circuit region is formed directly on the bit line connection gate electrode, thereby similarly to the bit line. The contact process can be omitted. In addition, the elimination of the landing plug contact process and the bit line contact process eliminates the problem of contact resistance, thereby eliminating the need to perform additional processes such as ion implantation, thereby shortening the process TAT.

Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The semiconductor device and the method of manufacturing the same according to the present invention described above solve the problem of misalignment by forming the gate electrode embedded in the semiconductor substrate during the recess gate process, and by using the recess gate of this type, the landing Since the bit line forming process may be performed immediately by omitting the plug contact process and the bit line contact process, the process may be simplified and problems such as contact resistance may be improved, thereby improving the electrical characteristics of the device.

Claims (15)

A semiconductor substrate including a plurality of active regions defined by an isolation layer and recesses formed in a gate predetermined region; A gate electrode embedded in the recess such that a surface is planarized with the semiconductor substrate; A capping layer covering the gate electrode; And A bit line having a protrusion extending over the semiconductor substrate in the direction of an active region between the active regions and connected to a bit line junction region of the active region; Semiconductor device comprising a. In a semiconductor device having a cell region and a peripheral circuit region, A semiconductor substrate including a plurality of active regions defined by an isolation layer and having a recess formed in a gate predetermined region; A gate electrode embedded in the recess such that a surface is planarized with the semiconductor substrate; A capping layer covering the gate electrode of the cell region and the gate electrode of the peripheral circuit region, except for the bit line connection gate electrode of the peripheral circuit region; And A bit line extending from an upper portion of the semiconductor substrate between an active region (hereinafter, referred to as a cell active region) of the cell region toward a cell active region and passing over the bit line connection gate electrode of the peripheral circuit region; Including, Here, the bit line of the cell region has a protrusion connected to the bit line junction region of the cell active region. Semiconductor device. The method according to claim 1 or 2, A gate insulating layer interposed between the recess and the gate electrode A semiconductor device further comprising. The method according to claim 1 or 2, The gate electrode, A polysilicon film formed along the profile of the recess and a tungsten film embedded in the recess in which the polysilicon film is formed; Semiconductor device. The method according to claim 1 or 2, The capping film is made of an oxide film or a nitride film-based material Semiconductor device. The method of claim 5, The capping film has a thickness of 200 ~ 400Å Semiconductor device. Etching a semiconductor substrate having a plurality of active regions to a predetermined depth to form a recess; Embedding a conductive film in the recess to form a gate electrode having a surface flattened with the semiconductor substrate; Performing source / drain ion implantation to form a junction region in the semiconductor substrate active region between the gate electrodes; Forming a capping layer covering an upper portion of the gate electrode; And Forming a bit line on the semiconductor substrate between the active regions and having a protrusion connected to a bit line junction region of the active region while extending in an active region direction; Method for manufacturing a semiconductor device comprising a. In the method of manufacturing a semiconductor device having a cell region and a peripheral circuit region, Etching a semiconductor substrate having a plurality of active regions to a predetermined depth to form a recess; Embedding a conductive film in the recess to form a gate electrode having a surface flattened with the semiconductor substrate; Performing source / drain ion implantation to form a junction region in the semiconductor substrate active region between the gate electrodes; Forming a capping layer covering the gate electrode of the cell region and the gate electrode of the peripheral circuit region, except for the bit line connection gate electrode of the peripheral circuit region; And Forming a bit line extending from an upper portion of the semiconductor substrate between an active region (hereinafter, referred to as a cell active region) of the cell region toward a cell active region and passing over the bit line connection gate electrode of the peripheral circuit region; Including, Here, the bit line of the cell region has a protrusion connected to the bit line junction region of the cell active region. Method of manufacturing a semiconductor device. The method according to claim 7 or 8, After the recess forming step, Forming a gate insulating film on a surface of the semiconductor substrate including the recess Method of manufacturing a semiconductor device further comprising. The method according to claim 7 or 8, The gate electrode forming step, Forming a conductive film filling the recess on the entire structure of the resultant product in which the recess is formed; And Performing an etch back process until the surface of the semiconductor substrate is exposed; Method of manufacturing a semiconductor device. The method according to claim 7 or 8, The gate electrode forming step, Forming a polysilicon film to a thickness such that the recess is not buried along a profile of the resultant product in which the recess is formed; Etching back the polysilicon layer until the surface of the semiconductor substrate is exposed; Forming a tungsten film filling the recess on the entire structure of the resultant product in which the recess is formed; And Etching back the tungsten film until the surface of the semiconductor substrate is exposed; Method of manufacturing a semiconductor device. The method according to claim 7 or 8, The capping film is made of an oxide film or a nitride film-based material Method of manufacturing a semiconductor device. The method of claim 12, The capping film has a thickness of 200 ~ 400Å Method of manufacturing a semiconductor device. The method of claim 7, wherein The capping film forming step, Forming an insulating film for capping on the entire structure of the resultant product including the gate electrode; Forming a photoresist pattern covering the gate electrode on the capping insulating layer; And Etching the capping insulating layer using the photoresist pattern as an etch mask, and etching the capping insulating layer until the semiconductor substrate is exposed and lost by a predetermined amount. Method of manufacturing a semiconductor device. The method of claim 8, The capping film forming step, Forming an insulating film for capping on the entire structure of the resultant product including the gate electrode; Forming a photoresist pattern on the capping insulating layer to cover the gate electrode of the cell region and the gate electrode of the peripheral circuit region, except for the bit line connection gate electrode of the peripheral circuit region; And Etching the capping insulating layer using the photoresist pattern as an etch mask, and etching the capping insulating layer until the semiconductor substrate is exposed and lost by a predetermined amount. Method of manufacturing a semiconductor device.

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