KR100935581B1 - Semiconductor device and word line driver including same - Google Patents

Abstract

A semiconductor device and a word line driver including the same are disclosed. The disclosed wordline driver includes a plurality of outputs including a plurality of transistors of different sizes, each output portion being a wordline driver disposed in an output forming region having a long axis and a short axis, wherein the relatively large transistor is The channel length of is arranged in parallel with the long axis of the output forming region, and the relatively small transistor is arranged so that its channel length is parallel with the short axis of the output forming region.

Main wordline driver, active area, pitch

Description

Semiconductor device and word line driver including same {Transistor And Word Line Driver Having The Same}

1 is a circuit diagram schematically showing a general main wordline driver;

2 is a diagram illustrating a layout of an output unit constituting a general main wordline driver;

3 is a diagram illustrating a layout of a word line switching transistor constituting an output unit of FIG. 2;

4 shows a layout of a transistor according to an embodiment of the present invention;

5 is a view showing a layout of a transistor according to another embodiment of the present invention;

6 is a view showing a layout of an output unit constituting a main wordline driver according to another embodiment of the present invention; and

FIG. 7 is a diagram illustrating a layout of a word line switching transistor constituting an output unit of FIG. 6.

<Explanation of symbols for the main parts of the drawings>

110: transistor region 120: active region

120a: first region of active region 120b: second region of active region

130: gate 140a / 140b: source / drain

150a: gate electrode wiring 150b: source electrode wiring

150c: drain electrode wiring

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor device such as a transistor and a word line driver including the same.

A word line is a signal line for selecting unit cells in a semiconductor memory device. A plurality of such word lines exist in the semiconductor memory device, and a word line driver for driving the plurality of word lines is provided in the semiconductor memory device.

The word line driver decodes the row address and column address connected to the memory cell to select or deselect the word line connected to the memory cell. The word line driver may include a selection signal driver, a main word line driver, and a sub word line driver.

The main word line driver 10 may include a selector 20, a ground voltage supply 30, and an output 40 as shown in FIG. 1.

The selector 20 may be composed of first and second transistors N1 and N2. The first and second transistors N1 and N2 switch the boosted voltage VPP in response to the word line non-selection signal WLOFF.

The ground voltage supply unit 30 includes third to fifth transistors N3, N4 and N5 connected in series between the output unit 40 and the ground terminal. The third transistor N3 switches the signal provided from the output unit 40 in response to the signals BAX34 decoded in the third and fourth addresses A3 and A4, and the fourth transistor N4 switches the fifth and fourth. The signal transmitted from the second transistor N2 or the third transistor N3 is switched in response to the signal BAX56 having decoded the sixth addresses A5 and A6. The fifth transistor N5 provides a signal transmitted from the fourth transistor N4 to the ground terminal in response to the signal BAX78 decoded from the seventh and eighth addresses A7 and A8. Here, the source of the second transistor N2 of the selector 20 is connected to the drain of the fourth transistor N4. Here, the first to fifth transistors N1 to N5 are, for example, NMOS transistors.

The output unit 40 includes sixth through ninth transistors P1, P2, N6, and N7, and an inverter IN. The sixth transistor P1 may include a gate for receiving the output signal (the drain signal) of the seventh transistor P2, a source for receiving the boosted voltage VPP, and a third transistor N3 of the ground voltage supply unit 30. It includes a source connected to the drain of. The seventh transistor P2 may include a gate for receiving the output signal (drain signal) of the sixth transistor P1, a source for receiving the boosted voltage VPP, and a drain connected to the gate of the sixth transistor P1. Include. That is, the sixth and seventh transistors P1 and P2 are cross coupled. The eighth transistor N6 provides the drain signal of the seventh transistor P2 to the ground terminal in response to the word line non-selection signal WLOFF. The ninth transistor N7 provides the drain signal of the seventh transistor P2 to the ground terminal in response to the word line signal WL. The inverter IN inverts the drain signal (or drain signals of the eighth and ninth transistors) of the seventh transistor P2 and outputs it as a word line signal WL.

In this case, the main word line driver 10 includes a plurality of output units 40. Accordingly, in order to effectively arrange the plurality of output units 40 in the region defined by the main word line driver 10, as illustrated in FIG. 2, the output unit region 40a having one pitch line width is conventionally used. The elements constituting the output unit 40, for example, the sixth through ninth transistors P1, P2, N6, N7 and the inverter IN are arranged side by side. At this time, the transistors constituting the sixth to ninth transistors P1, P2, N6, and N7 and the inverter IN are arranged such that their channel length and the line width of the output region 40a are parallel.

However, the ninth transistor N7 (hereinafter referred to as a wordline switching transistor) switched in response to the wordline signal WL has a different size as its size (eg, channel length) is directly connected to the main wordline driver 10 characteristics. It should be designed relatively large compared to transistors P1, P2, and N6. At present, since the total length of the word line switching transistor N7 for smoothly driving the word line driver is about 1.18 pitch F, the word line switching transistor N7 has an area greater than or equal to the output area 40a having one pitch. Is formed. (In this case, reference numeral 41 denotes an active region, 43 a gate, 45a a gate electrode wiring, 45b a source electrode wiring, 45c a drain electrode wiring, and c a contact).

However, as the word line switching transistor N7 has a length equal to or greater than the line width of the predetermined output section 40a, the word line switching transistor N7 extends to the output section 40a and its periphery (see FIG. 3). As the word line switching transistor N7 is formed larger than the predetermined output part region 40a, the result is that the entire line width of the actual output part 40 is extended, and thus the total area of the main word line driver 10 is increased. Is increased. On the other hand, if the size of the word line switching transistor N7 is reduced, the performance of the main word line driver 10 cannot be guaranteed. Therefore, there is an urgent need for a method of reducing the footprint while securing sufficient main word line driver performance.

Accordingly, it is an object of the present invention to provide a semiconductor device which can be efficiently disposed in a limited region without reducing size.

Further, another object of the present invention is to provide a semiconductor device capable of disposing transistors of different sizes in a limited region.

Another object of the present invention is to provide a word line driver that can be efficiently disposed in a limited area and can reduce the occupied area without reducing performance.

In order to achieve the above object of the present invention, the semiconductor device of the present invention comprises a device region having a short axis and a long axis, and a transistor disposed in the device region, the channel length of the transistor, the length of its source and the The sum of the lengths of the drains is greater than the short axis length of the device region, and the transistor is disposed in parallel with the long axis of the device region so that the transistor is formed in an area defined by the device region.

In addition, a semiconductor device according to another embodiment of the present invention includes a device region having a short axis and a long axis, a first transistor disposed in the device region, and a second transistor having a channel length greater than that of the first transistor, The first transistor is arranged such that its channel length is parallel to the short axis of the device region, and the second transistor is arranged such that its channel length is parallel to the long axis of the device region.

In addition, the word line driver according to another embodiment of the present invention includes a plurality of outputs having a plurality of transistors of different sizes, each output portion is a word disposed in the output portion forming region having a long axis and a short axis The line driver, wherein the relatively large transistor has its channel length arranged in parallel with the long axis of the output forming region, and the relatively small transistor has its channel length arranged in parallel with the short axis of the output forming region. do.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

First, as shown in FIG. 4, the semiconductor substrate 100, that is, a region 110 (hereinafter, referred to as a transistor region) on which a transistor is to be formed is defined. The transistor region 110 has a short axis (or line width) defined by the first width w1. Preferably, transistor region 110 has a short axis (or line width) having a first width w1 and a long axis (length) orthogonal to and relatively long to the short axis. Therefore, the transistor region 110 may have a substantially line shape.

The active region 115 is disposed in the transistor region 110 as described above. The active region 115 is defined by, for example, forming an isolation layer (not shown). Therefore, the transistor region 110 is a region including both an isolation region (not shown) and an active region 115. At this time, the length w2 of the active region 115 is greater than the short axis length of the transistor region 110, that is, the line width w1. In the present exemplary embodiment, the length w2 of the active region 115 represents the sum of the channel length and the source / drain length of the transistor.

Conventionally, as the length of the active region 41 is arranged in parallel with the short axis of the transistor region, the active region 41 is formed larger than the transistor region. However, in the present embodiment, as the length of the active region 115 is disposed to be parallel to the long axis of the transistor region 110, that is, a channel (not shown) of a transistor to be formed later is formed with the long axis of the transistor region 110. By being arranged in parallel, transistors can be implemented within the limited transistor region 110.

In this case, the long axis of the transistor region 110 has a relatively large length compared to the short axis of the transistor region 110. Therefore, in the long axis direction of the transistor region 110, the placement density of the transistor region 110 is relatively larger than that of the short axis direction of the transistor region 110. Therefore, when the active region 115 is disposed in the long axis direction of the transistor region 110, the active region 115 can be sufficiently disposed in the transistor region 110 regardless of the line width (pitch).

The gate 130 is disposed on the active region 115. The gate 130 may be formed of a conductive layer, for example, a doped polysilicon layer, and is disposed on the first region 120a of the active region 120. Although not shown in the drawing, a gate insulating film is interposed between the gate 130 and the active region 120.

Impurities are implanted into the active regions 120 at both sides of the gate 130 to form a source 140a and a drain 140b. This completes the transistor.

In the transistor of this embodiment, the total length is larger than the short axis of the transistor, that is, the line width. In this case, the channel length thereof is disposed so as to face the long axis direction of the transistor region in order to place it in the limited transistor region. Then, as the channel length of the transistor is extended toward the relatively large major axis direction, the transistor does not exceed the range of the limited region.

Meanwhile, as shown in FIG. 5, the active region 120 may be configured in a bent form. That is, the bending of the active region 120 is performed to secure the area to be effectively contacted with the electrode wiring within the limited area. The active region 120 may include a first region 120a extending in the long axis direction of the transistor region 110, and a second region 120b extending from one end of the first region 120a. For example, the second region 120b may extend in a direction crossing the first region 120a, that is, in a short direction of the transistor region 110. In this case, the length of the first region 120a of the active region 120 corresponds to the substantially transistor length, and the second region 120b is provided for forming contacts and wirings. In this case, since the second region 120b is a region where only the contact and the wiring to be connected to the contact are formed, the second region 120b is located within the short range of the transistor region 110 even though the second region 120b extends in the short direction of the transistor region 110.

The gate 130 is disposed on the active region 120. The gate 130 may be formed of a conductive layer, for example, a doped polysilicon film, as in the above-described embodiment, and is disposed on the first region 120a of the active region 120. Impurities are injected into each of the active regions 120 at both sides of the gate 130 to form a source 140a and a drain 140b. Preferably, the source 140a is formed in the first region 120a and the second region 120b on one side of the gate 130, and the drain is formed in the first region 120a on the other side of the gate 130.

The gate electrode wiring 150a, the source electrode wiring 150b, and the drain electrode wiring 150c are formed to contact the gate 130, the source 140a, and the drain 140c, respectively. The gate electrode wiring 150a may include a first wiring 150a-1 contacting the gate 120 and a second wiring 150a-2 electrically connected to the first wiring 150a-1. have. The gate electrode wiring 150a, the source electrode wiring 150b, and the drain electrode wiring 150c may be changed in shape depending on the electrical connection state of the transistor. Here, CT of FIG. 5 shows a contact part.

6 is a diagram illustrating an arrangement of an output unit of the main word line driver according to the present embodiment.

As shown in FIG. 1, the output unit 40 of the main word line driver may include sixth through ninth transistors P1, P2, N6, and N7, and an inverter IN. A plurality is provided as well. Each of the elements P1, P2, N6, N7, and IN constituting the output unit 40 are arranged side by side in the output unit region 200 having one pitch line width as described above. In this case, the output unit 40 includes a word line switching transistor N7 having a length of one pitch or more as described above. In this embodiment, in order to arrange the word line switching transistor N7 in the output region 200 defined by one pitch line width, the channel length of the word line switching transistor N7 is set to the long axis of the output region 200. Place parallel to the direction.

Referring to FIG. 7, the first region 120a of the active region is formed in parallel with the long axis of the output unit region 200, and the second region 120b is formed from one end of the first region 120a. ) Is extended. As described above, the first region 120a constituting the active region 120 has a substantially length of a word line switching transistor, and the second region 120b has a length sufficient to secure a contact region and a wiring region. Have In addition, in order to improve the placement efficiency, the active regions 120 of the adjacent output unit region 200 may be arranged to be symmetrical with respect to the tangent of the output unit region 200. Accordingly, the active region 120 formed in two adjacent output unit regions 200 is disposed so that the second region 120b is in contact with each other.

The gate 130 is disposed above the active region 120. The source 140a and the drain 140b are formed in the active region 120 at both sides of the gate 130. For example, a source 140a is formed in the first region 120a and the second region 120b on one side of the gate 130, and a drain is formed in the first region 120a on the other side of the gate 130.

The gate electrode wiring 150a, the source electrode wiring 150b, and the drain electrode wiring 150c are formed to contact the gate 130, the source 140a, and the drain 140c, respectively.

The gate electrode wiring 150a may include a first wiring 150a-1 contacting the gate 120 and a second wiring 150a-2 connected to the first wiring 150a-1. The first wiring 150a-1 and the second wiring 150a-2 are stacked on each other with an insulating film (not shown) therebetween. In this case, the gate electrode wire 150a may extend to be electrically connected to the gate IN_G of the inverter IN constituting the output unit 40.

The source electrode wiring 150b is formed to be in contact with each of the sources 140a of the adjacent word line switching transistors N7 at the same time. As described above, since the active regions 120 of the adjacent output unit regions 200 are symmetrically disposed on the basis of tangent lines, the second regions 120b of the adjacent output unit regions 200 are in contact with each other. In this case, as the source 140a is formed in the second region 120b, the source electrode wiring 150b is formed to be commonly connected to the sources 140a of the adjacent wordline switching transistor N7.

The drain electrode wire 150c is in contact with the drain 140b and extends to be electrically connected to the gate IN_G of the inverter IN and the drain N6_D of the eighth transistor N6. Here, the connection form of the gate electrode wiring 150a, the source electrode wiring 150b, and the drain electrode wiring 150c may be changed in various forms. 6 and 7, the CT represents a contact portion. Since a plurality of contact portions CT are formed on one wire, disconnection due to a poor contact can be prevented.

According to this embodiment, when fabricating a transistor having a length equal to or greater than a limited line width, the transistor is rotated and disposed in the longitudinal direction (long axis direction) of the limited area. Accordingly, the transistor may be disposed in a predetermined region while maintaining a constant length of the transistor without extending the transistor beyond the predetermined region.

The present invention is not limited to the above embodiment.

In the present embodiment, for example, the word line switching transistor formed in the output portion of the main word line driver has been described as an example. However, the present invention is not limited thereto, and all of the transistors having a length larger than the line width of the predetermined region can be applied.

In addition, although the form of a line has been described as an example of the transistor region in the present embodiment, all of them are applied here as long as the line width and length are different.

In addition, in the present embodiment, the transistor region has a short axis and a long axis, but the short axis here means a width or line width and the long axis means a length.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. Do.

As described in detail above, according to the present invention, when fabricating a transistor having a transistor length greater than or equal to a pitch of a predetermined region, the transistor is rotated and disposed in the longitudinal direction (long-axis direction) of the predetermined region. Accordingly, the transistor may be disposed in a predetermined region while maintaining a constant length of the transistor without extending the transistor beyond the predetermined region.

Therefore, the integration density of the semiconductor device can be improved.

Claims (17)

A device region having a short axis and a long axis; And A transistor disposed in the device region; The sum of the channel length of the transistor, the length of its source and the length of its drain is larger than the short axis length of the device region, And the transistor is disposed in parallel with a long axis of the device region so that the channel length direction thereof is formed in an area defined by the device region. The method of claim 1, The transistor, An active region having a length extending in parallel with the long axis of the device region, A gate disposed over the active region; And And a source / drain disposed on both sides of the gate. The method of claim 2, The active region, A first region extending in parallel with the major axis direction of the element region; And And a second region extending from one end of the first region. The method of claim 3, wherein And the second region extends in a minor direction of the transistor region. The method of claim 3, wherein A drain is formed in the first region on one side of the gate, A source is formed in the first region and the second region on the other side of the gate. A device region having a short axis and a long axis; And A first transistor disposed in the device region and a second transistor having a channel length greater than that of the first transistor, The sum of the channel length of the first transistor, its source length and its drain length is less than the short axis length of the device region, The sum of the channel length of the second transistor, its source length and its drain length is greater than the short axis length of the device region, The first transistor has its channel length arranged in parallel with the short axis of the device region, And the second transistor has its channel length arranged in parallel with the long axis of the device region. The method of claim 6, The second transistor, An active region disposed substantially parallel to a long axis of the device region; A gate disposed over the active region; And And a source / drain formed in active regions on both sides of the gate. delete The method of claim 6, And a gate electrode wiring in contact with the gate, a source electrode wiring in contact with the source, and a drain electrode wiring in contact with the drain. A word line driver comprising: a plurality of output units each having a plurality of transistors of different sizes, and an output unit formation region having a long axis and a short axis in which the respective output parts are disposed; The total length including the channel length, source length and drain length of the transistor of the largest size among the plurality of transistors is larger than the length of the short axis of the output portion forming region, The largest size transistor has its channel length arranged in parallel with the long axis of the output forming region, And the remaining transistors are arranged such that their channel lengths are parallel to the short axis of the output portion forming region. The method of claim 10, The largest size transistor is, An active region disposed substantially parallel to a long axis of the output portion forming region; A gate disposed over the active region; And And a source / drain formed in active regions on both sides of the gate. delete The method of claim 11, The active region of the transistor of the largest size, A first region extending in parallel with a long axis direction of the output portion forming region; And And a second region extending from one end of the first region. The method of claim 13, And the second region extends in a shorter direction of the output portion forming region. The method of claim 13, A drain is formed in the first region on one side of the gate, And a source formed in first and second regions on the other side of the gate. The method of claim 15, And a gate electrode wiring contacting the gate, a source electrode wiring contacting the source, and a drain electrode wiring contacting the drain. The method of claim 10, And the largest size transistor is arranged to be symmetrical with respect to another largest size transistor disposed in an adjacent output portion forming region and a tangent of the output portion forming region.

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