KR100933554B1 - Charge pump with turn-on time control of sharing transistors - Google Patents

Abstract

The present invention relates to a charge pump (CP), and more particularly, the control signal for controlling the operation of the source switch and the control signal for controlling the operation of the sharing transistor to adjust the sharing transistor to have a constant time difference, By turning on first to reach a constant voltage level, controlling the turn-on time of the shearing transistor prevents reverse current generated after the source switch is turned off and maintains the dynamic current applied to the loop filter stably. Relates to a possible charge pump.

Description

CHARGE PUMP FOR CONTROLLABLE TURN ON TIME OF SHARING TRANSISTOR}

The present invention relates to a charge pump (CP), and more particularly, the control signal for controlling the operation of the source switch and the control signal for controlling the operation of the sharing transistor to adjust the sharing transistor to have a constant time difference, By turning on first to reach a constant voltage level, controlling the turn-on time of the shearing transistor prevents reverse current generated after the source switch is turned off and maintains the dynamic current applied to the loop filter stably. Relates to a possible charge pump.

In general, the charge pump feeds back the reference frequency of the reference divider and the output signal of the voltage controlled oscillator in a phase locked loop (PLL), and outputs the output frequency of the divided main divider. It is composed of an electronic circuit that makes a voltage change in a loop filter by pushing and pulling a certain amount of electric charges according to the pulse signal output after comparing with the circuit).

Accordingly, when a positive pulse is output from the phase detector PFD, the charge pump supplies current to the capacitor included in the loop filter by the amount of charge corresponding to the pulse width to accumulate charge to increase the voltage, and the phase detector When a negative pulse is output at PFD, the charge pump draws current from the capacitor inversely by the amount of charge corresponding to the pulse width, thereby reducing the charge and reducing the voltage.

As shown in FIG. 1, the conventional charge pump includes a current sourcing unit supplying current to the loop filter, a current sink unit drawing current from the loop filter, a reference current supply unit supplying a constant bias current, and And a sharing unit having a terminal connected to the source switch and the sink switch provided in the current sourcing unit and the current sinking unit.

In this case, the current sourcing portion is configured as a current mirror structure consisting of a PMOS transistor, and the current sinking portion is configured as a current mirror structure consisting of an NMOS transistor.

The current source unit is connected between the voltage source Vdd and the output terminal Vout, the source switch P3 to which the source control signal UP_b generated by the phase detector PFD is applied to the gate, and the reference current supply unit. The constant _currents I _{UP and REF} are configured to include first control switches P1 and P2 applied to the gate as control signals. At this time, the source switch P3 is turned on when the source control signal UP_b is 0, and the source current flows from the voltage source Vdd through the output terminal Vout to the loop filter to accumulate charge.

In addition, the current sink unit is connected between the output terminal (Vout) and the ground voltage (GND), the sink switch (N3) to which the sink control signal (DN) generated by the phase detector (PFD) is applied to the gate, The reference current supply unit is configured to include the second control switch (N1, N2) is applied to the gate as a control signal (I _{DN , REF} ). At this time, the sink switch N3 is turned on when the sink control signal DN is 1, so that the sink current flows from the output terminal Vout to the ground voltage GND to push out the charge.

In addition, the sharing unit sharing includes a first sharing transistor including an NMOS transistor having one terminal connected to one terminal of the source switch, the other terminal connected to a ground power source, and the source control signal UP_b applied to a gate. (N5) and a second sharing transistor (P5) consisting of a PMOS transistor, one terminal of which is connected to one terminal of the sink switch, the other terminal of which is connected to a voltage source, and to which the sink control signal DN is applied. It is configured by.

The charge pump of the conventional source switch type is configured such that the gates of the source switch P3 and the first sharing transistor N5 form a common node and receive the same source control signal UP_b. The gates of the sink switch N3 and the second sharing transistor P5 form a common node and receive the same sink control signal DN.

In this way, since the same source control signal UP_b is simultaneously applied to the source switch P3 and the first sharing transistor N5, when the source control signal UP_b transitions from 1 to 0, the first sharing transistor N5. ) Is turned off, but the source switch P3 is turned on so that the source current I ₁ flows through the output terminal Vout from the voltage source Vdd, and the loop filter is turned on. Will accumulate charge. But. When the source control signal UP_b transitions from 0 to 1 after the charge corresponding to the width of the phase detector output pulse is accumulated, the source switch P3 is turned off and the supply of the voltage source Vdd is disconnected. Since the first sharing transistor N5 is turned on and connected to the ground power source, the supply of the source current I ₁ is cut off.

In this case, since the source control signal UP_b is simultaneously applied to the gate of the source switch P3 and the first sharing transistor N5, the first sharing transistor N5 is turned on during the turn-off time of the source switch P3. As it is turned on, the voltage source flows to the ground power supply through the source switch P3 and the first sharing transistor N5, thereby lowering the voltage of the node a.

Accordingly, since the voltage of the output terminal Vout becomes higher than the voltage of the node a, a reverse current flows through the first control switch P2 and the node a and the first sharing transistor N5 at the output terminal Vout. As shown in FIG. 2, the value of the dynamic current I ₃ supplied to the loop filter is decreased, so that the output voltage at the output terminal is gradually decreased, so that the correct value desired to be changed in the loop filter is reduced. There was a problem that can not change the voltage.

In addition, since the same sink control signal DN is simultaneously applied to the sink switch N3 and the second sharing transistor P5, the second sharing transistor is changed when the sink control signal DN transitions from 0 to 1. FIG. P5 maintains a turn off state, but the sink switch N3 is turned on to sink current N from the capacitor of the loop filter to the ground power supply GND through the output terminal Vout. I ₂ ) flows out and repels the charge.

But. When the sink control signal DN transitions from 1 to 0 after the charge corresponding to the width of the phase detector output pulse is released, the sink switch N3 is turned off and the supply at the output terminal Vout is disconnected. In addition, since the second sharing transistor P5 is turned on and connected to the voltage source Vdd, the flow of the sink current I ₂ is blocked.

At this time, since the sink control signal DN is simultaneously applied to the gates of the sink switch N3 and the second sharing transistor P5, the second sharing transistor P5 is turned on during the turn-off time of the sink switch N3. As it is turned on, the voltage source Vdd flows to the ground power supply through the sink switch P5 and the second sharing transistor P5, thereby increasing the voltage of the node b.

Accordingly, since the voltage of the output terminal Vout becomes lower than the voltage of the node b, a reverse current flows from the node b through the second control switch N2 to the output terminal Vout, and is supplied to the loop filter. There was a problem in that the value of the dynamic current I ₃ was changed so that the voltage could not be changed to the correct value desired to vary in the loop filter.

As described above, the dynamic current supplied to the loop filter is changed by reverse current caused by the node voltage instability at the terminals of the source switch P3 and the sink switch N3 by the first and second sharing transistors. As a result of abnormal operation, there is a problem in that spurious occurs in the phase-locked loop (PLL) because the voltage for controlling the exact phase difference according to the phase comparison result in the phase detector cannot be transferred to the voltage controlled oscillator. .

The technical problem to be solved by the present invention, before the source switch and the sink switch is turned off by adjusting the transition time of the control signal in which the source switch and the sink switch is turned off and the control signal in which the sharing transistor is turned on differently. The first sharing transistor and the second sharing transistor are first turned on so that one terminal of the sharing transistor reaches a constant voltage level, thereby preventing abnormal operation of the dynamic current due to reverse current generated when the source switch and the sink switch are turned off. The present invention provides a charge pump capable of controlling the turn-on time of a sharing transistor.

The charge pump capable of controlling the turn-on time of the sharing transistor for achieving the technical problem is a charge pump for varying the voltage in the loop filter by pushing or pulling the charge according to the pulse signal of the reference frequency and the output frequency compared in the phase detector. And a source sourcing unit having a source switch generated by the phase detector and controlled by a timing controller to a gate; A current sink having a sink switch generated by the phase detector and applied to a gate of a sink control signal adjusted by a timing controller; A sharing unit comprising a sharing transistor connected to the source switch and the sink switch; And a timing controller configured to generate and supply a control signal for controlling an operation time of the sharing transistor differently from an operation time of the source switch and the sink switch.

In addition, the sharing unit according to the present invention, an NMOS transistor, one terminal is connected to the source switch consisting of a PMOS transistor, the other terminal is connected to the ground power supply, the first sharing control signal generated by the timing controller is applied to the gate A first sharing transistor consisting of; And a second sharing transistor comprising a PMOS transistor having one terminal connected to a sink switch formed of an NMOS transistor, the other terminal connected to a voltage source, and a second sharing control signal generated by the timing controller applied to a gate. It is characterized by.

In addition, the timing controller according to the present invention generates a first sharing control signal that first turns on the first sharing transistor before the source switch is turned off, and generates the second sharing transistor before the sink switch is turned off. And generate a second sharing control signal that first turns on.

In addition, the timing controller according to the present invention, the first delay cell for delaying the signal generated by the phase detector; And a flip-flop receiving the output signal of the first delay cell and outputting the first and second sharing control signals.

In addition, the first delay cell according to the invention, the output terminal is connected to the source switch and the sink switch to apply the delayed source control signal to the gate of the source switch, and the delayed sink control signal to the gate of the sink switch And recognizing a transition time point of the source control signal and the sink control signal to determine turn-on time points of the first and second sharing transistors.

In addition, the present invention applies a first sharing control signal to the gate of the first sharing transistor that the output terminal (Q) of the flip-flop transitions before the turn-off time of the source switch to turn on, the turn of the sink switch The second sharing control signal transitioning before the off time is applied to the gate of the second sharing transistor to turn on.

In addition, the present invention is connected between the output terminal (Qb) and the reset terminal (Rn) of the flip-flop to apply the output signal as a reset signal of the flip-flop to transition the first and second sharing control signal again to the first And a second delay cell which determines a time for which the second sharing transistor maintains a turn on state.

According to the present invention, the sharing control signal for turning on the sharing transistor transitions before the source and sink control signals, thereby turning on the sharing transistor first, and then turning off the source switch and the sink switch. Reduces the voltage difference between the output terminal by inducing to a certain value in advance, thereby preventing reverse current from the output terminal when the source switch and the sink switch turn off, and compensate for the up and down current mismatch of the dynamic current. Stable supply, there is an advantage that can significantly reduce the spurious (spurious) of the phase locked loop (PLL).

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 3, the charge pump capable of controlling the turn-on time of the sharing transistor according to an embodiment of the present invention includes a current sourcing unit 100 that accumulates charge by supplying current to the loop filter, and the loop filter. The current sink unit 200 receives current and draws electric charges, the reference current supply unit 300 supplying a predetermined bias current, and the sharing connected to the source switch and sink switch provided in the current sourcing unit and the current sinking unit. And a timing controller 500 for generating and supplying a sharing 400 and a control signal for adjusting a turn on time of the transistor.

The current sourcing unit 100 has a current mirror structure formed of a PMOS transistor and is connected between the voltage source Vdd and the output terminal Vout, and is generated by a phase detector PFD (UP_b) to generate a timing controller 500. The source control signal UP_bbb adjusted in step S1 is applied to the gate, and the first current control switch MP1 is applied to the gate as a control signal by the reference current I _ref from the reference current supply unit 300. MP2). At this time, the source switch MP3 is turned on when the source control signal UP_bbb is 0 so that the source current flows from the voltage source Vdd through the output terminal Vout to the loop filter to accumulate charge. The letter 'b' in the source control signal refers to 'bar'.

The source switch MP3 has one terminal connected to the voltage source Vdd and the other terminal connected to one terminal of the first control switch MP2. The source switch MP3 and the first switch MP3 are connected to one terminal of the first control switch MP2. One terminal of the first sharing transistor MN5 to be described later is connected to the common connection terminal of the switch MP2. The other terminal of the first control switch MP2 is connected to the output terminal Vout.

In addition, the current sink 200 has a current mirror structure consisting of an NMOS transistor and is connected between the output terminal Vout and the ground voltage GND, and is generated by the phase detector PFD (DN). And the sink switch MN3 to which the sink control signal DN_bb adjusted by the timing controller 500 is applied to the gate, and the reference current I _ref is applied to the gate as the control signal from the reference current supply unit 300. It is comprised including two control switches MN1 and MN2. At this time, the sink switch MN3 is turned on when the sink control signal DN_bb is 1 so that the sink current flows from the loop filter through the output terminal Vout to the ground voltage GND to push out the charge. .

The sink switch MN3 has one terminal connected to the ground voltage GND, the other terminal connected to one terminal of the second control switch MN2, and the sink switch MN3 and the second terminal. One terminal of the second sharing transistor MP5 described later is connected to the common connection terminal of the control switch MN2. The other terminal of the second control switch MN2 is connected to the output terminal Vout.

The sharing unit 400 has one terminal connected to a common terminal of the source switch MP3 and the first control switch MP2, the other terminal connected to a ground power source, and a first sharing control signal The first sharing transistor MN5 formed of an NMOS transistor to which SHP is applied, and one terminal is connected to a common terminal of the sink switch MN3 and the second control switch MN2, and the other terminal is connected to a voltage source. And a second sharing transistor MP5 made of a PMOS transistor to which the second sharing control signal SHN is applied.

As illustrated in FIG. 4, the timing controller 500 differs between a time at which the source switch MP3 is turned off and a time at which the first sharing transistor MN5 is turned on. The source control signal UP_b generated by the phase detector PFD to differently adjust the time when the sink switch MN3 is turned off and the time when the second sharing transistor MP5 is turned on. ) And a first delay cell (Delay Cell A) 510 for delaying the sync control signal (DN) and the first and second sharing control signals (SHP, SHN) received from the delayed signal from the first delay cell. ) And a second delay cell (Delay Cell B) 530 for delaying the delayed signal from the first delay cell and applying the reset signal to the reset signal of the flip-flop.

At this time, the output terminal of the first delay cell 510 is connected to the source switch MP3 and the sink switch MN3 to apply a delayed source control signal UP_bbb to the gate of the source switch MP3. The sink control signal DN_bb is applied to the gate of the sink switch MN5.

In addition, the output terminal Q of the flip-flop 520 is connected to the first sharing transistor MN5 to apply a first sharing control signal SHP, and is connected to the second sharing transistor MP5 to form a second output. It is configured to apply the sharing control signal SHN.

In this case, the timing controller Timing so that the first sharing control signal SHP transitions ahead of the source control signal UP_bbb and the second sharing control signal SHN transitions before the sync control signal DN_bb. Controller 500 is controlled. Accordingly, the first sharing transistor MN5 is turned on before the source switch MP3 is turned off, and the second sharing transistor MP5 is configured to be turned on before the sink switch MN3 is turned off. do.

In addition, the second delay cell 530 determines the time for which the first and second sharing transistors MN5 and MP5 remain turned on, and output terminal Qb and reset terminal of the flip-flop 520. The first and second sharing control signals SHP and SHN are transitioned by turning on the first and second sharing transistors by applying a delayed signal connected between Rn as a reset signal of a flip-flop. do.

Next, the operation of the charge pump capable of controlling the turn-on time of the sharing transistor according to the present invention configured as described above will be described.

5 is a timing diagram of a control signal in which a turn on time of a transistor is controlled in a timing controller according to the present invention.

Referring to FIG. 5, first, when the source control signal UP_b, which is a positive pulse, is applied to the first delay cell A of the timing controller, the source control signal delayed for a predetermined time ( UP_bbb is output and applied to the source switch MP3.

At this time, while the source control signal UP_bbb is maintained at 1, both the source switch MP3 and the first sharing transistor MN5 are turned off, and the source control signal UP_bbb transitions from 1 to 0. In this case, the first sharing transistor MN5 is still turned off, but the source switch MP3 is turned on, and thus, the output terminal M1 is turned on through the source switch MP3 and the first control switch MP2 at the voltage source Vdd. Vout), the source current I ₁ flows. The flowed source current I ₁ is transferred to the loop filter as the dynamic current I ₃ to accumulate charge in the capacitor to vary the voltage.

Subsequently, when all the charges corresponding to the output pulse of the phase detector PFD are accumulated, the first sharing control signal SHP adjusted by the timing controller is first from 0 to 1 before the source switch MP3 is turned off. Transition. Accordingly, as the first sharing transistor MN5 is turned on, a portion I _{4 of the} current flowing through the source switch MP3 flows to increase the voltage level of the node A.

After the first sharing transistor MN5 is first turned on to increase the voltage level of the node A, the source control signal UP_bbb transitioning from 0 to 1 is applied to turn off the source switch MP3. . At this time, even after the source switch is turned off, since the node A has already risen to a constant voltage level, there is no voltage difference with the output terminal Vout, and thus no reverse current flows or becomes very weak.

Next, when the sink control signal DN, which is a negative pulse, is applied to the first delay cell A of the timing controller by the phase detector PFD, the sink control signal DN_bb delayed for a predetermined time is output. It is applied to the sink switch MN3.

At this time, while the sink control signal DN_bb is maintained at 0, the sink switch MN3 and the second sharing transistor MP5 are both turned off, and the sink control signal DN_bb transitions from 0 to 1. When the second sharing transistor MP5 is still turned off, the sink switch MN3 is turned on so that the second control switch MN2 is output at the output terminal Vout to push out the charge stored in the loop filter. The sink current I ₂ flows through the and sink switch MN3 to the ground power source GND. The sink current I ₂ flowing as described above is a dynamic current I ₃ , releasing the charge accumulated in the capacitor to vary the voltage.

Thereafter, when all the charges corresponding to the output pulse of the phase detector PFD are released, the second sharing control signal SHP adjusted by the timing controller is first from 1 to 0 before the sink switch MN3 is turned off. Transition. Accordingly, while the second sharing transistor MP5 is turned on, a current I ₅ flows from the voltage source Vdd through the second sharing transistor MP5 and the sink switch MN3 to supply the voltage of the node B. Will raise the level.

After the second sharing transistor MP5 is first turned on to increase the voltage level of the node B, the sink control signal DN_bb transitioning from 1 to 0 is applied to turn off the sink switch MN3. At this time, even after the sink switch is turned off, since the node B has already risen to a constant voltage level, there is no voltage difference with the output terminal Vout, and thus no reverse current flows or becomes very weak.

As described above, the timing controller recognizes in advance the transition state between the source control signal UP_b and the sink control signal DN applied from the phase detector, and immediately before turning off the source switch MP3 or the sink switch MN3. The first sharing transistor MN5 or the second sharing transistor MP5 is turned on first so that the node A or the node B has a constant voltage level, thereby inverting the source switch MP3 or the sink switch MN3 immediately after the turn-off. It is possible to prevent fluctuations in the dynamic current caused by the current.

The first sharing control signal SHP is again returned after a predetermined time by the flip-flop 520 that receives the output of the second delay cell B 530 provided in the timing controller as a reset signal. Transitioning to 0, the second sharing control signal SHN transitions to 1 again to turn off the first and second sharing transistors MN5 and MP5.

Accordingly, the sharing control signal for turning on the first and second sharing transistors MN5 and MP5 is applied before the control signal for turning off the source switch MP3 and the sink switch MN3. 2 By maintaining one terminal of the control switch at a constant voltage level to prevent the generation of reverse current generated during the transition of the source control signal and the sink control signal, the voltage of the output terminal (Vout) is high as shown in the graph shown in FIG. It can be seen that even if it is low or low, the dynamic current can be stably maintained and the quantitative amount of the output terminal (Vout) can be modeled more accurately to obtain a result almost identical to the theoretical analysis.

That is, in the related art, the voltage distribution between the output terminal Vout and the node A and the node B is increased until the node A and the node B become constant voltage immediately after the source switch and the sink switch are turned off. While the reverse current flows, the waveform shown by the dotted lines in the source current I ₁ , the sink current I ₂ , and the dynamic current I ₃ shown in FIG. 6 is present. And when the second sharing transistors MN5 and MP5 are turned on in advance and the nodes A and B reach a predetermined voltage level first, the reverse current does not flow after the source switch MP3 and the sink switch MN3 are turned off. Therefore, the source current I ₁ , the sink current I ₂ , and the dynamic current I ₃ only show a waveform shown in a straight line.

The technical spirit of the present invention has been described above with reference to the accompanying drawings, but this is by way of example only and not by way of limitation to the present invention. In addition, it is apparent that any person having ordinary knowledge in the technical field to which the present invention belongs may make various modifications and imitations without departing from the scope of the technical idea of the present invention.

1 is a circuit diagram of a conventional charge pump,

2 is a graph of the output voltage and current using a conventional charge pump,

3 is a circuit diagram of a charge pump capable of controlling the turn-on time of a sharing transistor according to the present invention;

4 is a configuration diagram of a timing controller according to the present invention;

5 is a timing diagram of a control signal in which a turn on time of a transistor is controlled in a timing controller according to the present invention;

Figure 6 is a graph of the output voltage and current of the charge pump capable of controlling the turn on time of the sharing transistor in accordance with the present invention.

<Explanation of symbols for the main parts of the drawings>

100-current sourcing unit 200-current sinking unit

300-reference current supply part 400-sharing part

500-Timing Controller 510-First Delay Cell

520-Flip-flop 530-Second delay cell

Claims (7)

In the charge pump for varying the voltage in the loop filter by pushing or pulling the charge in accordance with the pulse signal of the reference frequency and the output frequency compared in the phase detector, A current sourcing unit including a source switch generated by the phase detector and applied to a gate of a source control signal adjusted by a timing controller; A current sink having a sink switch generated by the phase detector and applied to a gate of a sink control signal adjusted by a timing controller; A sharing unit comprising a sharing transistor connected to the source switch and the sink switch; And And a timing controller configured to generate and supply a control signal for controlling an operation time of the sharing transistor differently from an operation time of the source switch and the sink switch. The method of claim 1, The sharing part, A first sharing transistor comprising one terminal connected to a source switch formed of a PMOS transistor, the other terminal connected to a ground power source, and an NMOS transistor to which a first sharing control signal generated by the timing controller is applied to a gate; And One terminal connected to a sink switch formed of an NMOS transistor, the other terminal connected to a voltage source, and a second sharing transistor made of a PMOS transistor to which a second sharing control signal generated by the timing controller is applied to a gate. A charge pump that can control the turn-on time of sharing transistors. The method of claim 2, The timing controller, A second sharing control signal that generates a first sharing control signal that first turns on the first sharing transistor before the source switch is turned off, and a second sharing control signal that first turns on the second sharing transistor before the sink switch is turned off Charge pump capable of controlling the turn-on time of the sharing transistor, characterized in that configured to generate. The method of claim 3, The timing controller, A first delay cell for delaying the signal generated by the phase detector; And And a flip-flop for receiving the output signal of the first delay cell and outputting the first and second sharing control signals. The method of claim 4, wherein The first delay cell has an output terminal connected to the source switch and the sink switch to apply a delayed source control signal to the gate of the source switch, and apply a delayed sink control signal to the gate of the sink switch. The charge pump capable of controlling the turn-on time of the sharing transistor, characterized in that for determining the turn-on time of the first and second sharing transistors by recognizing the transition time of the sink control signal. The method of claim 4, wherein The output terminal Q of the flip-flop is turned on by applying a first sharing control signal that transitions before the turn-off time of the source switch to the gate of the first sharing transistor, and transitions before the turn-off time of the sink switch. And a second sharing control signal applied to a gate of the second sharing transistor to turn on the charging transistor. The method according to any one of claims 4 to 6, The first and second sharing transistors are connected between the output terminal Qb and the reset terminal Rn of the flip-flop to apply an output signal as a reset signal of the flip-flop to transition back the first and second sharing control signals. The charge pump capable of controlling the turn-on time of the sharing transistor, characterized in that further comprises a second delay cell for determining the time to maintain the turn on state.

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