KR100929831B1 - Semiconductor memory device for high speed data input / output - Google Patents

Abstract

The present invention can reliably align the output data in a semiconductor memory device operating at a high speed to increase the reliability of the operation. To this end, the semiconductor memory device according to the present invention comprises a first serialization means for serializing the eight data input in parallel to output four consecutive data and to add the preamble data to each of the four data according to the operation mode, Second serialization means for receiving the output of the first serialization means and outputting two consecutive data, and third serialization means for receiving the output of the second serialization means and outputting the serialized data. Therefore, the present invention can prevent distortion of a signal generated due to delay or interference in outputting data.

Data Output, Semiconductor, Memory Device, Serializer, Preamble

Description

Semiconductor memory device for high speed data input / output {SEMICONDUCTOR MEMORY APPARATUS FOR HIGH SPEED DATA INPUT / OUTPUT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device capable of operating at high speed, and more particularly, to a data output control circuit and an operation method for aligning a plurality of data output to the outside and controlling a preamble in a semiconductor memory device operating at a high speed.

In a system composed of a plurality of semiconductor devices, the semiconductor memory device is for storing data. When data is requested from a data processing device such as a central processing unit (CPU), the semiconductor memory device outputs data corresponding to an address input from a device requesting data, or at a position corresponding to the address. Stores data provided from the data requesting device.

BACKGROUND OF THE INVENTION As the operating speed of a system composed of semiconductor devices becomes faster and technology related to semiconductor integrated circuits develops, semiconductor memory devices have been required to output or store data at a higher speed. In order for a semiconductor memory device to operate safely at a higher speed, several circuits in the semiconductor memory device must be able to operate at a high speed, and also a signal or data can be transferred at a high speed.

In order to speed up the operation of the semiconductor memory device, a plurality of internal operations that occur internally may be executed faster, or speeds of input / output of signals and data may be increased. In an example, a double data rate (DDR) semiconductor memory device outputs data in synchronization with a falling clock as well as a rising edge of a system clock in order to output data faster. Since two data can be input and output at one cycle of the system clock from one input / output stage of the semiconductor memory device, the input / output speed of the data is faster than that of the conventional semiconductor memory device. A semiconductor memory device capable of inputting and outputting four data has been proposed.

In order to output data at high speed, a prefetch operation has been used internally from a digital semiconductor memory device. Here, the prefetch operation refers to bringing the data or command to the storage means for operating at high speed before the data or command is processed. For example, a DDR semiconductor memory device (DDR SDRAM) employs an operation of accessing two bits of data from a memory cell and outputting the data pad to a data pad every one clock cycle. This operation is referred to as a two-bit prefetch operation. In addition, the digital2 semiconductor memory device (DDR2 SDRAM) employs a 4-bit prefetch operation, a method of accessing 4-bit data from a memory cell and outputting the data to a data pad every one clock cycle. Similarly, the DRAM3 semiconductor memory device (DDR3 SDRAM) employs an 8-bit prefetch operation that accesses 8-bit data from a memory cell and outputs it to a data pad every one clock cycle. As such, the semiconductor memory device had to increase data input / output speed in order to enable high-speed operation in response to a clock signal having a high frequency. As a result, each data input / output pad may be executed by a single read or write command. An operation method of reading or writing data corresponding to the minimum burst length (DQ) at one time is adopted. This method is called an N bits prefetch operation. N at this time is equal to the minimum burst length.

As described above, the recently proposed semiconductor memory device is required to input and output four data in one cycle of the system clock, and employs an 8-bit prefetch operation for high-speed input and output of such data. Eight data outputs corresponding to one read command from a unit cell are transferred in parallel through a corresponding sense amplifier and a data input / output line. In order to output the data transferred in parallel through one data pad, it must be serialized. To control this operation, the semiconductor memory device includes a plurality of data output circuits connected to each of the plurality of data input / output pads.

Meanwhile, the semiconductor memory device cuts leakage current to reduce power consumption and cuts off unnecessary current to reduce malfunction and damage. In general, the output terminal of the input / output signal pad maintains a high impedance (Hi-z) state. That is, before and after the semiconductor memory device outputs the data strobe signal and the like through the input / output signal pad or before or after the signal is transmitted from the outside, the output terminal of the input / output signal pad maintains a high impedance (HI-z) state. Doing. When the output signal is applied to the output terminal maintaining the high impedance state, it takes a certain time until the level of the output terminal transitions to the logic level of the first applied output signal. For this reason, the output timing of the first input / output signal output through each input / output signal pad of the semiconductor memory device may be deformed or distorted due to a delay or the like, which may lower reliability in the operation of the semiconductor memory device. In order to overcome this drawback, the semiconductor memory device transitions the output stage to a logic high or low level instead of a high impedance (Hi-z) state before the output signal is output through the output terminal of the input / output pad. The signal is called a preamble.

For example, in the case of a DDR, DDR2, or DDR3 semiconductor memory device, the above-described preamble is performed on the data strobe signal DQS. The data strobe signal DQS is for indicating that data output through the plurality of data pads DQ of the semiconductor memory device are valid values and should be able to be output at a predetermined time point. However, if there is a delay in transmitting the data strobe signal DQS out of the high impedance (Hi-z) state, the valid window of the first data becomes smaller than other data output after the first data. Disadvantages may occur, and preambles have been performed to prevent this.

However, as the data input / output speed of the semiconductor memory device becomes faster, it is difficult to accurately maintain the data output point only by performing the preamble only on the data strobe signal DQS. If the preamble is performed not only on the data strobe signal DQS but also on each of the plurality of data pads DQ from which the data is output, the first output data is subjected to inter-symbol interference (ISI) like the data to be output thereafter. It can be less affected and guarantee a valid window. Accordingly, recently proposed semiconductor memory devices require the data pad DQ to include operation modes for selectively performing a preamble.

The present invention is to improve the reliability of the operation by aligning the output data in the semiconductor memory device operating at a high speed, which may occur in the input and output process of the data by selectively outputting the preamble data pattern to the data transmitted therein Its feature is that it is possible to prevent distortion of data due to delay or skew.

The present invention serializes eight data input in parallel, outputs four consecutive data, and transfers the first serialization means and the first serialization means for outputting the preamble data to each of the four data according to the operation mode. And a second serialization means for receiving and outputting two consecutive data, and a third serialization means for receiving the output of the second serialization means and outputting serialized data.

In addition, the present invention receives four data input in parallel and outputs four consecutive data having four times the data window of each window of the serialized eight data and preamble data to each of the four data according to the operation mode A second serializer for outputting two consecutive four data having a data window twice as large as each window of eight data serialized by receiving the output of the first serializer; And a third serialization unit configured to receive the output of the second serialization unit and output serialized data.

Furthermore, the present invention provides eight consecutive data which are transmitted from the internal unit cell in parallel to the read command and outputted as four consecutive data, and the preamble data is added to each of the four data according to the operation mode. Operation of a semiconductor memory device comprising a first serialization step, a second serialization step for outputting four consecutive data as two consecutive data, and a third serialization step for outputting two consecutive data as serialized data Provide a method.

A semiconductor memory device that is required to operate at a high speed should be able to input and output more data in a short time in response to a system clock. To this end, the semiconductor memory device according to an embodiment of the present invention outputs data corresponding to a read command. In this case, by selectively outputting only data or outputting a predetermined preamble data pattern together before outputting data, a distortion of a signal generated in the data input / output process is prevented. In particular, the semiconductor memory device according to an embodiment of the present invention transitions the logic level similarly to the actual operation other than the preamble of the fixed logic level (logical low level) performed on the data strobe signal DQS in the conventional semiconductor memory device. A plurality of preamble patterns having a predetermined length are set and applied to an output terminal before outputting data according to an operation mode. Specifically, the present invention allows the data output timing to be precisely adjusted while selectively outputting the preamble pattern in the data output circuit for serializing the data output in the semiconductor memory device and delivered in parallel.

According to the present invention, a plurality of preamble patterns can be selectively output to a data output circuit for serializing data output in parallel in a semiconductor memory device, so that signal distortion does not occur due to delay or interference in data output. There is an advantage to avoid.

Specifically, the semiconductor memory device using the embodiment of the present invention can ensure the effective window of the first output data by selectively outputting the preamble pattern similar to the actual output data before the data output, and further Since a preamble pattern may be commonly performed in a plurality of data pads, skew between data signals may be prevented due to a difference in design process in each of the plurality of data pads.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

1 is a block diagram illustrating a data output circuit of a semiconductor memory device according to an embodiment of the present invention.

As shown, the data output circuit serializes eight data input in parallel and outputs four consecutive data, and according to an operation mode, a first serialization unit 100A for appending and outputting preamble data to each of the four data. ), The second serializer 100B for receiving the output of the first serializer 100A and outputting two consecutive data, and the eight serialized data for receiving the output of the second serializer 100B. And a third serialization unit 100C for outputting.

Here, the first serialization unit 100A outputs preamble data according to an operation mode, and then displays four data D4 to D7 among the eight data D0 to D7, respectively. First and second phase shifters 110A and 110B for shifting the phase by 4 times (4UI), other four data D0 to D3 of the eight data, and the first and second phase shifters ( Multiplexes the outputs of 110A and 110B to latch the outputs of the first and second multiplexers 120A and 120B and the first and second multiplexers 120A and 120B to output four consecutive two data. First and second latch portions 130A and 130B are included.

First, the operation of the data output circuit when the preamble data is not output will be described. Specifically, odd-numbered data D0, D2, D4, and D6 of the eight data D0 to D7 transmitted in parallel are serially paired and serialized by the first multiplexer 120A. To this end, the first phase shifter 110A first delays two data D4 and D6 among odd-numbered data by a window 4UI of data aligned by the first and second multiplexers 120A and 120B. Move it. Similarly, even-numbered data D1, D3, D5, and D7 are serialized and aligned using the second phase shifter 110B and the second multiplexer 120B. Four data paired by two data by the first and second multiplexers 120A and 120B are latched by the first and second latch units 130A and 130B, respectively. Here, each data window of four data including two consecutive data output from the first and second latch units 130A and 130B in the first serialization unit 100A is output from the third serialization unit 100C. 4 times each window of 8 serialized data.

In addition, the second serializer 100B, which receives four data output from the first and second latch units 130A and 130B, serializes two data D2-D6 and D3-D7 of the four data. Third and fourth phase shifters 140A and 140B for shifting the phase by two times (2UI) of each data window of eight data, and two other data among the four data (D0-D4 and D1-D5) And a third for outputting two consecutive four data (D0-D2-D4-D6, D1-D3-D5-D7) by multiplexing the outputs of the third and fourth phase shifters 140A and 140B. And fourth and fourth latch portions 160A, 160B for latching outputs of fourth multiplexers 150A, 150B and third and fourth multiplexers 150A, 150B.

Specifically, the third and fourth phase shifters 140A and 140B may include two pieces of data D2 among the four data output from the first and second latch units 130A and 130B in the first serializer 100A. -D6, D3-D7) are delayed by using the divided clocks WCK / 2 and WCKB / 2 generated by dividing the data clocks WCK and WCKB at half frequency. Here, the data clocks WCK and WCKB are used as a reference for outputting eight serialized data, and the system clock has a frequency twice as high as the frequency. The newly proposed semiconductor memory device has a data clock WCK and WCKB. Output two data during one cycle of). That is, the data window UI of each of the eight serialized data corresponds to half of the period of the data clocks WCK and WCKB. Each of the third and fourth phase shifters 140A and 140B uses two divided clocks WCK / 2 and WCKB / 2, each of which is four times the data window UI of each of the eight serialized data periods. (D2-D6, D3-D7) Delay each phase by twice the data window UI of each of the eight serialized data. Thereafter, each of the third and fourth multiplexers 150A and 150B is phased by the third and fourth phase shifters 140A and 140B among the four data output from the first and second latch units 130A and 130B. The two delayed data (D2-D6, D3-D7) are aligned with the other two data (D0-D4, D1-D5), respectively, so that two consecutive four data (D0-D2-D4-D6, D1-D3-D5-D7) is output. Finally, the third and fourth latch units 160A and 160B latch and output the outputs of the third and fourth multiplexers 150A and 150B to the third serializer 100C.

Finally, the third serialization unit 100C serializes one data D1-D3-D5-D7 of two consecutive four data D0-D2-D4-D6 and D1-D3-D5-D7. A fifth phase shifter 170 for shifting the phase by each data window UI of the eight data data and two consecutive four data (D0-D2-D4-D6, D1-D3-D5-D7) Multiplexing the outputs of the other one (D0-D2-D4-D6) and the fifth phase shifter 170 to obtain the serialized eight data (D0-D1-D2-D3-D4-D5-D6-D7). And a fifth multiplexer 180 for outputting.

Referring to FIG. 1, the data output circuit corresponds to a read data output signal RDOUTEN for activating data output in response to a read command and a divided clock WCK / 2 of the data clock WCK as a reference for the data output. The first control pulse POUT_CL15P for controlling the first and second phase shifters 110A and 110B in the first serializer 100A, and the second for controlling the first and second multiplexers 120A and 120B. The serialization control unit 190 may further include a control pulse POUT_CL15 and a data transfer signal DOFFB for controlling the first and second latch units 130A and 130B.

In the following, the operation of the data output circuit will be described when outputting preamble data. First, when the preamble signal DQ_PREAMBLE is activated, the serialization control unit 190 may enable the first pattern enable signal EN0101 or the second pattern enable in response to the first pattern signal PATTERN0101 or the second pattern signal PATTERN1010. Activate signal EN1010. Here, the first pattern signal PATTERN0101 and the second pattern signal PATTERN1010 are used to determine the configuration of the preamble data. Specifically, when the first pattern signal PATTERN0101 is activated, the data output circuit before the serialized data D0-D1-D2-D3-D4-D5-D6-D7 is output from the fifth multiplexer 180. Four preamble data corresponding to '0101' are output. In addition, when the second pattern signal PATTERN1010 is activated, the data output circuit may include four corresponding to '1010' before the serialized data D0-D1-D2-D3-D4-D5-D6-D7 is output. Output preamble data.

In order to output four preamble data corresponding to '0101' in response to the first pattern signal PATTERN0101, the first phase shifter 110A phase shifts two data D4 and D6 input in parallel. After outputting two preamble data corresponding to the previous '0', the two data D4 and D6 are transferred after phase shift. At this time, the second phase shifter 110B outputs two preamble data corresponding to '1' and then outputs two data D5 and D7 before phase shifting the other two data D5 and D7 input in parallel. Pass after phase shift. The first multiplexer 120A delivers two preamble data corresponding to '0' before the first data D0 to be output in synchronization with the rising edge of the data clock, and the second multiplexer 120B polls the data clock. Two preamble data corresponding to '1' are delivered before the first data D1 to be output in synchronization with the edge. The four preamble data transmitted through the first and second multiplexers 120A and 120B are aligned before the first output data D0 that is aligned through the second serializer 100B and the third serializer 100C. .

On the other hand, when the second pattern signal PATTERN1010 is activated, in order to output four preamble data corresponding to '1010', the first phase shifter 110A receives two data D4 and D6 input in parallel. Two preamble data corresponding to '1' are output before the phase shift. In addition, the second phase shifter 110B outputs two preamble data corresponding to '0' before phase shifting two data D5 and D7 input in parallel. Through this, as in the method of outputting four preamble data corresponding to '0101', the data control circuit may output four preamble data corresponding to '1010'.

FIG. 2 is a waveform diagram illustrating an operation of the semiconductor memory device shown in FIG. 1. In particular, the operation of the data output circuit in the semiconductor memory device when the preamble data is not output will be described with reference to the data clock WCK and the divided clock WCK / 2. 2 illustrates an example of a GDDR5 semiconductor memory device in which the frequency of the divided clock WCK / 2 is the same as the frequency of the system clock and outputs four data during one period tCK of the system clock.

As shown in the drawing, the semiconductor memory device stores eight serialized data (D0-D1-D2-D3-D4-D5-D6-D7) serialized from the time after the cas delay time CL after the read command is applied. Output Specifically, in the semiconductor memory device, the read data output signal RDOUTEN corresponding to the read command is activated at a time point earlier than the cas delay time CL by 4tCK (4 periods of the system clock). Thereafter, the serialization control unit 190 in the data output circuit generates a plurality of signals for controlling the first serialization unit 100A in response to the read data output signal RDOUTEN. In addition, the plurality of data D0 to D7 output from the internal unit cell is transferred to the data output circuit at a time point that is 2.5 tCK earlier than the cas delay time CL.

The plurality of data D0 to D7 are transferred to the data output circuit in parallel. The data output circuit serializes a plurality of data D0 to D7 input in parallel and outputs eight consecutive data D0-D1-D2-D3-D4-D5-D6-D7. First, the serialization controller 190 activates the first control pulse POUT_CL15P at a time point that is 1.5 tCK earlier than the cas delay time CL in response to the read data output signal RDOUTEN. The first and second phase shifters 110A and 110B in the first serializer 100A correspond to the activated first control pulses POUT_CL15P, and the four data D4 to D7 of the plurality of data D0 to D7. D7) delays the phase by 1tCK (4UI).

In addition, the serialization control unit 190 activates the second control pulse POUT_CL15 to a logic high level at a time point that is 1.5 tCK earlier than the cas delay time CL, such as the first control pulse POUT_CL15P. At this time, the inversion signal POUT_CL15B of the second control pulse POUT_CL15 is at a logic low level. In response to the inverted signal POUT_CL15B of the second control pulse POUT_CL15 and the second control pulse POUT_CL15, the first and second multiplexers 120A and 120B are connected to four data D0 to D3 input in parallel. The other four data D4 to D7 whose phases are shifted through the first and second phase shifters 310A and 310B are serialized. After four consecutive two data (D0-D4, D2-D6, D1-D5, D3-D7) are generated through the first and second multiplexers 120A and 120B, the first and second latch units ( The 130A and 130B respectively transmit four pieces of data to the second serializer 100B in response to the data transfer signal DOFFB output from the serialization controller 190.

Of the four data transferred to the second serializer 100B, two data D2-D6 and D3-D7 are input to the third and fourth phase shifters 140A and 140B and delayed by 0.5 tCK (2UI). do. Thereafter, the third and fourth multiplexers 150A and 150B are divided into four pieces of data, namely, two data delayed by the third and fourth phase shifters 140A and 140B and the first and second latch units 130A and 130B. Receives 2 undelayed data output from) and serializes it into 2 data. The two serialized data are transferred to the third serializer 100C through the third and fourth latch units 160A and 160B, respectively. In particular, each of the third and fourth latch units 160A and 160B transfers data before 0.25 tCK of the cas delay time CL corresponding to the falling edge of the data clock WCK. 4, four data (D0-D4, D2-D6, D1-D5, D3-) transmitted to the input terminals (d0, d1, d2, d3) of the third and fourth multiplexers (150A, 150B). D7) and the second serialization unit (D0-D2-D4-D6, D1-D3-D5-D7) at the output terminals d4 and d5 of the third and fourth multiplexers 150A and 150B. The operation of 100B) can be confirmed.

The data D1-D3-D5-D7 transmitted to the third serializer 100C through the fourth latch unit 160B is delayed in phase by the UI corresponding to the fifth phase shifter 170. Through the third latch unit 160A, the fifth multiplexer 180 is 0.25 tCK (half period of the data clock WCK) earlier than the cas delay time CL, that is, synchronized with the falling edge of the data clock WCK. When delivered to, one data D0-D2-D4-D6, rdo, which is delivered, starts to be output by the fifth multiplexer 180 in synchronization with the rising edge of the data clock WCK. On the other hand, after another data (D1-D3-D5-D7, fdo) delayed through the fifth phase shifter 170 is transferred to the fifth multiplexer 180 in synchronization with the rising edge of the data clock WCK. Output is started in synchronization with the falling edge of the data clock WCK by the fifth multiplexer 190. Through the above-described process, eight serialized data in which eight data D0 to D7, which have been transmitted in parallel since the cas delay time CL after the read command is applied, are serialized by the data output circuit and continuously output. Data is output as D0-D1-D2-D3-D4-D5-D6-D7.

3 is a block diagram illustrating the serialization control unit 190 shown in FIG. 1.

As shown in the drawing, the serialization control unit 190 corresponds to the read data output signal RDOUTEN and the divided clock WCK / 2, and the first control pulse POUT_CL15P, the second control pulse POUT_CL15 and POUT_CL15B, and the data transfer signal. (DOFFB), and a plurality of flip-flops 191, 192, 193 and first to third latches 196, 197, and 198 for outputting the first and second preamble enable signals enb0101 and enb1010. .

Specifically, the first latch 196 outputs a first control pulse POUT_CL15P for controlling the first and second phase shifters 110A and 110B in response to the read data output signal RDOUTEN. The second latch 197 has a second control pulse (POUT_CL15, POUT_CL15B) having an activation period equal to twice (1 tCK) in the period of the data clock WCK for controlling the first and second multiplexers 120A and 120B. Outputs In addition, the third latch 198 outputs a data transfer signal DOFFB having an activation interval of four times (2tCK) in the period of the data clock, and the fourth and fifth latches 303 and 304 are preambles. When the signal DQ_PREAMBLE is activated, the first and second pattern enable signals enb0101 and enb1010 are output in response to the first and second pattern signals PATTERN0101 and PATTERN1010.

Specifically, if the read data output signal RDOUTEN is activated to a logic high level at a time point CL-4 that is four cycles earlier than the cas delay time CL after the read command is applied, a plurality of flip-flops are provided. Reference numerals 191, 192, and 193 phase shift the read data output signal RDOUTEN in response to the divided clock WCK / 2. The first flip-flop 191 transitions the output terminal N1 to a logic high level at a time point CL-3 that is three cycles earlier than the cas delay delay CL. As a result, the NAND gate 302 is connected to the output of the third inverter 305 and the first flip-flop 191 to invert the logic level of the output terminal N3 of the third flip-flop 193. The logic low level is output after performing an AND operation corresponding to the logic level of the output terminal N1. Each of the fourth and fifth latches 303 and 304 receives the output of the negative AND gate 302 and receives the first and second pattern enable signals when the first and second pattern signals PATTERN0101 and PATTERN1010 are activated. enable enb0101, enb1010) to a logic low level. In addition, the logical product of the preamble signal DQ_PREAMBLE and the output terminal N1 of the first flip-flop 191 (that is, the point of time CL-3 which is three cycles earlier than the system delay time CL) by the logic level of the preamble signal DQ_PREAMBLE In response to the output of the AND gate that performs the operation, the third latch 198 activates the data transfer signal DOFFB.

Thereafter, the output terminal N2 of the second flip-flop 392 transitions to a logic high level at a time point CL-2 that is two cycles earlier than the cas delay time CL. At this time, the AND gate 395 at the time inverted by the first inverter 399_1 of the divided clock WCK / 2 (that is, the falling edge of the divided clock WCK / 2) causes the AND gate 395 to generate a first control pulse POUT_CL15P. Activate. At this time, the first control pulse POUT_CL15P has an activation period for the period of the data clock WCK.

After the output terminal N2 of the second flip-flop 392 transitions to a logic high level, the first latch 396 generates a second control pulse POUT_CL15 in response to the falling edge of the divided clock WCK / 2. do. On the other hand, the second latch 397, which receives the output of the second inverter 399_2 inverting the output terminal N2 of the second flip-flop 392, corresponds to the falling edge of the divided clock WCK / 2. The inverted signal POUT_CL15B of the control pulse POUT_CL15 is generated. Here, the inverted signal POUT_CL15B of the second control pulse POUT_CL15 and the second control pulse POUT_CL15 may operate in response to the falling edge of the divided clock WCK / 2. Because of this, it may have an activation period of 1tCK (one cycle of the system clock).

In addition to activating the second control pulse POUT_CL15, the data transfer signal DOFFB is also generated by the third latch 398 that operates in response to the falling edge of the divided clock WCK / 2. However, the third latch 398 is four times larger than the second control pulse POUT_CL15 by receiving the outputs of the AND gate 301 and the outputs of the second and third flip-flops 392 and 393 through the OR gate 394. The data transmission signal DOFFB having an activation period of may be output.

FIG. 4 is a waveform diagram illustrating the operation of the serialization controller 190 shown in FIG. 3. In particular, the signals output from the serialization controller 190 when the preamble signal DQ_PREAMBLE is deactivated will be described.

As shown in the drawing, the serialization control unit 190 generates a plurality of signals based on the divided clock WCK / 2 in response to the read data output signal RDOUTEN. First, when the read data output signal RDOUTEN is activated, the phase is delayed by the period of the divided clock WCK / 2 through the plurality of flip-flops 391, 392, and 393. After the output stages (N1, N2, N3) of 393), the first and second latches 196, 197 in the serialization control unit 390 correspond to the falling edge of the divided clock WCK / 2. 2 Generate the control pulses (POUT_CL15P, POUT_CL15, POUT_CL15B). In addition, the OR gate 194 performs an OR operation on the outputs of the second and third flip-flops 191 and 192, and outputs an output pulse having an double activation interval through the output terminal n4. The third latch 198 outputs a data transfer signal DOFFB in response to the falling edge of the divided clock WCK / 2. On the other hand, the preamble signal DQ_PREAMBLE is inactivated, so that the fourth and fifth latches 303 and 304 are deactivated to the logic high level regardless of the output of the negative gate 302. enb0101, enb1010).

FIG. 5 is a waveform diagram illustrating an operation of the serialization controller 190 shown in FIG. 3 when preamble is performed with the first pattern '0101'.

As illustrated, the serialization controller 190 receives not only the read data output signal RDOUTEN but also the preamble signal DQ_PREAMBLE and the first pattern signal PATTERN0101 that are activated at a logic high level. The first and second control pulses POUT_CL15P, POUT_CL15, and POUT_CL15B, which are activated corresponding to the read data output signal RDOUTEN, are generated in the same manner as in FIG. 4 described above.

On the other hand, if the preamble signal DQ_PREAMBLE and the first pattern signal PATTERN0101 are activated and input, the output signal of the first flip-flop 191 transitions to a logic high level in response to the read data output signal RDOUTEN. The output terminal n5 of the AND gate 302 also transitions to a logic high level. The fourth latch 303 receiving the logic high level outputs the first pattern enable signal enb0101 to the first and second phase shifters 110A and 110B in response to the first pattern signal PATTERN0101. In response to the activated first pattern enable signal enb0101, the first phase shifter 110A outputs the logic low level preamble data to the first multiplexer 120A and the second phase shifter 110B is logic. The high level preamble data is output to the second multiplexer 120B.

In addition, unlike the operation shown in FIG. 4 in which the preamble signal DQ_PREAMBLE is inactivated, the AND gate 301 is 3 cycles earlier than the cas delay time CL in response to the activation of the preamble signal DQ_PREAMBLE. The logic high level is output at the time point CL-3. In response to the output of the AND gate 301, the third latch 198 activates the data transfer signal DOFFB in response to the system clock. Of course, the data transfer signal DOFFB output from the third latch 198 corresponding to the output of the OR gate 194 is activated until a point CL-1 which is one cycle earlier than the cas delay time CL. State can be maintained. For reference, in FIG. 5, the active state is maintained without being deactivated due to the read data output signal RDOUTEN repeatedly activated.

FIG. 6 is a waveform diagram illustrating an operation of the serialization controller shown in FIG. 3 when preamble is performed in the second pattern '1010'.

As illustrated, the serialization controller 190 receives not only the read data output signal RDOUTEN but also the preamble signal DQ_PREAMBLE and the second pattern signal PATTERN1010 that are activated at a logic high level. The first and second control pulses POUT_CL15P, POUT_CL15, and POUT_CL15B, which are activated corresponding to the read data output signal RDOUTEN, are generated in the same manner as in FIG. 4 described above. The data transfer signal DOFFB, which is activated corresponding to the preamble signal DQ_PREAMBLE and the read data output signal RDOUTEN, is also generated in the same manner as in FIG. 5.

On the other hand, if the preamble signal DQ_PREAMBLE and the second pattern signal PATTERN1010 are activated and input, the output signal of the first flip-flop 191 transitions to a logic high level in response to the read data output signal RDOUTEN. The output terminal n5 of the AND gate 302 also transitions to a logic high level. The fifth latch 304 receiving the logic high level outputs the second pattern enable signal enb1010 to the first and second phase shifters 110A and 110B in response to the second pattern signal PATTERN1010. In response to the activated first pattern enable signal enb1010, the first phase shifter 110A outputs the logic high level preamble data to the first multiplexer 120A and the second phase shifter 110B is logic. The low level preamble data is output to the second multiplexer 120B.

FIG. 7 is a circuit diagram illustrating the first phase shifter 110A shown in FIG. 1.

As shown, the first phase shifter 110A includes a plurality of unit latches for phase shifting a plurality of data D4 and D6 respectively input in parallel, and each unit latch unit includes data input d Latches an output of the fifth inverter 112 for inverting the second inverter 112, a transfer gate 114 for transferring the output of the fifth inverter 112 in response to the first control pulse POUT_CL15P, and an output of the transfer gate 114. And an inverter latch 118 for inverting and outputting the same. In addition, the unit latch unit further includes a sixth inverter 116 for inverting the first control pulse POUT_CL15P to control the transfer gate 114.

The inverter latch 118 includes a MOS transistor for transmitting a logic high level in response to the first pattern enable signal enb0101, a transfer gate 114 when the second pattern enable signal enb1010 is inactive to a logic high level. When the output of the transistor is inverted and output and the second pattern enable signal enb1010 is activated at a logic low level, a negative logic gate for outputting preamble data having a logic high level, and an output of the negative logic gate are inverted and feedbacked. It includes a seventh inverter for. That is, the inverter latch 118 may activate the first pattern enable signal enb0101 or the second pattern enable signal activated at a logic low level before the first control pulse POUT_CL15P is activated and transmits the input data d. The preamble data of the logic low level or the logic high level is output in response to enb1010.

Although not shown, the second phase shifter 110B also includes components similar to the first phase shifter 110A. However, the second phase shifter 110B is a preamble output from the first phase shifter 110A because the locations where the first pattern enable signal enb0101 and the second pattern enable signal enb1010 are inputted are changed. The preamble data having a level complementary to the data may be output.

The operating method of a semiconductor memory device according to an embodiment of the present invention outputs eight data, which are transmitted from an internal unit cell and input in parallel, as four consecutive data in response to a read command, and four data according to an operation mode. A first serialization step for appending and outputting preamble data to each, a second serialization step for outputting two consecutive four pieces of data as two consecutive four pieces of data, and serializing two consecutive four pieces of data A third serialization step for outputting two pieces of data. Here, each data window of two consecutive data output in the first serialization step is four times each window of eight serialized data, and each data window of four consecutive data output in the second serialization step is serialized. It is twice the window of eight data.

In detail, the first serializing step includes outputting the preamble data according to an operation mode, and then shifting four data out of eight data phases by four times each data window of the eight serialized data. Multiplexing the other four data among the data and the four phase shifted data to output four consecutive two data, and latching four consecutive two data. Also, the second serialization step is for shifting the phase of two data out of four consecutive two data by twice the data window of the eight data serialized, and the other two out of four consecutive two data. Multiplexing data and phase shifted data to output the two consecutive four data, and latching an output of the multiplexer. The third serialization step is for shifting the phase of one of the two consecutive four data by each data window of the eight serialized data, and the data which is phase shifted with the other of the two consecutive four data. Multiplexing to output the eight serialized data serialized. In addition, during a test operation or a training operation, the third serialization step may include outputting externally any data that is not synchronized with the system clock.

As described above, the data output circuit in the semiconductor memory device according to an embodiment of the present invention is parallel to 1.5 tCK before the data output time (that is, the cas delay time CL after the read command is applied). By serializing a large number of data outputs, it is possible to output data corresponding to high frequency system clocks and data clocks. In particular, in the case of a graphics semiconductor memory device in which fast data input and output are considered important, the operation of a high frequency system clock becomes possible, thereby improving product competitiveness.

In addition, the present invention has been described using the data output circuit in the semiconductor memory device as an example, but may be utilized in communication and network equipment for serializing and outputting data input in parallel. In addition, the data output circuit may first pass preamble data similar to the actual one before outputting the data, thereby ensuring that valid data transmitted thereafter may be transmitted without distortion.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a block diagram illustrating a data output circuit of a semiconductor memory device according to an exemplary embodiment of the present invention.

FIG. 2 is a waveform diagram illustrating an operation of the semiconductor memory device shown in FIG. 1.

FIG. 3 is a block diagram illustrating the serialization controller shown in FIG. 1.

4 is a waveform diagram illustrating an operation of the serialization controller shown in FIG. 3 when the preamble signal is inactive.

FIG. 5 is a waveform diagram illustrating an operation of the serialization controller shown in FIG. 3 when performing preamble with a first pattern.

FIG. 6 is a waveform diagram illustrating an operation of the serialization controller shown in FIG. 3 when performing preamble with a second pattern.

FIG. 7 is a circuit diagram for describing the first phase shifter illustrated in FIG. 1.

Claims (25)

First serializing means for serializing eight data input in parallel and outputting four consecutive data, and outputting preamble data to each of the four consecutive data according to an operation mode; Second serialization means for receiving the output of the first serialization means and outputting two consecutive data; And And third serialization means for receiving the output of said second serialization means and outputting serialized data. The method of claim 1, And each data window of the continuous data output from the first serialization means is four times each window of the serialized data. The method of claim 2, The first serialization means A phase shifter for outputting the preamble data according to the operation mode and shifting four data of the eight data by four times each data window of the serialized data; A multiplexer for outputting the four consecutive data by multiplexing the output of the phase shifter with the other four data of the eight data; And And a latch unit for latching an output of the multiplexer. The method of claim 3, wherein The phase shifter includes a plurality of unit phase shifters corresponding to each of the four data, and each unit phase shifter A first inverter for inverting input data; A transmission gate for transmitting an output of the first inverter in response to a first control pulse; And And an inverter latch for outputting the preamble data and latching, inverting and outputting the output of the transfer gate according to the operation mode. The method of claim 4, wherein The inverter latch is A transistor for delivering preamble data at a logic high level in response to the first pattern enable signal; A negative logic gate configured to invert and output the outputs of the transfer gate and the transistor when the second pattern enable signal is inactive, and to output preamble data having a logic high level when the second pattern enable signal is activated; And And a second inverter for inverting and feeding back the output of the negative logic gate. The method of claim 3, wherein And a serialization controller for controlling the phase shifter, the multiplexer, and the latch unit in response to a read data output signal for activating data output in response to a read command, a preamble signal, and a data clock as a reference for the data output. Semiconductor memory device. The method of claim 6, The serialization control unit A first latch for generating a first control pulse for controlling the phase shifter in response to the read data output signal; A second latch for generating a second control pulse having an activation period twice as long as a period of the data clock for controlling the multiplexer; A third latch for outputting a data transfer signal having an activation period of one of four times and eight times a period of the data clock for controlling the latch unit in response to a preamble signal for determining the operation mode; A fourth latch for outputting a first pattern enable signal in response to a preamble signal and a first pattern signal before the first control pulse is activated; And And a fifth latch configured to output a second pattern enable signal in response to the preamble signal and the second pattern signal before the first control pulse is activated. The method of claim 1, And each data window of the continuous data output from the second serialization means is twice the window of the serialized data. The method of claim 8, The second serialization means A phase shifter for shifting two data out of the output of the first serialization means by twice the data window of the eight serialized data; A multiplexer for multiplexing the output of the phase shifter with two other data among the outputs of the first serialization means and outputting the two consecutive data; And And a latch unit for latching an output of the multiplexer. The method of claim 1, The third serialization means A phase shifter for shifting a phase of one of the two consecutive data by each data window of the serialized eight data; And And a multiplexer for outputting the serialized data by multiplexing the output of the phase shifter with another one of the two consecutive four data. The method of claim 10, And during the test operation or the training operation, the phase shifter in the third serialization means outputs arbitrary data which is not synchronized with a system clock and transmits the multiplexer to the outside. Receives eight data input in parallel and outputs four consecutive data having four times the data window of each of the eight serialized data, and preamble data is stored in each of the four consecutive data according to the operation mode. In addition, a first serialization unit for outputting; A second serialization unit receiving the output of the first serialization unit and outputting two consecutive four data having a data window twice as large as each window of the eight serialized data; And And a third serializer for receiving the output of the second serializer and outputting the serialized data. The method of claim 12, The first serialization unit A phase shifter for outputting the preamble data according to the operation mode and shifting four data out of the eight data by four times each data window of the serialized data; And And a multiplexer for outputting the four consecutive data by multiplexing the output of the phase shifter with the other four data among the eight data. The method of claim 12, Each of the second to third serialization means A phase shifter for shifting a phase by a window of data to output half of the input data; And And a multiplexer for generating the data to be output by multiplexing the other half of the input data and the output of the phase shifter. The method according to claim 13 or 14, Each of the first and second serialization means further comprises a latch portion for latching and delivering the output of the multiplexer. The method of claim 12, And a serialization controller for controlling the first serializer in response to a data enable signal for activating data transfer and a data clock as a reference for data output. The method of claim 16, The serialization control unit A first latch for generating a first control pulse having an activation period corresponding to a period of the data clock for controlling a phase shifter in the first serializer in response to the data enable signal; A second latch for generating a pulse having an activation period twice as long as a period of the data clock for controlling the multiplexer in the first serializer; A third latch for outputting a pulse having an activation interval of four times the period of the data clock for controlling the latch unit in the first serialization unit; A fourth latch for controlling the phase shifter in response to the preamble signal and the first pattern signal before the first control pulse is activated; And And a fifth latch for controlling the phase shifter in response to the preamble signal and the second pattern signal before the first control pulse is activated. The method of claim 13, The third serializer outputs any data that is not synchronized with the system clock to the outside during a test operation or a training operation. First serialization for outputting eight data transmitted from an internal unit cell in parallel in response to a read command and four consecutive data and adding preamble data to each of the four consecutive data according to an operation mode. step; A second serialization step for outputting the four consecutive data as two consecutive data; And And a third serialization step for outputting the two consecutive data as serialized data. The method of claim 19, And each data window of the data output in the first serialization step is four times each window of the serialized data. The method of claim 19, The first serialization step is Outputting the preamble data according to the operation mode and shifting four of the eight data phases by four times each data window of the eight serialized data; Multiplexing the other four data among the eight data and the four phase shifted data to output the four consecutive data; And And latching the four consecutive data. The method of claim 19, Wherein each data window of the data output in the second serialization step is twice the window of the serialized data. The method of claim 22, The second serialization step is Phase shifting two of the four consecutive data phases by twice the respective data window of the serialized data; Multiplexing the other two data and the phase shifted data among the four consecutive data to output the two consecutive data; And And latching the two consecutive data. The method of claim 19, The third serialization step is Shifting a phase of one of the two consecutive data by each data window of the serialized data; And Outputting the serialized data by multiplexing the phase shifted data with another one of the two consecutive data. The method of claim 19, In a test operation or a training operation, the third serialization step includes outputting externally any data that is not synchronized with the system clock.

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