KR100924924B1 - Gate driver and motor driving device using same - Google Patents

Abstract

The present invention provides a gate driver for minimizing the production cost of a motor driving device and an electronic device by implementing a gate driver of a motor driving device for driving a motor mounted in an electronic device as a simple circuit element without using an expensive IC chip. It relates to a motor driving device of the robot cleaner using the same.

The present invention provides a position detection unit for outputting the first to third position signals according to the position of the rotor of the motor, signal generation means for generating a PWM signal to determine the energization time applied to the three-phase coil of the motor according to the control voltage; By combining the PWM signal output from the signal generating means and the position signal of the rotor, the first to third of the application timing is different from each other to selectively drive the first to third upper drive transistors of the first to third inverters; A logic controller for generating first to third gate driving signals consisting of PWM signals and first to third gate signals for selectively driving the lower driving transistors, and first to third according to the first to third PWM signals And first to third gate drivers for performing pre-amplification for driving the first to third upper driving transistors of the inverter.

Motor Drive, Inverter, Power FET, Gate Driver, 3-Phase Drive

Description

GATE DRIVER AND MOTOR DRIVING DEVICE USING THE SAME

The present invention relates to a gate driver and a motor driving device using the same. More specifically, when driving a three-phase BLDC motor using an inverter, the upper channel of the inverter is driven through the gate driver, and the lower channel is The circuit structure can be simplified by the direct control from the logic controller, and the gate driver can drive the upper channel of the inverter by using simple circuit elements, thereby greatly reducing the manufacturing cost, and using the same. It relates to a motor drive device.

In recent years, in order to increase energy efficiency, home appliances (air conditioners, washing machines, refrigerators, etc.) are increasingly using three-phase brushless DC motors controlled by inverters. Brushless DC motors (BLDC motors), also known as commutatorless motors, are used in electronic circuits using power switching semiconductor devices such as transistors, MOSFETs, and IGBTs, instead of brushes and commutators, which are usually important parts of DC motors. It is a motor that generates torque by switching the current flowing through the stator winding by switching.

Therefore, the brushless DC motor has the characteristics of current-to-torque and speed-to-voltage similar to the DC motor in the structure of the synchronous motor, and because of its high efficiency and high power density, the field of application is expanding from home appliances to industrial equipment. It is a trend.

Three-phase brushless DC motors are easier to control torque than single-phase, high efficiency and advantageous in terms of noise.

This brushless DC motor is a stator and is disposed opposite the permanent magnet as the stator so that the three coils electrically have a phase difference of 120 degrees, and the core and permanent magnetized accordingly when selectively energizing the stator coils of each phase through a switching element. The rotor rotates by the magnetic force acting on the magnetic poles of the magnets. Therefore, in order to control the driving of the brushless DC motor, it is necessary to detect the relative position between the magnetic pole of the rotor and the core of the stator phase. For this purpose, a position detection sensor using a Hall device is used and the Hall element is detected. Appropriate voltage is applied to the stator windings through the inverter by the location information.

As the motor driving apparatus used to drive the brushless DC motor described above, a voltage inverter using six power switching elements such as a FET or an IGBT is used. Such an inverter is mainly controlled by a pulse width modulation (PWM) driving method. In general, the PWM driving method controls the average current by setting a constant voltage and giving a current in a pulse method. At this time, the method of controlling the ratio of the pulse width is PWM control.

As the PWM driving method, a triangular wave slice method and a peak current detection method are known. The triangular wave slice method uses an error amplifier that sends a coil current to the detection resistor and outputs the difference between the voltage generated in the detection resistor and the torque command voltage as a slice level. It is a method of determining the duration of energization. The peak current detection method does not use an error amplifier. When the voltage generated by the current detection resistor through which the coil current flows reaches the torque command voltage, the current supply to the coil is stopped and the regenerative current mode is set.

The conventional motor driving apparatus using six inverters is largely composed of an inverter including a microcomputer, a logic unit, three gate driver units, and six field effect transistors (FETs).

The six FET devices forming the output driver have the advantage that the driving circuit is simple when the high side uses the P channel element and the low side uses the N channel element, while the P channel is simple. The device has the disadvantage of being 1.5 to 2.5 times more expensive than the N-channel device. Therefore, a motor driving apparatus having an output driver using a low-cost N-channel element is also widely used in the upper FET. A motor driving apparatus using six N-channel FETs is described below by way of example.

1 is a schematic block diagram for explaining a motor driving device used for a robot cleaner, for example.

Referring to FIG. 1, the motor driving apparatus includes a microcomputer 10, a logic unit 20, three gate drivers 31, 32, and 33, and an inverter 40 including six N-channel FETs. Then, a driving voltage is applied to the motor 50.

The motor driving apparatus shown in FIG. 1 illustrates a case in which the motor 50 is driven in a three-phase driving method, and includes three high side FETs FET1 to FET3 and three lower FETs FET4 to FET6. ) Forms three pairs of inverters, and inverter outputs are generated from these three connection points to alternately apply three-phase driving voltages OUT1 to OUT3 to the three-phase driving coil of the motor 50.

The microcomputer 10 receives a variable voltage of 0 to 5 volts and outputs a PWM (pulse width modulation) signal to the logic unit 20.

The logic unit 20 combines the PWM signal output from the microcomputer 10 and the three detection signals HS in which the Hall element of the motor 50 detects the magnet polarity of the rotor, and the gate control signals HIN and LIN. ).

The three gate drivers 31 to 33 convert the gate control signals HIN and LIN output from the logic unit 20 into upper and lower driver outputs HO and LO capable of driving the upper and lower FETs, respectively. It is applied to the gate terminals of the upper FETs (FET1 to FET3).

The six FETs FET1 to FET6 are implemented as power devices, and each of the upper FETs FET1 to FET3 and the lower FETs FET4 to FET6 are three phases of the corresponding motor 50, for example, U, W, It is connected to the V-phase driving coil, respectively, and drives the motor 50 by applying three-phase driving voltages OUT1 to OUT3 to the motor 50 according to the upper and lower driver outputs HO and LO applied to the gate terminal. .

In this case, in the conventional motor driving apparatus illustrated in FIG. 1, the gate drivers 31 to 33 respectively include upper and lower drivers, respectively, and include upper FETs FET1 to FET3 and lower FETs FET4 to FET6. The upper and lower driver output signals HO and LO for driving are generated, and the floating channel is designed to perform a bootstrap operation.

Therefore, the gate drivers 31 to 33 basically serve to amplify the current required to drive the FET of the inverter 40, and when the PWM driving signal generated from the microcomputer 10 at the point on the motor is ON. The gate terminal of the high side FETs FET1 to FET3 of the inverter 40 has a positive (+) 15V greater than the connection point (ie, inverter output) between the upper FETs (FET1 to FET3) and the lower FETs (FET4 to FET6). It is maintained higher, and serves to control the gate terminal to be the same voltage, that is, 0V when the OFF signal is output from the microcomputer 10.

In order to play such a role, a conventionally developed gate driver uses an IC chip having two input / output pins each, or three gate drivers as one IC chip. For example, each gate driver 31-33 may be manufactured using an IC chip such as FAN 7382 (High-and Low-Side Gate Driver) manufactured by FAIRCHILD SEMICONDUCTOR or 'IR 2101' or 'IR 2106' manufactured by International Rectifier. However, since the gate driver IC chip itself is expensive, the production cost of the motor driving device becomes large.

In other words, three expensive gate driver chips are used to drive a three-phase drive type motor, and thus, as the production cost of the motor driving device increases, an electronic device adopting the same, in particular, a battery, such as a robot cleaner, is driven. The production cost of electric appliances used as a power source also rises, which lowers the competitiveness.

Therefore, the present invention was devised to solve the above problems, the object of which is to drive the upper channel of the inverter through the gate driver when driving the three-phase BLDC motor using the inverter, the lower channel is It is to provide a motor drive device that can be made simple circuit structure by direct control from the logic control unit.

Another object of the present invention is to provide a gate driver and a motor driving apparatus using the same, which can drive an upper channel of an inverter with a bootstrap function using simple circuit elements without using expensive IC chips.

In order to achieve the above object, the present invention includes an inverter having a top and bottom drive transistor connected to the tompole, and the top drive transistor of the motor drive device for supplying current to the motor from the connection point of the top and bottom drive transistors of the inverter CLAIMS 1. A gate driver for driving a transistor comprising: a first transistor for generating an output inverted in phase in accordance with a PWM (pulse width modulation) signal applied to an input side; First and second resistors connected in series to form a voltage divider circuit in the collector of the first transistor; A bootstrap diode that is connected to a cathode of the first resistor and is connected to a supply power supply (Vcc) to prevent current from flowing in the direction of the supply power and rectify the same; A bootstrap capacitor inserted between a cathode terminal of the bootstrap diode and a connection point of upper and lower driving transistors and charged by a power supply Vcc; A base is connected to the voltage divider output of the first resistor and the second resistor, and a supply power supply (Vcc) is connected to the emitter terminal through the bootstrap diode, and is connected to one end of a bootstrap capacitor to turn on the first transistor. A second transistor stepped up at a collector output side and a voltage charged at a bootstrap capacitor, the second transistor being dropped to a motor phase potential at the collector output side when the first transistor is turned off; Each base is commonly connected to the output of the second transistor, and a complementary emitter follower forms a complementary emitter follower so that the current amplified output from the commonly connected emitter is applied to the upper driving transistor of the inverter. When turned on, the output of the emitter follower is boosted to the motor phase potential that can drive the upper drive transistor and the voltage charged to the bootstrap capacitor, and when the second transistor is turned off the output of the emitter follower is It provides a gate driver of a motor drive device comprising a third and a fourth transistor that is dropped to a phase potential.

The bootstrap capacitor is charged by the supply power when the lower driving transistor is turned on and the upper driving transistor is turned off.

In addition, the third transistor has a base connected to the collector output of the second transistor, a collector connected to a supply power supply (Vcc) through the bootstrap diode, and a current amplified output from the emitter is applied to the upper driving transistor of the inverter. The fourth transistor is connected to the base of the collector output of the second transistor, the collector is connected to the connection point of the upper and lower driving transistors, the emitter is connected to the emitter of the third transistor and the current amplified from the emitter Preferably, the output is applied to the upper drive transistor of the inverter.

The motor is preferably driven in a three-phase drive method.

According to another feature of the present invention, the present invention includes first to third inverters having upper and lower drive transistors connected in series, respectively, from the connection point of each of the upper and lower drive transistors to each of the three-phase drive motors. A motor driving device for supplying current, comprising: a position detection unit for outputting first to third position signals according to a rotor position of the motor; Signal generating means for generating a PWM signal for determining the energization time applied to the three-phase coil of the motor according to the control voltage; A first application timing different from each other to selectively drive the first to third upper driving transistors of the first to third inverters based on the PWM signal and the first to third position signals output from the signal generating means; A logic controller configured to generate first to third gate driving signals including first to third PWM signals and first to third gate signals for selectively driving the lower driving transistors; Pre-amplification is performed to drive the first to third upper driving transistors of the first to third inverters according to the first to third PWM signals having different application timings respectively constituting the first to third gate driving signals. And a first to third gate driver, wherein the logic controller selects any one of the upper driving transistors of the first to third inverters according to the position signal, and conducts a predetermined period of time, while remaining the inverters. It provides a motor drive device characterized in that to control to conduct one of the lower drive transistor of the.

In the motor driving apparatus, the position detecting unit preferably includes first to third Hall elements for generating first to third position signals corresponding to the strength of the magnetic field of the rotor.

The first to third gate drivers may include a first transistor configured to generate an output inverted in phase according to a PWM signal applied to an input side, respectively; First and second resistors connected in series to form a voltage divider circuit in the collector of the first transistor; A bootstrap diode that is connected to a cathode of the first resistor and is connected to a supply power supply (Vcc) to prevent current from flowing in the supply power direction and to rectify the current; A bootstrap capacitor inserted between a cathode terminal of the bootstrap diode and a connection point of upper and lower driving transistors and charged by a power supply Vcc; A second transistor that is turned on when the first transistor is turned on, and the output is boosted to a voltage charged in the motor phase potential and the bootstrap capacitor, and is turned off when the first transistor is turned off to drop the output to the motor phase potential; Each base is commonly connected to the output of the second transistor, and a complementary emitter follower forms a complementary emitter follower so that the current amplified output from the commonly connected emitter is applied to the upper driving transistor of the inverter. When turned on, the output of the emitter follower is boosted to the motor phase potential capable of driving the upper drive transistor and the voltage charged to the bootstrap capacitor, and the output of the emitter follower is the motor phase change when the second transistor is turned off. And third and fourth transistors that drop down.

In this case, the second transistor has a base connected to the voltage divider output of the first resistor and the second resistor, and a supply power supply (Vcc) connected to the emitter terminal through the bootstrap diode, and connected to one end of a bootstrap capacitor. It is preferable to be.

The logic controller may include: first to third inverters for generating first to third inverted position signals in which the first to third position signals are inverted to have a 180 degree difference in phase; The combination of the PWM signal, the first to third position signals and the first to third inverted position signals, the application timing is different from each other to selectively drive the first to third upper drive transistors of the first to third inverters First to third AND gates for generating first to third gate driving signals including first to third PWM signals; The combination of the three pairs of position signals may include a fourth to sixth AND gate for generating a first to third gate signal for selectively driving the lower driving transistor.

The second AND signal, the third inverted position signal, and the PWM signal are input to the first AND gate, and the first PWM signal is generated at the output when the second position signal and the third inverted position signal are both at high level (H). The second AND gate is input with a third position signal, a first inverted position signal, and a PWM signal, and when the third position signal and the first inverted position signal are both at a high level (H), a second PWM signal at an output. The first AND signal, the second inverted position signal, and the PWM signal are input to the third AND gate, and when the first position signal and the second inverted position signal are both at the high level (H), A PWM signal is generated, and the fourth AND gate generates a first gate signal when both the input third position signal and the second inverted position signal are high level (H), and the fifth AND gate is input. The second gate when both the first position signal and the third inverted position signal are high level (H); Generates a call, the first AND gate 6 is the logic is configured to generate the third gate signal when the input signal and the second position the first reversing position signal are both high-level (H).

Therefore, when the gate voltage applied to one gate of the upper driving transistors of the first to third inverters is at the high level (H), the gate voltage applied to the gate of the lower driving transistor corresponding thereto is at the low level (L). Is set.

As described above, in the present invention, when the three-phase drive type BLDC motor is driven by using the inverter, the upper channel of the inverter is driven through the gate driver, and the lower channel is directly controlled from the logic controller. It can be done simply, and the gate driver can drive the upper channel of the inverter using simple circuit elements, which can greatly reduce the manufacturing cost.

Hereinafter, a gate driver and a motor driving apparatus using the same according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram illustrating a motor driving apparatus according to a preferred embodiment of the present invention.

In the motor driving apparatus of the present invention shown in FIG. 2, the microcomputer 100, the position detection unit 110, the logic control unit 200, three first to third gate drivers 301 to 303, and three first to third devices are illustrated. Three inverters 401-403 are provided.

First, the motor 500 driven by the motor driving apparatus of the present invention has a U-phase coil 501, a V-phase coil 502, and a W-phase coil 503 on the stator so that driving is performed in a three-phase driving method. ) BLDC motor with star (Y) connection.

The first to third inverters 401-403 are U phase, V phase, and W phase upper driving transistors Q1, Q3, and Q5, and U, V, and W phase lower driving transistors Q2, Q4, and Q6. Sources of the upper driving transistors Q1, Q3, and Q5 are U, V, and W phases so as to form an output circuit connected to the U phase, V phase, and W phase between the supply power supply V _DD and ground, respectively. The U-phase coil 501 and the V-phase coil 502 of the motor 500 are connected to the drains of the lower driving transistors Q2, Q4, and Q6, respectively, from the respective connection points P _U , P _V , and P _W. And an output signal to the W-phase coil 503 is generated.

The driving transistors Q1 to Q6 are formed of n-type power MOS FETs that operate as switching elements, and coils 501 to 503 are turned off when the driving transistors are turned off between the drain and the source of the driving transistors Q1 to Q6. Diodes D1-D6 for freewheeling the counter electromotive force generated from the circuit are connected in the reverse direction.

The drive device of the BLDC motor flows current into each phase of the stator side coil of the three-phase BLDC motor 500, and the rotor of the motor 500 rotates by a magnetic field based on the current supplied from the drive device. In order to continuously rotate the rotor of the motor 500 in one direction, the magnetic field of the rotor using the three Hall elements HA, HB, HC is set to the position of the rotor (the strength of the magnetic field of the rotor). Switching elements, i.e., driving transistors, for detecting three signals which are formed by and having a phase difference of 120 ㅀ, and for changing the direction of current flowing in each phase of the coils 501 to 503 according to the detected position of the rotor. (Q1 ~ Q6) must be turned on and off sequentially.

To this end, the position detection unit 110 includes three Hall ICs (HA, HB, HC), and three Hall ICs (HA, HB, HC) of the magnetic field of the rotor. First to third position signals SA, SB, and SC corresponding to the intensity are generated and output to the logic controller 200. In this case, pull-up resistors R6-R8 are connected between the output terminals of the Hall ICs HA, HB and HC and the supply power supply Vcc to remove noise.

The microcomputer (CPU) 100 is a motor 500 for controlling the supply of the drive current to the motor 500 in a pulse width modulation (PWM) manner when the motor driving device is a motor used in the vacuum suction device of the robot cleaner. ) Outputs a PWM signal that determines the energization time applied to the coils 501-503 according to a control voltage which is varied in a range of 0 to 3.3 or 5 volts supplied from the controller of various cleaner bodies to which the vacuum cleaner is applied. That is, a vacuum suction device such as a robot cleaner drives the motor at a constant speed so that vacuum suction is performed at an output of a corresponding intensity according to a user's selection of a control voltage proportional to a preset output intensity. The energization time is determined by the control voltage supplied from the circuit. Therefore, the microcomputer 100 is used as a signal generating means for generating a PWM signal.

However, the PWM signal of the motor drive device has a current carrying time applied to the coil according to the torque control voltage from the main body and the voltage corresponding to the current flowing through the coil determined by the triangular wave slice method or the peak current detection method, which is a kind of PWM method. Can be determined. If the peak current detection method is performed using the PWM method, the peak value of the current flowing through the coils 501-503 is supplied to the input of the microcomputer 100.

The logic controller 200 includes three inverters 111-113, and the first to third inverted position signals / SA, which are inverted to have a 180-degree difference in phase through the inverters 111-113. / SB, / SC, and combines the PWM signal output from the microcomputer 100 and the three pairs of position signals SA, / SA, SB, / SB, SC, / SC, to 1st to 1st. The upper channel (ie, the upper driving transistors Q1, Q3, and Q5) of the third inverters 401-403 are driven through the first to third gate drivers 301-303, respectively, and the lower channel (that is, the lower side). The driving transistors Q2, Q4, and Q6 generate three gate driving signals AH-CH and three gate signals GAL-GCL for direct control.

Each of the three first to third gate drivers 301 to 303 may be configured by first to third gate driving signals AH-CH, that is, first to third PWM signals supplied from the logic controller 200. The gate signals GAH-GCH necessary for driving the U-phase, V-phase, and W-phase upper driving transistors Q1, Q3, and Q5 forming the upper channel of the three inverters 401-403 are generated. This will be described later.

The logic controller 200 may convert the first to third inverted position signals / SA, / SB and / SC which are inverted to be 180 degrees out of phase with the first to third position signals SA, SB and SC. The three gate driving signals AH- are generated by combining the three inverters 111-113 generated, the PWM signal and three pairs of position signals SA, / SA, SB, / SB, SC, and / SC. In order to generate CH, the first to third AND gates AND1 to AND3 and the fourth to sixth AND gates AND4-AND6 for generating three gate signals GAL-GCL are included.

Since the second position signal SB, the third inversion position signal / SC, and the PWM signal are applied to the third input terminal, the first AND gate AND1 receives the second position signal SB and the third inversion position signal. The first PWM signal is output and applied to the first gate driver 301 during the period when (/ SC) is all at the high level (H).

In addition, since the third position signal SC, the first inversion position signal / SA, and the PWM signal are applied to the third input terminal, the second AND gate AND2 is inverted from the third position signal SC and the first inversion. The second PWM signal is output and applied to the second gate driver 302 while the position signals / SA are all at the high level H.

In addition, since the first position signal SA, the second inverted position signal / SB, and the PWM signal are applied to the third input terminal AND3, the first position signal SA and the second inverted signal are applied to the third input gate AND3. The third PWM signal is output and applied to the third gate driver 303 while the position signals / SB are all at the high level H.

As a result, the gate driving signals AH-CH applied to the inputs of the first to third gate drivers 301 to 303 from the first to third AND gates AND1 to AND3 have different application timings. To a third PWM signal.

Further, the fourth AND gate AND4 is the first inverter 401 when both the third position signal SC and the second inverted position signal / SB input to the two input terminals are high level (H). The gate signal GAL is applied to the lower driving transistor Q2 of the second AND gate AND5, and the first position signal SA and the third inverted position signal / SC input to the second input terminal When all are at the high level H, the gate signal GBL is applied to the lower driving transistor Q4 of the second inverter 402, and the sixth AND gate AND6 is the second position signal input to the two input terminals. When both the SB and the first inverted position signal / SA are at the high level H, the gate signal GCL is applied to the lower driving transistor Q6 of the third inverter 403.

The second position signal SB and the third inverted position signal / SC input to the first AND gate AND1 are the third position signal SC and second input to the fourth AND gate AND4. There is a timing having a logic level opposite to that of the inversion position signal / SB, and the third position signal SC and the first inversion position signal / SA input to the second AND gate AND2 are There is a timing having a logic level opposite to the first position signal SA and the third inverted position signal / SC input to the fifth AND gate AND5, and inputs to the third AND gate AND3. The first position signal SA and the second inverted position signal / SB are opposite to the second position signal SB and the first inverted position signal / SA input to the sixth AND gate AND6. The timing with a logic level of is set to exist.

That is, when the gate signal GAH-GCH applied to one of the upper driving transistors Q1, Q3, and Q5 of the first to third inverters 401 to 403 is set to the high level H, it corresponds to this. The gate signals GAL-GCL applied to the gates of the lower driving transistors Q2, Q4, and Q6 are set to the low level (L).

Therefore, if the upper driving transistor Q1 of the first inverter 401 is turned on, the lower driving transistor Q2 corresponding to the upper driving transistor Q1 is turned off, and the upper driving transistor is turned on from the driving power source V _DD . Current flows from the connection point P _U to the coil 501 of the U phase of the motor 500 through the transistor Q1. The current flowing to the U-phase coil 501 flows to ground through the coils 502 and 503 of one of the lower driving transistors Q4 and Q6 of the second and third inverters 402 and 403.

As described above, in the motor driving apparatus of the present invention, the gate driving signal AH− obtained by combining the PWM signal and the three position signals SA, SB, and SC from the position detecting unit 110 in the logic control unit 200. CH is sequentially and selectively applied to the first to third gate drivers 301 to 303 to turn on one of the upper driving transistors Q1, Q3, and Q5, and the gate signal GAL-GCL is turned on to the lower driving transistor. By applying directly to one of the gates of Q2, Q4, Q6 to control the current flow path to the coil (501-503) of the three-phase drive motor 500 through the first to third inverters (401-403) Let the rotor continue to rotate in one direction.

In addition, the logic controller 200 may transmit one of the first to third inverters 401-403, for example, the upper driving transistor Q1 of the first inverter 401 to the position signal ( Selects according to SA, SB, and SC, conducts a predetermined period of time, and simultaneously conducts the lower drive transistors Q4 and Q6 of the second and third inverters 402 and 403, and the drive transistors For example, in the case of the lower driving transistor Q2 of the first inverter 401, the gate driving signal AH-CH is configured to conduct the upper driving transistors Q3 and Q5 of the remaining second and third inverters 402 and 403. And gate signals GAL-GCL may be applied to the first to third gate drivers 301 to 303 and the lower driving transistors Q2, Q4, and Q6, respectively.

In this case, speed and torque control of the motor 500 is performed by operating the gate drivers 301-303 and the first to third inverters 401-403 according to the PWM signal generated by the microcomputer 100.

In FIG. 2, the gate resistors R11, R13, R15, R17, R19, and R21 inserted between the outputs of the gate drivers 301-303 and the gates of the driving transistors Q1-Q6 are for current limiting, and the driving transistor ( The resistors R12, R14, R16, R18, T20, and R22 connected between the gate and the source of Q1-Q6) are high capacitance resistors and the FET malfunctions due to the charge charged in the parasitic capacitor formed between the gate and the source of the FET. To discharge the charge charged in the parasitic capacitor to prevent the. In this case, the resistors R12, R14, R16, R18, T20, and R22 may be omitted.

The first to third gate drivers 301 to 303 have the same circuit configuration, and each of the inverters 401 to 403 according to three gate driving signals AH-CH supplied from the logic controller 200. The gate signals GAH-GCH necessary for driving the U-phase, V-phase, and W-phase upper driving transistors Q1, Q3, and Q5 forming the upper channel are generated.

The connection points P _U , P _V , P _W between the source of the upper driving transistors Q1, Q3, Q5 and the drain of the lower driving transistors Q2, Q4, Q6 are turned on and turned on of the driving transistors Q1-Q6. According to the off, the voltage is changed between the operating power source V _DD and 0V.

Therefore, in order to turn on the upper driving transistors Q1, Q3 and Q5, when the driving transistors Q1, Q3 and Q5 are FET devices operating at 5V, the gate terminal of the upper driving transistors Q1, Q3 and Q5 is connected to the connection point. It is required to generate the gate signals GAH-GCH of the first to third gate drivers 301-303 so as to be + 5V than (P _U , P _V , P _W ) (that is, the phase voltage of the motor).

Hereinafter, a detailed circuit configuration and driving method of the gate driver will be described in detail with reference to FIG. 3.

3 is a circuit diagram of a gate driver according to the present invention.

Referring to FIG. 3, in the first gate driver 301 according to the present invention, the gate signal AH applied from the microcomputer 100 through the first AND gate AND1 of the logic controller 200, that is, the first PWM The signal is applied to the base terminal of the first transistor TR1 in which the emitter is grounded by the NPN type common emitter method through the third resistor R3 used as the base resistor, and the collector terminal of the first transistor TR1. The first resistor R1 and the second resistor R2 connected in series to form a voltage divider circuit are connected to the load.

A first capacitor C1 is connected in parallel at both ends of the first resistor R1, and a cathode of a bootstrap diode D10 is connected to the first resistor R1 and the first capacitor C1. The anode of the bootstrap diode D10 is supplied with a + 5V voltage through a fifth resistor R5 for limiting the current charged in the second capacitor C2 for bootstrap use described below. Vcc) is connected.

The connection point P3 whose output is obtained by the voltage dividing circuit of the first resistor R1 and the second resistor R2 is connected to the base terminal of the second transistor TR2 of the PNP type used in the common emitter CE method. The power supply Vcc is connected to the emitter terminal of the second transistor TR2 through the bootstrap diode D10 and the fifth resistor R5.

The collector terminals of the second transistor TR2 have third and fourth polarities that are different in polarity and have the same characteristics so as to have a function as a preamplifier required for driving the power driving transistor Q1 of the inverter 401 connected to the rear stage. Transistors TR3 and TR4 form a complementary emitter follower 310, respectively, and serve as current amplifiers.

To this end, the base terminals of the third and fourth transistors TR3 and TR4 are connected to the collector terminals of the second transistor TR2, and the collector power supply of the third transistor TR3 is supplied via a diode D10. Vcc) is connected, and the fourth resistor R4 is connected between the base and the collector of the fourth transistor TR4, and the output amplified from the emitter terminals of the third and fourth transistors TR3 and TR4 is It is applied to the upper driving transistor Q1 of the first inverter 401, and the collector terminal of the fourth transistor TR4 is the connection point P _U of the upper and lower driving transistors Q1 and Q2 of the first inverter 401. That is, the motor 500 is connected.

Accordingly, the third and fourth transistors TR3 and TR4 alternately conduct as the emitter follower 310 according to the polarity of the base input voltage. That is, when the input signal applied to the base is at the high level, the third transistor is turned on and the fourth transistor is turned off. When the input signal is at the low level, the third transistor is turned off and the fourth transistor is turned off. Is turned on.

On the other hand, the bootstrap between the cathode terminal of the bootstrap diode (D1) and the connection point (P _U ) of the upper and lower drive transistors (Q1, Q2) to rectify the current while preventing the flow of current in the direction of the power supply (Vcc) The second capacitor C2 which functions is inserted, and when the lower driving transistor Q2 is turned on and the upper driving transistor Q1 is turned off, the supply power Vcc is inserted into the second capacitor C2. The charge is charged by.

Hereinafter, referring to the operation of the gate driver 301, when the PWM signal output from the microcomputer 100 is ON, that is, a high (H) level, the PWM signal is applied to the base terminal of the first transistor TR1. The first transistor TR1 is turned on.

As the first transistor TR1 is turned on, the collector P2 of the first transistor TR1 is set to a low level, and as a result, a low level voltage is applied to the base terminal of the second transistor TR2. The second transistor TR2 is applied to turn on. Therefore, Vcc (+ 5V) is applied to the input terminals of the third and fourth transistors TR3 and TR4, that is, the connection point P1, higher than the motor phase voltage.

Accordingly, the third transistor TR3 is turned on and the fourth transistor TR4 is turned off so that the emitter follower 310 is charged to the second capacitor C2 which bootstraps with Vcc (+ 5V). Charged charge is discharged through the third transistor TR3 The current applied to the input terminal is amplified and input to the gate terminal of the upper driving transistor Q1 as the gate driving signal GAH. In this case, the gate terminal of the upper driving transistor Q1 is set to be + 5V higher than the motor phase voltage, that is, the connection point P _U.

As a result, the upper driving transistor Q1 is turned on, and current flows to the U-phase coil 501 of the motor 500 through the upper driving transistor Q1.

On the other hand, when the PWM signal output from the microcomputer 100 is OFF, that is, at the low (L) level, the first transistor TR1 is turned off in contrast to the above, so that the connection point P3, that is, the second transistor TR2, is turned off. The base terminal rises to a high (H) level voltage of (motor phase voltage + 5V), and as a result, the second transistor TR2 is turned off.

Accordingly, the connection point P1 drops to the motor phase voltage, so that a weak current flows through the resistor R4, and as a result, the fourth transistor TR4 is turned on to output the emitter follower 310, that is, the upper driving transistor The gate terminal of Q1) drops to the motor phase voltage.

As a result, the upper driving transistor Q1 is turned off so that no current flows to the motor 500 through the upper driving transistor Q1.

On the other hand, when the high (H) level signal is applied to the lower driving transistor Q2 from the logic controller 200 as the gate driving signal GAL and turned on, and the upper driving transistor Q1 is set to the turn-off state, the first driving transistor Q2 is turned on. Charge is charged to the second capacitor C2 by the power supply Vcc, and the bootstrap second capacitor C2 serves as another voltage source for supplying a + 5V voltage.

As described above, in the motor driving apparatus of the present invention, the first to third gate drivers having a simple circuit configuration only for the upper driving transistors Q1, Q3, and Q5 of the first to third inverters 401 to 403 ( 301-303), and the lower drive transistors Q2, Q4, and Q6 are directly controlled by the logic control unit 200, so that the circuit structure is simple and the three-phase drive using the inverter is made by using a low-cost device as a whole. The motor can be controlled in a manner.

As a result, a gate driver can be implemented without using an expensive IC chip.

In the above-described embodiment, a FET device operated when a 5V voltage is applied to a gate of a drive transistor of an inverter has been described as an example. Thus, a + 5V power supply is used as a supply power supply (Vcc). It is also possible to use the one operating at + 15V as the supply voltage (Vcc).

The motor driving device of the present invention disclosed in the above embodiment is designed to be suitable for driving a motor in a device using a battery power source, that is, a low voltage driving power source such as a robot cleaner or a vehicle, It can also be easily made by those skilled in the art.

Although the present invention has been described in detail only with respect to the described embodiments, it will be apparent to those skilled in the art that various modifications and changes are possible within the technical spirit of the present invention, and such modifications and modifications belong to the appended claims.

1 is a block diagram illustrating a motor driving apparatus of a general robot cleaner.

2 is a circuit diagram illustrating a motor drive device according to the present invention.

3 is a detailed circuit diagram of a gate driver in the motor driving apparatus according to the present invention shown in FIG.

Figure 4 is a waveform diagram of the main part of the motor drive device according to the present invention.

Explanation of symbols on the main parts of the drawings

100: microcomputer 110: position detection unit

111-113: Inverter 200: Logic Control Unit

301-303: first to third gate drivers

310: emitter follower 401-403: first to third inverters

500: motor 501-503: coil

AND1-AND6: AND gate C1, C2: capacitor

D1-D6, D10: Diode HA-HC: Hall IC

R1-R8, R11-R22: Resistance Q1-Q6: Drive transistor

TR1-TR4: Transistor

Claims (14)

A gate driver having an inverter having upper and lower drive transistors connected in series, the gate driver for driving an upper drive transistor of a motor drive device for supplying current to a motor from a connection point of the upper and lower drive transistors of the inverter, A first transistor generating a phase inverted output according to a PWM (pulse width modulation) signal applied to an input side; First and second resistors connected in series to form a voltage divider circuit in the collector of the first transistor; A bootstrap diode that is connected to a cathode of the first resistor and is connected to a supply power supply (Vcc) to prevent current from flowing in the supply power direction and to rectify the current; A bootstrap capacitor inserted between a cathode terminal of the bootstrap diode and a connection point of upper and lower driving transistors and charged by a power supply Vcc; A base is connected to the voltage divider output of the first resistor and the second resistor, and a supply power supply (Vcc) is connected to the emitter terminal through the bootstrap diode, and is connected to one end of a bootstrap capacitor to turn on the first transistor. A second transistor that is boosted to a motor phase potential at a collector output side and a voltage charged to a bootstrap capacitor, and is dropped to a motor phase potential at a collector output side when the first transistor is turned off; Each base is commonly connected to the output of the second transistor, and a complementary emitter follower forms a complementary emitter follower so that the current amplified output from the commonly connected emitter is applied to the upper driving transistor of the inverter. When turned on, the output of the emitter follower is boosted to the motor phase potential that can drive the upper drive transistor and the voltage charged to the bootstrap capacitor, and when the second transistor is turned off the output of the emitter follower is And a third and a fourth transistor dropping to a phase potential. The gate driver of claim 1, wherein the bootstrap capacitor is charged by the supply power when the lower driving transistor is turned on and the upper driving transistor is turned off. The method of claim 1, The third transistor has a base connected to a collector output of the second transistor, a collector connected to a supply power supply (Vcc) through the bootstrap diode, and a current amplified output from an emitter is applied to an upper driving transistor of an inverter. The fourth transistor has a base connected to the collector output of the second transistor, a collector connected to the connection point of the upper and lower driving transistors, and an emitter connected to the emitter of the third transistor so that the current amplified output from the emitter is The gate driver of the motor drive device, characterized in that applied to the upper drive transistor of the inverter. The gate driver of claim 1, wherein the motor is driven by a three-phase driving method. A motor driving apparatus comprising first to third inverters having upper and lower driving transistors connected in series, respectively, and supplying current to a three-phase driving motor from a connection point of each of the upper and lower driving transistors of the inverter, A position detector for outputting first to third position signals according to the position of the rotor of the motor; Signal generating means for generating a PWM signal for determining the energization time applied to the three-phase coil of the motor according to the control voltage; A first of different application timings to selectively drive the first to third upper driving transistors of the first to third inverters by combining the PWM signals output from the signal generating means and the first to third position signals; A logic controller configured to generate first to third gate driving signals including first to third PWM signals and first to third gate signals for selectively driving the lower driving transistors; Pre-amplification is performed to drive the first to third upper driving transistors of the first to third inverters according to the first to third PWM signals having different application timings respectively constituting the first to third gate driving signals. Including first to third gate drivers, The logic controller First to third inverters for generating first to third inverted position signals in which the first to third position signals are inverted to have a 180 degree difference in phase, the PWM signal and the first to third position signals and third A first to third PWM signal having different application timings to selectively drive the first to third upper driving transistors of the first to third inverters by combining the first to third inverted position signals; Fourth to sixth ANDs generating first to third gate signals for selectively driving the lower driving transistors by combining the first to third AND gates for generating a three gate driving signal and the three pairs of position signals. A motor drive device comprising a gate. 6. The motor driving apparatus of claim 5, wherein the position detection unit comprises first to third Hall ICs which generate first to third position signals corresponding to the strength of the magnetic field of the rotor. The method of claim 5, The first to third gate drivers are respectively A first transistor generating an output inverted in phase according to a PWM signal applied to an input side; First and second resistors connected in series to form a voltage divider circuit in the collector of the first transistor; A bootstrap diode that is connected to a cathode of the first resistor and is connected to a supply power supply (Vcc) to prevent current from flowing in the supply power direction and to rectify the current; A bootstrap capacitor inserted between a cathode terminal of the bootstrap diode and a connection point of upper and lower driving transistors and charged by a power supply Vcc; A second transistor that is turned on when the first transistor is turned on and the output is boosted to a voltage charged to the motor phase potential and the bootstrap capacitor; and when the first transistor is turned off, the second transistor turns off and the output drops to the motor phase potential Wow; Each base is commonly connected to the output of the second transistor, and a complementary emitter follower forms a complementary emitter follower so that the current amplified output from the commonly connected emitter is applied to the upper driving transistor of the inverter. When turned on, the output of the emitter follower is boosted to the motor phase potential that can drive the upper drive transistor and the voltage charged to the bootstrap capacitor, and when the second transistor is turned off the output of the emitter follower is And a third and a fourth transistor dropping to a phase potential. The method of claim 7, wherein the second transistor has a base connected to the voltage divider output of the first resistor and the second resistor and a supply power supply (Vcc) connected to the emitter terminal through the bootstrap diode, A motor drive device, characterized in that connected to one end. delete The method of claim 5, The second AND signal, the third inverted position signal, and the PWM signal are input to the first AND gate, and the first PWM signal is generated at the output when the second position signal and the third inverted position signal are both at high level (H). Become, A third position signal, a first inversion position signal, and a PWM signal are input to the second AND gate, and when the third position signal and the first inversion position signal are both at a high level, a second PWM signal is generated at the output. , The first AND signal, the second inverted position signal, and the PWM signal are input to the third AND gate, and when the first position signal and the second inverted position signal are both at high level, a third PWM signal is generated at the output. Become, The fourth AND gate generates a first gate signal when both the input third position signal and the second inverted position signal have a high level (H), The fifth AND gate generates a second gate signal when both the input first position signal and the third inverted position signal are high level (H), And the sixth AND gate generates a third gate signal when both the input second position signal and the first inverted position signal have a high level (H). 6. The logic controller of claim 5, wherein the logic controller selects any one of the upper driving transistors of the first to third inverters according to the position signal, and conducts a predetermined period of time, and conducts the lower driving transistors of the remaining inverters. Motor drive device characterized in that for controlling to. 6. The logic controller of claim 5, wherein the logic controller selects one of the upper driving transistors of the first to third inverters according to the position signal, and conducts a predetermined period of time, and at least one of the lower driving transistors of the other inverters. A motor drive device, characterized by controlling to conduct. 6. The logic controller of claim 5, wherein the logic controller selects any one of the lower driving transistors of the first to third inverters according to the position signal, conducts a predetermined period of time, and conducts the upper driving transistors of the remaining inverters. Motor drive device characterized in that for controlling to. The motor drive device according to any one of claims 5 to 8 and 10 to 13, wherein the motor is used in a vacuum generator.

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