KR100924493B1 - Manufacturing Method of Array Board for Integrated LCD - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching element of a drive circuit-integrated liquid crystal display device and a method for forming a CMOS element constituting the drive circuit.

The present invention employs n-type and p-type inverted steady polycrystalline thin film transistors as the switching element and the CMOS element, and briefly describes a method of manufacturing the same.

First mask: gate electrode formation

Second mask (diffraction exposure): Forming a polycrystalline silicon layer pattern, an ohmic contact layer (n + doping) and an LDD region (n-doping) of an n-type TFT constituted in a pixel and a driving circuit.

Third mask: shielding the pixel and the driving circuit and forming an ohmic contact layer on the P-type TFT of the driving circuit (p + doping, counter doping)

Fourth Mask: Transparent Pixel Electrode Formation

Fifth mask: simultaneously patterning the protective film and the nitride film;

Sixth mask: forming respective source and drain electrodes of the switching element and the CMOS element.

Since the mask process can be significantly reduced by the process described above, process cost and process time can be reduced, thereby improving the process yield.

Description

Method of fabricating an array substrate for Liquid Crystal Display Device with driving circuit}             

1 is a plan view schematically showing a general liquid crystal panel integrated with a driving circuit unit;

2A and 2B are cross-sectional views of a CMOS element constituting a switching element and a driving circuit constituted in a conventional pixel,

3A to 3H and 4A to 4H are cross-sectional views illustrating a method of manufacturing a switching device and a CMOS device according to a conventional process according to a conventional process sequence.

5A to 5I and FIGS. 6A to 6I are cross-sectional views illustrating a method of manufacturing a switching device and a CMOS device according to the present invention, in the order of the present invention.

<Description of Symbols for Main Parts of Drawings>

100 substrate 102 buffer layer

104: gate electrode 110: gate insulating film

140: protective film 142: silicon insulating film                 

150a: source electrode 150b: drain electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing a switching element and a CMOS element, each comprising a polycrystalline thin film transistor, in an integrated liquid crystal display device with a driving circuit.

In general, a liquid crystal display device injects a liquid crystal between an array substrate including a thin film transistor (TFT) and a color filter substrate, and displays an image by using a difference in refractive index of light due to the anisotropy of the liquid crystal. It is a display device.

Currently, an active matrix liquid crystal display (AM-LCD) in which the thin film transistor and the pixel electrode are arranged in a matrix manner has been attracting the most attention because of its excellent resolution and video performance. Hydrogenated amorphous silicon (a-Si: H) is mainly used because the low-temperature process is possible, so that an inexpensive insulating substrate can be used.

However, because hydrogenated amorphous silicon has disordered atomic arrangements, weak Si-Si bonds and dangling bonds exist, which are converted into a quasi-stable state when irradiated with light or applied with an electric field, and used as a thin film transistor device. It is difficult to use as a driving circuit due to poor stability and low electrical characteristics (low field effect mobility: 0.1 to 1.0 cm2 / V · s).

On the other hand, since polysilicon has a greater field effect mobility than amorphous silicon, a driving circuit can be made on a substrate. When the polysilicon is used to make a driving circuit directly on a substrate, driving IC costs can be reduced and mounting is simplified.

1 is a schematic diagram of an array substrate for a liquid crystal display device integrated with a general driving circuit unit.

As illustrated, the insulating substrate 10 may be largely defined as a display unit D1 and a non-display unit D2, and a plurality of pixels P are arranged in a matrix form on the display unit D1, and a switching element for each pixel. T and the pixel electrode 17 connected thereto are formed.

In addition, a gate line 12 extending along one side of the pixel P and a data line 14 perpendicular to the gate line 12 are formed.

The non-display part D2 includes the driving circuit parts 16 and 18, and the driving circuit parts 16 and 18 are located at one side of the substrate 10 to apply a signal to the gate wiring 12. And a data driving circuit portion 18 positioned on the other side of the substrate 10 that is not parallel thereto and applying a signal to the data line 14.

In addition, the gate and data driving circuit unit are connected to an external signal input terminal 20.

The gate and data driving circuit units 16 and 18 control an internal signal input through the external signal input terminal 20 to control the display to the pixel unit P through the gate and data lines 12 and 14, respectively. Apparatus for supplying signals and data signals.

Accordingly, the gate and data driver circuits 16 and 18 are constituted by thin film transistors having a complementary metal-oxide semiconductor (CMOS) structure which is an inverter to properly output an input signal.

The CMOS is a semiconductor technology used in a thin film transistor for driving circuits requiring high-speed signal processing. The CMOS uses extra electrons (n-type semiconductor) and negatively charged holes (p-type semiconductor) charged with negative electricity. It is used as a complementary method for forming a conductor and forming a current gate by effective electrical control of the two kinds of semiconductors.

2A and 2B are cross-sectional views illustrating the thin film transistor of the pixel portion thin film transistor and the driving circuit portion CMOS structure thin film transistor, respectively. (A: Cross-sectional view of a switching thin film transistor, and B and C are CMOSs in which n-type and p-type thin film transistors are combined. Section of the device.)

As shown in FIGS. 2A and 2B, a buffer layer 32 is formed on an insulating substrate 30, and an n-type thin film transistor is formed in the switching region A and the driving circuit region P of the substrate. And a CMOS element (a combination of an n-type thin film transistor and a p-type thin film transistor) are located.

The cross-sectional structure of each of the above-described thin film transistors will be described below.

As illustrated, the first active pattern 34, the second active pattern 36, and the second active pattern 38 are formed in respective regions of the buffer layer 32.                         

The first and third active patterns 34, 36, and 38 are formed by patterning a polycrystalline silicon layer, and each of the first and third active patterns 34, 36, and 38 is formed on both sides of the first active region V1 and the first active region V1. It may be defined as (V2).

A gate insulating film 40 is disposed on an entire surface of the substrate 30 including the first to third active patterns 34, 36, and 38, and the first to third active patterns 34 are disposed on the gate insulating film 40. The first, second, and third gate electrodes 42, 44, and 46 are respectively configured to correspond to the first active regions V1 of, 36, 38.

An interlayer insulating film 52 is formed on the entire surface of the substrate 30 on which the first to third gate electrodes 42, 44, and 46 are formed, and the interlayer insulating film 52 and the gate insulating film 40 below are etched. First source and drain electrodes 60a and 60b and second source and drain electrodes 62a in contact with each of the second active regions V2 of the first to third active patterns 34, 36, and 38 that are exposed. And 62b and third source and drain electrodes 64a and 64b.

In the above-described configuration, the second active regions V2 of the first and second active patterns 34 and 36 of the n-type polycrystalline thin film transistors configured in the switching region A and the driving circuit regions B and C are gated. The n-ion-doped LDD (Lightly Doped Drain) region F adjacent to the electrodes 42 and 44 and the non-LDD region are divided into n-ion-doped ohmic contact regions.

The LDD region F in the n-type thin film transistor is configured to disperse hot carriers. Since the doping concentration is low, the LDD region F is prevented from increasing the leakage current I _off due to low doping concentration. It prevents the loss of current.

In the above-described configuration, the n-type polycrystalline thin film transistor positioned in the switching region is configured to be in contact with the pixel electrode 70 and the insulating layer 66 mentioned above in FIG. 1.

The n-type thin film transistors in the switching region A and the n-type and p-type thin film transistors constituting the CMOS elements in the driving circuit regions B and C are constructed in the same process on a single substrate. Hereinafter, a switching thin film transistor according to the related art and a method of manufacturing a CMOS device will be described.

3A to 3H and 4A to 4H are cross-sectional views illustrating a process of manufacturing a switching thin film transistor and a CMOS device, respectively, according to a conventional process sequence.

First, FIGS. 3A and 4A illustrate a first mask process step. First, a driving circuit area B including a switching area S, an N area B, and a P area C on a substrate 30. , C) and a silicon insulating material (silicon nitride (SiN _X ), silicon oxide (SiO ₂ )) are deposited to form the buffer layer 32.

The first active pattern 34 and the second patterned by the first mask process on the switching region A and the driving circuit regions N regions B and P regions C on the buffer layer 32. The active pattern 36 and the third active pattern 38 are formed.

The first, second, and third active patterns 34, 36, and 38 are formed of polycrystalline silicon layers, and for convenience, each of the second active regions is disposed at both sides of the first active region V1 and the first active region V1. It is defined as (V2).

3B and 4B illustrate a second mask process step, wherein silicon nitride (SiN _X ) and silicon oxide (SiO) of the substrate 30 on which the first to third active patterns 34, 36, and 38 are formed. _A gate insulating film 40 is formed by depositing one selected from the group of inorganic insulating materials including ₂ ).

First, second and third gate electrodes 42 and 44 corresponding to the first active regions V1 defined in the first to third active patterns 34, 36 and 38 on the gate insulating layer 30, respectively. And 46), respectively.

Next, n− is formed in the second active regions V2 of the first to third active patterns 34, 36 and 38 by using the first to third gate electrodes 42, 44 and 46 as anti-doping films. The process of doping ions (the state which shows the doping amount of n-type ion very low) is performed.

3C and 4C are diagrams illustrating a third mask process step, in which part of N area B and all of P area C of the switching area A and the driving circuit areas B and C are shielded, respectively. First to second photoresist patterns 48a, 48b, and 48c are formed.

In this case, the first to second photoresist patterns 48a and 48b further include first and second gate electrodes 42 and 44 and predetermined regions F on both sides of the gate electrodes 42 and 44. To form.

The regions further shielded by the first and second photoresist patterns 48a and 48b, except for the gate electrodes 42 and 44, are referred to as LDD regions F, respectively.                         

N + doping is performed on the entire surface of the substrate 30 on which the first to third photoresist patterns 48a, 48b, and 48c are formed, so that the first active pattern 34 and the second active pattern 36 are not shielded. N + ions are doped into the second active region V2. This area is usually used as an ohmic contact area.

FIG. 3D is a view illustrating a fourth mask process step, after n + doping the first and second active patterns 34 and 36 of the switching area A and the N area B, and then switching area A. FIG. ) And the first and second photoresist sheet patterns 50a and 50b which completely shield the N region B are formed by the fourth mask process, respectively.

Next, p + ions are doped on the entire surface of the substrate 30 on which the first and second photoresist patterns 50a and 50b are formed to be formed in the P region C of the unshielded driving circuit region BC. A process of doping p + ions into the second active region V2 is performed.

In this process, the second active region V2 serves as an ohmic contact region.

3E and 4E illustrate a fifth mask process step, wherein silicon nitride (SiN _X ) and silicon oxide (SiN) are formed on the entire surface of the substrate 30 on which the first to third gate electrodes 42, 44, and 46 are formed. And depositing and patterning one selected from the group of inorganic insulating materials including Si0 ₂ ) to expose the second active region V2 of the first active pattern 34 formed in the switching region A, respectively. A third contact hole 54a and 54b and a second active region V2 of the second active pattern 36 formed in the N-type region B of the driving circuit regions B and C, respectively; Fifth and sixth contact holes 58a and 58b exposing fourth contact holes 56a and 56b and second active regions V2 of the third active pattern 38 formed in the P-type region C, respectively. To form.

3F and 4F illustrate a sixth mask process step, in which copper (Cu), tungsten (W), molybdenum (Mo), and chromium (Cr) are formed on the entire surface of the substrate 30 on which the interlayer insulating film 52 is formed. And depositing one selected from the group of conductive metals including titanium (Ti), tantalum (Ta), and the like, and patterning it with a sixth mask to contact the second active region V2 of the first active pattern 34, respectively. First source and drain electrodes 60a and 60b, second source and drain electrodes 62a and 62b in contact with the second active region V2 of the second active pattern 36, and the third active, respectively. The pattern 38 forms third source and drain electrodes 64a and 64b in contact with the second active region V2, respectively.

In the above-described configuration, the first source and drain electrodes 60a and 60b and the second source and drain electrodes 62a, which are formed in the N region A of the switching region A and the driving circuit regions B and C, 62b) is constructed so as not to contact each LDD region F. As shown in FIG.

Through the above-described process, a CMOS device including an n-type polycrystalline thin film transistor in the switching region A and an n-type and p-type thin film transistor in the circuit driving regions B and C may be configured.

Hereinafter, the process will be described for forming a pixel electrode in contact with the thin film transistor of the switching region in the array substrate including the thin film transistor described above.

3G and 4G illustrate a seventh mask process step, wherein the first source and drain electrodes 60a and 60b, the second source and drain electrodes 62a and 62b, and the third source and drain electrode 46a are illustrated. The protective film 66 is formed by coating one selected from the group of organic insulating materials including benzocyclobutene (BCB) and acrylic resin (resin) on the entire surface of the substrate 30 having 64b).

Subsequently, the passivation layer 66 is patterned to form a drain contact hole 68 exposing the drain electrode 60b of the switching region A. FIG.

3H and 4H illustrate an eighth mask process step, which includes indium tin oxide (ITO) and indium zinc oxide (IZO) on the entire surface of the substrate 30 on which the passivation layer 66 is formed. A selected one of the transparent conductive metal groups is deposited and patterned to form a transparent pixel electrode 70 in contact with the exposed drain electrode 60b.

Through the above-described process, a conventional array of driving circuit integrated liquid crystal display devices can be manufactured. (For convenience, the gate wiring and the data wiring portion formed simultaneously with the gate electrode and the source and drain electrodes of the switching region are omitted. .)

In the above-described manufacturing process of the liquid crystal display array substrate with integrated driving circuit, a total of eight mask processes are performed. Since the mask process includes a photo resist coating, an exposure, and a development, as the mask process is added, manufacturing cost and processing time increase, and thus, the production yield decreases, and the number of masks As it increases, there is a problem in that the probability of generating a defect in the thin film transistor element increases.

In order to solve the above problems, in the present invention, a polycrystalline thin film transistor formed in the switching region and the driving circuit region is formed in an invertedb staggered type, and a counter doping is performed to perform a mask process. It is aimed to improve process yield by significantly reducing.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device including a driving circuit, the method comprising: defining a substrate as a pixel portion, a switching portion in the pixel portion, and a driving circuit portion around the pixel portion;

A first mask process step of forming a first gate electrode in the switching portion of the substrate, and a second gate electrode and a third gate electrode in the driving circuit portion; First, second and third active patterns made of multi-rigid silicon are formed on the first to third gate electrodes with a first insulating film interposed therebetween, and the first active pattern and the second active pattern are formed under the gate electrode. Forming a portion that does not correspond to the n-ion doped region and the n + ion doped region; A third mask process step of forming a portion of the third active pattern that does not correspond to the gate electrode below the p + ion doped region; A fourth mask process step of forming a transparent pixel electrode in the pixel portion adjacent to the first active pattern; A second insulating film is formed on the entire surface of the substrate including the pixel electrode and the first to third active patterns, and then patterned to form one side and the other side (n + ion doped region) of a portion of the pixel electrode and the first active pattern adjacent thereto. ) And second and second contact holes exposing), second and third contact holes exposing one side and the other side (n + ion doped region) of the second active pattern, and one side and the other side of the third active pattern, respectively. a fifth mask process step of forming fourth and fifth contact holes exposing (p + ion doping), respectively;

A first source electrode simultaneously contacting one side of the exposed first active pattern and a pixel electrode adjacent thereto, a second drain electrode contacting the other side of the first active pattern, the second active pattern and a third active pattern And a sixth mask process step of forming second source and drain electrodes in contact with one side and the other side of the third source electrode, and a third source and drain electrode, respectively.

The second mask process may include: stacking a first insulating layer, a polycrystalline silicon layer, and a photoresist layer on an entire surface of the substrate on which the first to third gate electrodes are formed; Positioning a mask on a spaced upper portion of the photoresist layer, the portion corresponding to the gate electrode being a blocking portion, both sides of the blocking portion being semi-transmissive portions, and other regions being transparent portions; A developing process is performed in succession with an exposure process for irradiating light to the upper portion of the mask, and the thickness of each of the gate electrodes, the partial regions on both sides adjacent thereto, and the other regions on the first to third gate electrodes. Forming a first, second, and third photoresist pattern in which T1 and T2 have a relationship of T1> T2; Patterning the polycrystalline silicon layer exposed between the first to third photoresist patterns to form first, second, and third active patterns on the first, second, and third gate electrodes; Etching the first, second, and third photoresist patterns, removing a portion having a thickness of T2, and then doping n + ions to the exposed first, second, and third active patterns to form an ohmic contact region. Wow; The process of etching the etched first, second, and third photoresist patterns is performed once again, exposing a portion of the first, second, and third active patterns that are not doped with n +, wherein the first, second, and third photoresist patterns are exposed. Forming first, second and third photoresist patterns of substantially the same size as the second and third gate electrodes; And forming an LDD region by doping n-ions into a portion of the first, second, and third active patterns that are not doped with the n + ions.

The third mask process may include forming a photoresist pattern on the entire surface of the first, second, third, and active patterns, and patterning the photoresist with a third mask to completely cover the first and second active patterns, and to cover the third and third active patterns. Forming a photoresist pattern covering only a portion corresponding to the gate electrode; And doping p + ions in the exposed third active pattern to form an ohmic contact region.

The method may further include forming a buffer layer on the substrate before forming the first, second, and third gate electrodes.

Hereinafter, a thin film transistor of a driving circuit-integrated liquid crystal display device according to an exemplary embodiment of the present invention will be described with reference to the drawings.

Example

5A to 5I and FIGS. 6A to 6I are cross-sectional views illustrating a method of manufacturing a switching thin film transistor and a CMOS device constituting an array substrate for a liquid crystal display device having an integrated driving circuit, according to a process sequence of the present invention.                     

5A and 6A illustrate a first mask process step, in which a switching region S is defined in a region corresponding to a display portion of the insulating substrate 100, and a driving circuit is formed on one side of the substrate 100 corresponding to the non-display portion. The furnace areas (N area (B), P area (C)) are defined.

Next, a silicon insulating material (silicon nitride (SiN _x ) or silicon oxide (SiO ₂ )) is deposited on the entire surface of the substrate 100 to form a buffer layer 102.

First, second and third gate electrodes 104, 106 and 108 are formed on the N and P-type regions of the switching region A and the driving circuit regions B and C, respectively.

The gate insulating layer 110 is formed by depositing one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) or silicon oxide (SiO ₂ ) on the entire surface of the substrate 100 on which the first to third gate electrodes 104, 106 and 108 are formed. ) And polycrystalline silicon (a-Si: H) 112 are laminated.

The polycrystalline silicon layer 112 is formed by depositing amorphous silicon to form an amorphous preceding film (not shown), and then proceeds with dehydration as necessary.

Subsequently, high temperature or low temperature heat is applied to the amorphous preceding film (not shown) to form polycrystalline silicon.

Next, a photoresist (having a positive characteristic), hereinafter referred to as " PR " is applied to the polycrystalline silicon layer 112 to form a PR layer 114.

Next, a mask M including the transmissive part E1, the transflective part E2, and the blocking part E3 is positioned on the upper part spaced apart from the substrate 100 on which the PR layer 114 is formed.                     

In this case, the blocking portion E3 corresponds to the upper portions of the gate electrodes 104, 106, and 108, and the transflective portion E2 is disposed on both sides of the blocking portion E3.

Light is irradiated to the upper portion of the mask M to expose and develop a lower PR layer 114.

Hereinafter, the process of FIGS. 5B-5D and 6B-6D demonstrated a 2nd mask process.

5B and 6B, corresponding to the transmissive portion E1 and the transflective portion E2 of the developed PR layer, the switching regions A and the driving circuit regions B and C are respectively provided. The first PR pattern 116a, the second PR pattern 116b, and the third PR pattern 116c are configured.

In this case, the first to third PR patterns 116a, 116b, and 116c may have a thickness G1 corresponding to the gate electrodes 104, 106, and 108 and a thickness T1 of portions corresponding to both sides G2 of the gate electrodes 104, 106, and 108. T2) is different.

That is, the portion formed in the relationship of T1> T2, and the portion corresponding to the thickness T2 corresponds to the transflective portion of the mask (FIGS. 5A and 6A), and is partially exposed and developed compared to the transmissive portion, thereby obtaining this result.

Next, a process of removing the lower polycrystalline silicon layer 114 exposed between the first to third PR patterns 116a, 116b and 116c is performed.

In this way, as shown in FIGS. 5C and 6C, the first active pattern 118, the second active pattern 120, and the third active pattern are respectively formed in the switching region A and the driving circuit regions B and C, respectively. The pattern 130 is formed.                     

Next, an ashing process is performed to etch only part of the first to third PR patterns 116a, 116b, and 116c.

In this way, as shown in FIGS. 5D and 6D, all PRs of portions corresponding to both sides G2 of the gate electrodes 104, 106, and 108 are removed, and are etched into portions corresponding to the gate electrodes 104, 106, and 108. The remaining first PR pattern 124, the second PR pattern 126, and the third PR pattern 128 are formed.

Subsequently, n + ions are doped into the surfaces of the first active pattern 124, the second active pattern 126, and the third active pattern 128 exposed between the first to third PR patterns 124, 126, and 128.

Next, an ashing process of removing a part of the first to third PR patterns 124, 126, and 128 is performed.

In this case, as illustrated in FIGS. 5E and 6E, the first PRs etched corresponding to the first to third gate electrodes 104, 106, and 108 positioned in the switching region A and the driving circuit regions B and C may be etched. The pattern 130, the second PR pattern 132, and the third PR pattern 134 are formed.

As a result, there is a region G3 where ion doping does not proceed between the PR pattern and the region previously doped with n +.

Next, a process of doping n-ions (doping amount of ions compared to n + ions) on the entire surface of the substrate 100 on which the first to third PR patterns 130, 132 and 134 are etched is performed.

Through the above-described process, n-ions doped on both sides of the gate electrodes 104, 106 and 108 in the N region B and the P region C of the switching region A and the driving circuit regions B and C, respectively. And a region doped with n + ions are formed.

In general, the region G2 doped with n + ions is referred to as an ohmic contact region, and the region G3 doped with n− ions is referred to as an LDD region.

In this case, unlike the switching region A and the N-type region B, the P region C needs to be composed of a p-type thin film transistor, so that n-doped region G3 and n + -doped region G2 It is necessary to form the two regions G2 and G3 as ohmic contact regions doped with p + ions by simultaneously counter-doping the p + ions.

In other words, by doping a larger amount of p + ions compared to the doped n + ions so that the p + ions predominate.

To this end, the process shown in FIGS. 5F and 6F is performed.

5F and 6F illustrate a third mask process step, in which a photo-resist is applied to the entire surface of the substrate 100 and then patterned in a third mask process to form the switching area A and the driving circuit area ( The PR pattern 136 which completely shields the N area B of B and C is formed.

At this time, only the P region C is not shielded, and a process of doping p + ions is performed on the substrate in this state.

In this manner, p + ions are formed in the region H exposed to the outside of the third PR pattern 134 remaining on the third gate electrode 108 among the third active patterns 122 formed in the P region C. Is doped.                     

The region H doped with p + ions becomes an ohmic contact region.

Subsequently, all of the PR patterns 136, 136, and 134 formed in the switching area A and the driving circuit areas B and C are removed.

5G and 6G illustrate a fourth mask process step. When the process as described above is completed, the first active pattern 118 formed in the switching area A and the driving circuit areas B and C may be formed. Only the second active pattern 120 and the third active pattern 122 remain.

For convenience, the regions in which the ions are not doped in the first to third active patterns 118, 120, and 122 are referred to as the first active region V1, and the regions in which the ions are doped are referred to as second active regions V2.

In this case, the second active regions V2 of the first active pattern 118 and the second active pattern 120 each include an LDD region G3.

Next, one selected from the group of transparent conductive metals including indium tin oxide (ITO) or indium zinc oxide (IZO) on the entire surface of the substrate 100 having the first to third active patterns 118, 120, and 122 formed thereon. Is deposited and patterned in a third mask process to form a pixel electrode 138 in proximity to the switching region A. (The pixel electrode is configured in the display region.)

5H and 6H illustrate a fifth mask process step, wherein a benzocyclobutene (BCB) and an acrylic resin are formed on the entire surface of the substrate 100 on which the first to third active patterns 118, 120, and 122 are formed. The first passivation layer 140 is formed by depositing one selected from the group of organic insulating materials including the resin, and the silicon insulating layer 142 is formed on the first passivation layer 140.

The first passivation layer 140 and the silicon insulating layer 142 are patterned by a fifth mask process, so that the first to third active patterns 118, 120, and 122 disposed in the switching region A and the driving circuit regions B and C are formed. First and second contact holes 144a and 144b and second and second contact holes 146a and 146b and fourth and fifth contact holes 148a and 148b exposing both side active regions V2, respectively. To form.

In this case, one of the contact holes formed in the switching area A, which is close to the pixel electrode 138, is formed to simultaneously expose the pixel electrode 138.

5I and 6I illustrate a sixth mask process step and include chromium (Cr), tungsten (W), and molybdenum (Mo) on the entire surface of the substrate 100 on which the passivation layer 140 and the silicon insulating layer 142 are formed. N, B and P of the switching region A and the driving circuit regions B and C by depositing and patterning one selected from a group of conductive metals including titanium, titanium, tantalum, and the like. First source and drain electrodes 150a and 150b and second source and drain electrodes 152a in contact with the exposed second active regions V2 of the first to third active patterns 108, 110 and 112 positioned in the region C. And 152b and third source and drain electrodes 154a and 154b.

Through the above-described process, an n-type polycrystalline thin film transistor may be formed in the switching region, and a CMOS device combining an n-type thin film transistor and a p-type thin film transistor may be formed in the driving circuit region.

In addition, the N-type thin film transistor of the switching region A is formed such that one electrode contacts the pixel electrode 138 simultaneously when the source and drain electrodes 150a and 150b are formed.

Through the above-described process, a drive circuit integrated array substrate including a polycrystalline switching thin film transistor and a polycrystalline CMOS device may be manufactured.

The above-described feature of the present invention is to use a diffraction mask in the second mask process step and to perform counter-doping without a mask process to manufacture the driving circuit-integrated liquid crystal display device in a six-mask process.

Therefore, the drive circuit-integrated liquid crystal display device array substrate according to the present invention, as mentioned above, uses a diffraction mask in the second mask process step and performs a counter doping that does not require a mask process. Since an integrated liquid crystal display device can be manufactured, cost and processing time can be significantly reduced, thereby improving process yield.

Claims (7)

In the method of manufacturing an array substrate for a drive circuit-integrated liquid crystal display device comprising a drive circuit portion CMOS (complementary metal-oxide semiconductor) and a pixel switching element, Forming a first gate electrode, a second gate electrode, and a third gate electrode in the switching unit of the substrate divided into a pixel unit, a switching unit in the pixel unit, and a driving circuit unit around the pixel unit; A first mask process step;  Forming first, second, and third active patterns each having a width greater than that of the first to third gate electrodes and having a first insulating layer interposed therebetween, the first and second gate electrodes being made of multi-rigid silicon; A second mask process step of doping n + ions in a first region of each of the first to third active patterns and doping n-ions in a second region of each of the first to third active patterns; A third mask process step of doping P + ions into the first and second regions of the third active pattern; A fourth mask process step of forming a transparent pixel electrode in said pixel portion; First and second contacts exposing the pixel electrode and the first region of the first active pattern by patterning a second insulating layer on the entire surface of the substrate including the first and third active patterns. A fifth to form a hole, third and fourth contact holes respectively exposing the first region of the second active pattern, and fifth and sixth contact holes exposing the first region of the third active pattern, respectively; A mask processing step; The first region of the first active pattern through the first contact electrode and the second contact hole simultaneously contacting any one of the first regions of the first active pattern exposed through the first contact hole and the pixel electrode A first drain electrode in contact with the other one of the second source electrode, and a second source electrode and a second drain electrode in contact with one or the other of the first region of the second active pattern through the third and fourth contact holes, respectively. And a sixth mask process step of forming a third source electrode and a third drain electrode respectively contacting any one and the other of the first region of the third active pattern through the fifth and sixth contact holes. and, The first active pattern is located in the pixel portion, the second and third active patterns are located in the driving circuit portion, and the second regions of the first to third active patterns are disposed in the first to third gate electrodes. 12. A method of manufacturing an array substrate for a liquid crystal display device having a driving circuit, wherein the first region is located at both sides of the corresponding third region, and the first region is located at both sides of the second region. The method of claim 1, The second mask process step Stacking a first insulating layer, a polycrystalline silicon layer, and a photoresist layer on the entire surface of the substrate on which the first to third gate electrodes are formed; Placing a mask on the spaced upper portion of the photoresist layer as a blocking portion of a portion corresponding to the gate electrode, comprising a semi-transmissive portion on both sides of the blocking portion and a transmissive portion on both sides of the semi-transmissive portion; A developing process is performed in succession with an exposure process of irradiating light to the upper portion of the mask to correspond to the second region of the first gate electrode and the first active pattern on the first to third gate electrodes. A first photoresist pattern having a thickness of T1 and having a thickness of T2 less than the T1 corresponding to the first region of the first active pattern, and corresponding to the second region of the second gate electrode and the second active pattern A second photoresist pattern having a thickness of T1 and having a thickness of T2 corresponding to the first region of the second active pattern, and corresponding to a second region of the third gate electrode and the third active pattern Forming a third photoresist pattern having a thickness of T1 and having a thickness of T2 corresponding to the first region of the third active pattern; Patterning the polycrystalline silicon layer exposed between the first to third photoresist patterns to form first, second, and third active patterns on the first, second, and third gate electrodes; By etching the first, second and third photoresist patterns, an n + ion is doped into the first regions of each of the exposed first, second and third active patterns by removing a portion having a thickness of T2. Forming an area; The process of etching the etched first, second and third photoresist patterns is performed once again, exposing the second regions of each of the first, second and third active patterns while exposing the first, second and third photoresist patterns. Forming first, second and third photoresist patterns of substantially the same size as the third gate electrode; Doping n-ions into the second regions of the first, second, and third active patterns to form LDD regions; Array circuit manufacturing method for a drive circuit-integrated liquid crystal display device comprising a. The method according to any one of claims 1 to 2, The third mask process step A photoresist pattern is formed on the entire surface of the first, second, third, and active patterns and patterned with a third mask so as to completely cover the first and second active patterns, wherein the third active pattern is formed with a gate electrode. Forming a photoresist pattern covering only a corresponding portion; And forming an ohmic contact region by doping p + ions to the exposed third active pattern. The method of claim 1, And forming a buffer layer on the substrate before forming the first, second and third gate electrodes. The method of claim 1, And the buffer layer is formed of silicon nitride (SiN _X ) or silicon oxide (SiO ₂ ). The method of claim 1, And the transparent pixel electrode is formed of one selected from a group of transparent conductive metals including indium tin oxide (ITO) and indium zinc oxide (IZO). The method of claim 1, And the concentration of p + ions is greater than that of n + ions.

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