KR100924140B1 - Manufacturing Method of Flat Panel Display - Google Patents

Abstract

The present invention relates to a method of manufacturing a flat panel display device, comprising: forming a plurality of scan lines and a plurality of data lines on a substrate; Forming anti-static wires formed at ends of the plurality of scan lines to bind the scan lines together; Forming a thin film transistor on the substrate, the thin film transistor including a gate electrode formed at the same time as the antistatic wiring, and forming a gate insulating film or an interlayer insulating film having a hole exposing the antistatic wiring in the thin film transistor; Forming a passivation layer including a via hole exposing a source / drain electrode and a hole for cutting the antistatic wiring on the thin film transistor; After forming the first electrode material on the passivation layer, patterning the first electrode material and cutting the antistatic wiring exposed through the hole are simultaneously performed by the same etching solution. It is about a method.

Flat Panel Display, Anti-Static Wiring, Hall

Description

Method of manufacturing flat panel display {Method of fabricating Flat Panel Display}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flat panel display device, wherein in cutting an antistatic wiring for discharging static electricity generated during a manufacturing process, a simpler process is formed by simultaneously cutting the antistatic wiring while forming a first electrode. The present invention relates to a method for manufacturing a flat panel display device, the method comprising cutting an antistatic wiring.

Cathode ray tube (CRT), which is one of the commonly used display devices, is mainly used for monitors such as TVs, measuring devices, and information terminal devices.However, due to the weight and size of the CRT itself, You cannot actively respond.

In order to replace such a CRT, a flat panel display device having the advantages of small size and light weight has been attracting attention. The flat panel display includes a liquid crystal display (LCD), an organic electroluminescence display (OELD), and the like.

Such a flat panel display device is composed of a TFT substrate on which a TFT is formed and a light emitting element of red, green, and blue.

As described above, the flat panel display includes a TFT array process in which a TFT that applies a signal of a pixel unit is formed, and a process of forming red, green, and blue light emitting elements for realizing color, and a unit flat panel display. It is formed through a process of cutting into a cell (cell).

In this case, a cell cutting process of the unit flat panel display device includes a scribe process of forming a light emitting element on a TFT substrate, and then forming a cutting line on the TFT substrate, and applying a force along the cutting line. It consists of a break process which cut | disconnects the said TFT substrate.

The manufacturing process of such a flat panel display device is mostly performed on a substrate such as a glass substrate. Since such a substrate is a non-conductor, an instantaneous charge cannot be discharged below the substrate, which is very vulnerable to static electricity. Thus, the insulating film, TFT or light emitting element formed on the substrate may be damaged by static electricity.

In particular, static electricity has a very high voltage but a very low amount of charge, which locally degrades the substrate. In addition, the static electricity is mainly generated in the cell cutting process of cutting the substrate, and most of the static electricity flows through the pad portion of the scan line and the data line, causing deterioration of the channel of the TFT.

In the manufacturing process, an antistatic wiring is formed at the end of the scan line or data line to bundle the plurality of scan lines or data lines into one to discharge the static electricity generated. The antistatic wiring must be disconnected (cut) to apply a signal to each cell to operate the flat panel display.

In the conventional manufacturing process of disconnecting the antistatic wiring, the source / drain electrode was formed and the antistatic wiring was also disconnected, which is relatively weak in preventing the static electricity from the static electricity generated at the stage after the formation of the source / drain electrode. There was this. In addition, when the etchant for etching the source / drain electrodes and the etchant for disconnecting the antistatic wiring, there is a difficulty in disconnecting the antistatic wiring.

Disclosure of Invention The present invention is to solve the above-described problems of the prior art, and can effectively prevent static electricity even after the source / drain electrode forming step of the flat panel display manufacturing process, and can easily disconnect the antistatic wiring. The purpose is to provide a method for producing.

In order to achieve the above object, a flat panel display device manufacturing method according to the present invention,

Forming a plurality of scan lines and a plurality of data lines on the substrate; Forming anti-static wires formed at ends of the plurality of scan lines to bind the scan lines together; Forming a thin film transistor on the substrate, the thin film transistor including a gate electrode formed at the same time as the antistatic wiring, and forming a gate insulating film or an interlayer insulating film having a hole exposing the antistatic wiring in the thin film transistor; Forming a passivation layer including a via hole exposing a source / drain electrode and a hole for cutting the antistatic wiring on the thin film transistor; After forming the first electrode material on the passivation layer, patterning the first electrode material and cutting the antistatic wiring exposed through the hole are simultaneously performed by the same etching solution. How,

Wherein the source / drain electrode is characterized in that for forming the source / drain electrode by patterning the conductive layer using an etching solution containing a material of the stock solution is NH ₄ F or HF,

The hole for cutting the antistatic wiring is characterized in that it has the same width as the width of the antistatic wiring,

The gate electrode and the antistatic wiring are formed using Mo, Al, Cr and their respective alloys, or formed as a two-layer film of Al and Mo or a two-layer film of Cr and Al,

The first electrode material is any one selected from the group consisting of Ag / ITO, ITO / Ag / ITO, Al alloy / ITO and ITO / Al alloy / ITO,

As the etchant for etching the first electrode and the antistatic wiring, an etchant containing phosphoric acid is used as the etchant.

As described above, according to the present invention, in forming the first electrode on the substrate after forming the hole to expose the antistatic wiring at the time of forming the contact hole and the via hole, the first electrode material and the antistatic wiring material are formed. Both the etching solution can be used to form the first electrode and the anti-static wiring can be cut to simplify the process and reduce the cost. In addition, there is an effect of preventing the static electricity generated in the step subsequent to the formation of the source / drain electrodes, rather than disconnecting the anti-static wiring after etching and forming the conventional source / drain electrodes.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

1 is a plan view schematically illustrating a TFT substrate of a flat panel display device having antistatic wiring according to an embodiment of the present invention.

Referring to FIG. 1, a plurality of scan lines 210 and a plurality of data lines 220 are formed in the light emitting area to extend to the outside of the light emitting area. In this case, the plurality of scan lines 210 are formed in parallel in a first direction, and the plurality of data lines 220 are formed in parallel in a second direction perpendicular to the first direction.

In addition, the data line 220 is connected to the antistatic circuit 240 at an outer side of the light emitting area, and the antistatic circuit 240 prevents static electricity that may occur in a manufacturing process of a flat panel display device. .

In addition, although not shown in the drawing, a switching TFT and a driving TFT may be formed in a pixel area defined by the scan line 210 and the data line 220 crossing each other.

On the other hand, the end portion of the scan line 210 in the outer portion of the light emitting region, that is, the region between the light emitting region and the pad portion, the antistatic, called a shorting bar that binds the plurality of scan lines 210 together. Although the wiring 230 is formed, the antistatic wiring 230 serves to prevent static electricity that may occur in the manufacturing process of the flat panel display.

The antistatic wire 230 between any one of the plurality of scan lines 210 and the adjacent scan line 210 is exposed by a hole (330 of FIG. 2), and the hole 330 is a contact hole. And when the source / drain electrodes are formed, they are exposed and formed. In addition, at the same time as the via hole is formed, the hole 330 may be formed in the light emitting region, and the anti-static wiring through the hole 330 may be formed by etching the first electrode material to form the first electrode. 230) is etched.

FIG. 2 is an enlarged view of an antistatic wiring between each scan line of FIG. 1.

Referring to FIG. 2, the antistatic wire 320 between any one scan line 310 and the adjacent scan line 310 of the plurality of scan lines is formed as two or more parallel lines, and each line is At least one cut is performed by the hole 330 for cutting the antistatic wiring. In this case, the hole 330 for cutting the antistatic wiring 320 preferably has a width greater than or equal to the width of the antistatic wiring 320. This is to electrically insulate each scan line by sufficiently etching the antistatic wiring exposed by the hole at the same time as the first electrode material to be formed is patterned to form the first electrode.

3A to 3F are cross-sectional views illustrating a flat panel display including antistatic wiring according to a preferred embodiment of the present invention.

Referring to FIG. 3A, a flat panel display according to the present invention selectively forms a buffer layer (diffusion barrier) 410 with a predetermined thickness on a substrate 400 made of glass, synthetic resin, stainless steel, or the like. do. In this case, the buffer layer 410 is to prevent the diffusion of impurities in the substrate 400 during the crystallization process of the amorphous silicon formed in a subsequent process, it is deposited by a method such as PECVD, LPCVD, sputtering (sputtering).

Next, amorphous silicon is deposited on the buffer layer 410 to a predetermined thickness using a method such as PECVD, LPCVD, or sputtering, and then the amorphous silicon is crystallized and patterned by a photolithography process. A layer 420 is formed, and a gate insulating layer 430 is deposited on the entire surface of the substrate 400. In this case, the gate insulating film 430 may be formed using a silicon oxide film (SiO ₂ ), a silicon nitride film (SiN _x ), or a stacked structure thereof, and is preferably ELA, MIC, MILC, SLS, Crystallization processes such as SPC are used.

A gate insulating film 430 is deposited on the semiconductor layer 420, a conductive metal film is deposited on the gate insulating film 430, and then the conductive metal film is patterned to form a gate electrode 441. The gate electrode 441 is formed of at least one conductive film. Preferably, Mo, Al, Cr and a material consisting of their respective alloys may be used, and among the alloys, Mo / Al or Cr / Al alloys may be preferably used. Further, the gate electrode 441 can be formed of a two-layer film of Al and Mo or a two-layer film of Cr and Al.

At this time, the antistatic wiring 445 is formed of a material capable of forming the gate electrode 441 and the gate electrode material. The antistatic wiring 445 is to prevent static electricity that may occur in the manufacturing process of the flat panel display device.

Then, the source / drain regions 421 and 425 are formed by doping the semiconductor layer 420 with impurities having a predetermined conductivity type using the gate electrode 441 as a mask. A region of the semiconductor layer 420 that is not doped with impurities between the source / drain regions 421 and 425 serves as the channel region 423 of the TFT. In the present exemplary embodiment, the doping process is performed after the gate electrode 441 is formed, but the doping process may be performed before the gate electrode 441 is formed.

Referring to FIG. 3B, after the gate electrode 441 and the antistatic wiring 445 are formed, an interlayer insulating film 450 is formed on the entire surface of the substrate 400, and the interlayer insulating film 450 is patterned to form the interlayer insulating film 450. Contact holes 451 and 455 exposing portions of the source / drain regions 421 and 425 and holes 457 exposing portions of the antistatic wiring 445 are formed.

In this case, the contact holes 451 and 455 are formed, and the hole 457 exposing the antistatic wiring 445 is formed. At this time, the width of the hole 457 is preferably equal to the width of the anti-static wiring 445 or larger than the width of the anti-static wiring 445.

This is accomplished by sufficiently etching each of the anti-static wires 445 exposed by the hole 475 at the same time as the first electrode material formed thereafter is patterned and the first electrode 480 is formed. To insulate with

Referring to FIG. 3C, after forming holes 457 exposing the contact holes 451 and 455 and the antistatic wiring 445, a conductive material film is deposited on the entire surface of the substrate 400. 460 is formed. The conductive material film 460 may be formed of a two-layer film of Ti / Cu / Ti, Ta / Cu / Ta, Ta, and Cu, and a two-layer film of Ti and Cu.

Referring to FIG. 3D, after forming the predetermined conductive material film 460, the conductive material film 460 is etched to form source / drain electrodes 461 and 465.

The source / drain electrodes 461 and 465 may be a compound containing a fluorine ion as a stock etchant for etching the conductive material layer 460, and preferably an NH ₄ F or HF as an etchant. In addition, patterning using an etchant containing H ₂ O ₂ , methylimidazole (C ₄ H ₆ N ₂ ), pyrazole (C ₃ H ₄ N ₂ ), CH ₃ COOH, CH ₃ COONH _4, and CH ₃ COOK It can form by doing. When the conductive material layer 460 is etched using the etchant to form the source / drain electrodes 461 and 465, the antistatic wiring 445 is not simultaneously etched by the etchant. The antistatic wiring 445 may be formed of the same material as the material forming the gate electrode 441. The antistatic wiring 445 is made of at least one conductive film, preferably may be made of a material consisting of Mo, Al, Cr and their respective alloys, preferably Mo / Al or Cr / Al alloys may be used. Further, it may be made of a two-layer film of Al and Mo or a two-layer film of Cr and Al.

In the exemplary embodiment of the present invention, the gate insulating layer 430, the gate electrode 441, and the source drain electrodes 461 and 465 are positioned on the semiconductor layer 420 in the form of a top gate. However, the gate insulating layer is disposed below the semiconductor layer. The gate electrode may be positioned, and the same may be applied to the bottom gate type in which the source drain electrode may be positioned on the semiconductor layer.

Referring to FIG. 3E, after forming the source / drain electrodes 461 and 465, a protective film 470 is formed on the entire surface of the substrate 400 and then etched to form any of the source / drain electrodes 461 and 465. For example, a via hole 475 exposing a portion of the drain electrode 465 is formed, and a hole exposing the antistatic wiring 445 is formed to expose the antistatic wiring 445. The width of the hole is preferably equal to the width of the antistatic wiring 445 or larger than the width of the antistatic wiring 445.

This is accomplished by sufficiently etching the antistatic wiring 445 exposed by the hole 475 at the same time as the first electrode material formed thereafter is patterned to form the first electrode 480, thereby eliminating each scan line. To insulate electrically.

A first electrode material 479 is then formed over the substrate. The first electrode material 479 may use any one selected from the group consisting of Ag / ITO, ITO / Ag / ITO, Al alloy / ITO, and ITO / Al alloy / ITO. Due to the above process, a first electrode electrically connected to the drain electrode 465 can be formed through the via hole 475.

Referring to FIG. 3F, the first electrode material may be patterned to form a patterned first electrode 480. In order to form the first electrode 480 by patterning the first electrode material, etching is performed using an etchant. The etchant may not only etch the first electrode material, but also may remove and remove the antistatic wiring exposed through the hole. The etchant is an etchant containing the phosphoric acid in the stock solution to the etching action, preferably A _x H _y PO ₄ (where A is K, Na, 0≤x, y≤3, x + y = 3) Phosphorus materials can be used. In addition, the etching solution may further include nitric acid or acetic acid.

Therefore, by using the above-described etchant, not only the first electrode 480 may be formed, but also the antistatic wiring exposed by the hole may be etched to cut (disconnect) the antistatic wiring.

Thereafter, the formed first electrode 480 may be formed as a reflective film on the substrate 400 and a transparent electrode on the reflective film, wherein the reflective film is light emitted from an organic film (not shown) formed in a subsequent process. Is formed to reflect in the direction opposite to the substrate 400 (front emission). Here, the first electrode 480 serves as an anode electrode.

In this case, when the first electrode 480 is formed using the first electrode material, the organic light emitting diode emitting light may be manufactured.

Although not shown in the drawings, a flat panel display is formed by performing a manufacturing process of a general flat panel display.

1 is a plan view schematically showing a TFT substrate of a flat panel display device according to the present invention.

FIG. 2 is an enlarged view of an antistatic wiring between each scan line of FIG. 1.

3A to 3F are cross-sectional views illustrating a flat panel display device according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110, 210, 310. Scan lines 120, 220. Data lines

130, 230, 320, 445. Antistatic wiring 240. Antistatic circuit

330, 457. Hole 400. Substrate

410. Buffer layer 420. Semiconductor layer

421. Source area 423. Channel area

425. Drain region 430. Gate insulating film

441. Gate electrodes 451, 455. Contact holes

460. Conductive Material Film 461. Source Electrode

465. Drain electrode 470. Protective film

475. Via hole 479. First electrode material

480. First electrode

Claims (7)

Forming a plurality of scan lines and a plurality of data lines on the substrate; Forming anti-static wires formed at ends of the plurality of scan lines to bind the scan lines together; Forming a thin film transistor on the substrate, the thin film transistor including a gate electrode formed at the same time as the antistatic wiring, and forming a gate insulating film or an interlayer insulating film having a hole exposing the antistatic wiring in the thin film transistor; Forming a passivation layer including a via hole exposing a source / drain electrode and a hole for cutting the antistatic wiring on the thin film transistor; After forming the first electrode material on the passivation layer, patterning the first electrode material and cutting the antistatic wiring exposed through the hole are simultaneously performed by the same etching solution. Way. The method of claim 1, And the source / drain electrodes are formed of two layers of Ti / Cu / Ti, Ta / Cu / Ta, Ta and Cu, and two layers of Ti and Cu. The method of claim 2, The source / drain electrode may be formed by patterning the conductive layer using an etchant including a material having a stock solution of NH ₄ F or HF to form the source / drain electrode. The method of claim 1, And the hole for cutting the antistatic wiring has the same width as that of the exposed antistatic wiring. The method of claim 2, And the gate electrode and the antistatic wiring are formed using Mo, Al, Cr and their respective alloys, or a two-layer film of Al and Mo or a two-layer film of Cr and Al. The method of claim 2, And the first electrode material is any one selected from the group consisting of Ag / ITO, ITO / Ag / ITO, Al alloy / ITO, and ITO / Al alloy / ITO. The method of claim 2, A method of manufacturing a flat panel display device, characterized in that an etchant containing phosphoric acid is used as an etchant for etching the first electrode and the antistatic wiring.

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