KR100922789B1 - Line-on glass liquid crystal display device and driving method thereof - Google Patents

Abstract

The present invention provides a line-on-glass type liquid crystal display and a driving method thereof capable of minimizing image degradation due to signal distortion.

The line-on-glass type liquid crystal display according to the present invention includes a plurality of liquid crystal cells formed at each intersection of signal lines, and a line-on-glass type signal line for supplying driving signals for driving the liquid crystal cell is directly formed on the substrate. And a signal compensating unit configured to add and invert amplify at least two driving signals supplied to the liquid crystal panel to compensate for any one of the at least two driving signals.

Description

Line-on-glass type liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY OF LINE-ON-GLASS TYPE AND DRIVING METHOD THEREOF}             

1 is a plan view illustrating a line-on glass liquid crystal display device.

FIG. 2 is a diagram for describing a horizontal stripe phenomenon in the liquid crystal display illustrated in FIG. 1.

3 is a diagram illustrating a specific pattern causing greenish in the conventional liquid crystal display.

4A and 4B illustrate swing widths of a common voltage and a gate low voltage due to the specific pattern illustrated in FIG. 3.

FIG. 5 is a diagram for describing a greenish phenomenon due to the swing of the common voltage illustrated in FIGS. 4A and 4B.

FIG. 6 illustrates a specific pattern including a window that causes horizontal crosstalk in a conventional liquid crystal display.

FIG. 7 illustrates a comparison between swing widths of a common voltage and a gate low voltage in a section including a window region illustrated in FIG. 6 and a section including no window region.

FIG. 8 is a diagram for describing a horizontal crosstalk phenomenon due to the swing of the common voltage shown in FIG. 7.

9 is a plan view illustrating a LOG type liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 10 is a diagram illustrating in detail a signal compensator shown in FIG. 9.

FIG. 11 is a waveform diagram illustrating a compensation common voltage generated by the signal compensator shown in FIG. 10.

FIG. 12 is a diagram illustrating another form of the signal compensator shown in FIG. 9.

FIG. 13 is a waveform diagram illustrating a compensation common voltage generated by the signal compensator shown in FIG. 12.

<Description of main parts of drawing>

2,32: thin film transistor array substrate 4,34: color filter array substrate

6,36: liquid crystal panel 8,38: gate TCP

10,40: Gate Drive IC 12,42: Data TCP

14,44: Data Drive IC 16,46: Data PCB

18,48: FPC 20,50: Main PCB

22, 52: timing controller 24, 54: power supply

26,56: LOG signal line group 32: horizontal line

70,80,90: Signal compensator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a line on glass type liquid crystal display device and a driving method thereof capable of minimizing image degradation due to signal distortion.

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.

In the liquid crystal display panel, the liquid crystal cells display an image by adjusting the light transmittance according to the pixel signal.

The driving circuit includes a gate driver for driving the gate lines of the liquid crystal display panel, a data driver for driving the data lines, a timing controller for controlling the driving timing of the gate driver and the data driver, the liquid crystal display panel and the driving. And a power supply unit supplying power signals necessary for driving the circuits.

The data driver and the gate driver are separated into a plurality of integrated circuits (hereinafter, referred to as ICs) and manufactured in a chip form. Each of the integrated drive ICs is mounted on an open IC area on a tape carrier package (TCP) or mounted on a base film of TCP in a chip on film (COF) method, and a liquid crystal display panel and a tape automated bonding (TAB) method. Electrically connected. In addition, the drive IC may be directly mounted on the liquid crystal panel using a chip on glass (COG) method. The timing control unit and the power supply unit are manufactured in a chip form and mounted on a main printed circuit board (PCB).

The drive ICs connected to the liquid crystal display panel by TCP are connected to the timing control part and the power supply part of the main PCB through the flexible printed circuit (FPC) and the sub PCB. Specifically, the data drive ICs receive data control signals and pixel data from the timing controller mounted on the main PCB through the FPC and the data PCB, and power signals from the power supply. The gate drive ICs receive gate control signals from the timing controller mounted on the main PCB and power signals from the power supply through the gate FPC and the gate PCB.

Drive ICs mounted on a liquid crystal display panel in a COG method control signals from a timing controller mounted on a main PCB through line on glass (LOG) type signal lines formed on the FPC and the liquid crystal display panel. And power signals from the pixel data and the power supply unit.

Recently, even when the drive ICs are connected to the liquid crystal display panel via TCP, the LOG type signal lines are adopted to eliminate the PCB, thereby making the liquid crystal display device even thinner. In particular, signal lines for removing gate PCBs that transmit relatively few signals and supplying gate control signals and power signals to gate drive ICs are formed in a LOG type on the liquid crystal display panel. Accordingly, the gate drive ICs mounted in TCP are gate control signals from the timing controller and power signals from the power supply via the main PCB-> FPC-> data PCB-> data TCP-> LOG signal line-> gate TCP. Will be supplied. In this case, the gate control signals and the gate power signals supplied to the gate drive IC are distorted by the line resistance of the LOG signal lines, thereby causing a problem in that the quality of the image displayed on the liquid crystal display panel is degraded.

In detail, the LOG type liquid crystal display device in which the gate PCB is removed includes the main PCB 20 including the timing controller 22 and the power supply unit 24 and the main PCB (FPC 18) as shown in FIG. 1. A data PCB 16 connected to the 20, a data drive IC 14 mounted thereon, a data TCP 12 connected between the data PCB 16 and the liquid crystal display panel 6, and a gate drive IC 10; And a gate TCP 8 connected to the liquid crystal display panel 6.

The liquid crystal display panel 6 is formed by bonding the thin film transistor array substrate 2 and the color filter array substrate 4 to each other with a liquid crystal interposed therebetween. The liquid crystal display panel 6 includes liquid crystal cells independently driven by thin film transistors in regions defined by intersections of the gate lines GL and the data lines DL. The thin film transistor supplies the pixel signal from the data line DL to the liquid crystal cell in response to the scan signal from the gate line GL.

The data drive ICs 14 are connected to the data lines DL via the data TCP 12 and the data pad portion of the liquid crystal display panel 6. The data drive ICs 14 convert the pixel data into analog pixel signals and supply them to the data lines DL. To this end, the data drive ICs 14 transmit data control signals, pixel data, and power signals from the timing control unit 22 and the power supply unit 24 on the main PCB 20 via the data PCB 16 and the FPC 18. Will be supplied.

The gate drive ICs 10 are connected to the gate lines GL via the gate TCP 8 and the gate pad portion of the liquid crystal display panel 6. The gate drive ICs 10 sequentially supply scan signals of the gate high voltage VGH to the gate lines GL. In addition, the gate drive ICs 10 supply the gate low voltage VGL to the gate lines GL in a period other than the period in which the gate high voltage VGH is supplied.

To this end, gate control signals and power signals from the timing control unit 22 and the power supply unit 24 on the main PCB 20 are supplied to the data TCP 12 via the FPC 18 and the data PCB 16. . Gate control signals and power signals supplied through the data TCP 12 are supplied to the gate TCP 8 via the LOG signal line group 26 formed in the edge region of the thin film transistor array substrate 2. Gate control signals and power signals supplied to the gate TCP 8 are input into the gate drive IC 10 through the input terminals of the gate drive IC 10 and used. The gate control signals and the power signals are output through the output terminals of the gate drive IC 10, and the gate drive mounted on the next gate TCP 8 via the gate TCP 8 and the LOG signal line group 26. It is supplied to the IC 10.

The LOG signal line group 26 is normally supplied from the power supply unit 24 such as the gate low voltage VGL, the gate high voltage VGH, the common voltage VCOM, the ground voltage GND, and the base driving voltage VCC. DC drive voltages; It is composed of signal lines for supplying each of the gate control signals supplied from the timing controller 22, such as the gate start pulse GSP, the gate shift clock signal GSC, and the gate enable signal GOE.

The LOG signal line group 26 is formed in a fine pattern by using the same gate metal layer as the gate lines in a limited pad region of the thin film transistor array substrate 2. Further, as the LOG signal line group 26 is contacted with the gate TCP 8 through ACF bonding, the contact portion A with the gate TCP 8 increases, resulting in a large contact resistance. Accordingly, the LOG signal line group 26 has a larger line resistance than the signal lines of the conventional gate PCB. Due to this line resistance, the gate control signals GSP, GSC, and GOE transmitted through the LOG signal line group 26 and the power signals VGH, VGL, VCC, GND, and VCOM are distorted, thereby causing horizontal stripes, spots, and the like. The deterioration of image quality such as crosstalk of the dot pattern, greenish, etc. becomes worse.

For example, the LOG signal line groups 26 that supply the gate control signals GSP, GSC, and GOE and the power signals VGH, VGL, VCC, GND, and VCOM may include the gate TCP as shown in FIG. And first to fourth LOG signal line groups LOG1 to LOG4 connected to the respective ones 8. Each of the first to fourth LOG signal line groups LOG1 to LOG4 has a line resistance (aΩ, bΩ, cΩ, dΩ) that is proportional to the line length, and passes through the gate TCP 8 and the gate drive IC 10. Are connected in series. Due to the first to fourth LOG signal line groups LOG1 to LOG4, gate control signals GSP, GSC, and GOE input to each gate drive IC 10 and power signals VGH, VGL, VCC, GND, VCOM) will cause a level difference. As a result, a luminance difference is generated between the horizontal line blocks A to D driven by the different gate drive ICs 10, resulting in horizontal stripes 32.

Specifically, the first gate drive IC 10 is provided with the first line resistance aΩ of the first LOG signal line group LOG1, and the second gate drive IC 10 is provided with the first and second LOG signal line groups. Due to the first and second line resistances aΩ + bΩ of LOG1 and LOG2, the third gate drive IC 10 includes the first to third of the first to third LOG signal line groups LOG1 to LOG3. By the line resistance aΩ + bΩ + cΩ, the fourth gate drive IC 10 has the first to fourth line resistances aΩ + bΩ + cΩ + of the first to fourth LOG signal line groups LOG1 to LOG4. The gate control signals GSP, GSC, and GOE, which are dropped by dΩ, and the power signals VGH, VGL, VCC, GND, and VCOM are supplied. Accordingly, as the difference occurs between the gate signals VG1 to VG4 supplied to the gate lines of the first to fourth horizontal blocks A to D driven by different gate drive ICs 10, the horizontal Horizontal stripes 32 are generated between the line blocks A to D. FIG.

In addition, when a pattern in which black gray and 31 gray are alternated pixel by pixel is displayed on the liquid crystal panel driven by the dot inversion method as illustrated in FIG. 3, the data size of the transition between adjacent pixels is not canceled. And the gate low voltage VGL and the common voltage VCOM are supplied by the parasitic capacitor as shown in FIG. 4B. 4A and 4B show the common voltage (VCOM) and gate low voltage (VGL) waveforms swinged by parasitic capacitors when the black gray signal and the 31 gray signal are supplied in a dot inversion manner to a specific data line. will be. Here, it can be seen that the common voltage VCOM and the gate low voltage VGL swing with the same phase as the black gray signal having a relatively large voltage.

As a result, as shown in FIG. 5, when the black pixel signal is supplied to each of R1, G1, and B1 shown in FIG. 3 and the pixel signal of 31 gray is supplied to each of R2, G2, and B2, the swing is performed along the black pixel signal. Due to the common voltage VCOM, the pixel signal charging values VR2, VG2, and VB2 of R2, B2, and G2 become smaller than the pixel signal charging values VG1, VR1, and VB1 of G1, R1, and B1. Accordingly, the G2, R2, and B2 pixels appear relatively bright. R1 and B1, to which the black pixel signal is supplied, cannot be visually detected, so only the G2 pixel to which 31 gray is supplied becomes bright, and a greenish phenomenon occurs.

As shown in FIG. 6, when a pattern in which 31 grays and black grays alternate in sub pixel units is displayed on a liquid crystal panel and a window W displaying the same gray is displayed in a specific area, the window area W is displayed. Since the same gray is displayed, the pixel signal transition size between adjacent pixels cancels out. Accordingly, as illustrated in FIG. 7, the swing widths of the gate low voltage VGL and the common voltage VCOM in the T2 section including the window region W may include T1 not including the window region W. It becomes smaller than the interval. Therefore, the charge values of the pixels driven in the T2 section including the window region W and the pixels driven in the T1 section not included in the window region W are changed. Specifically, as shown in FIG. 8, when the lines R1, G1, and B1 are viewed, except for the G1 line (not visually sensed) to which the black pixel signal is supplied, the lines R1 and B1 are charged in the period T1 (VR1, VB1). It can be seen that the charge amounts VR2 and VB2 in the T2 section are smaller. As a result, horizontal crosstalk may be generated in which pixels driven in the T2 section including the window region W appear relatively brighter than pixels driven in the T1 section including the window region W. FIG.

As such, the swing voltages of the common voltage VCOM and the gate low voltage VGL according to the transition size of the pixel signal are induced to the ground line forming the current path. As a result, the swing width of the common voltage VCOM and the gate low voltage VGL is further increased by the relatively large resistance component of the LOG signal line supplying the ground voltage, thereby increasing the aforementioned greenish and horizontal crosstalk phenomena. It becomes clear.

Accordingly, an object of the present invention is to provide a LOG type liquid crystal display device and a driving method thereof capable of minimizing image degradation due to signal distortion.

In order to achieve the above object, the line-on-glass type liquid crystal display according to the present invention includes a plurality of liquid crystal cells formed at each crossing area of the signal lines and supplies a line-on-glass type signal for supplying driving signals for driving the liquid crystal cell. A liquid crystal panel having a line directly formed on the substrate, and a signal compensating unit configured to add and invert amplify at least two driving signals supplied to the liquid crystal panel to compensate for any one of the at least two driving signals; It is characterized by.

The line on glass type liquid crystal display may further include a power supply for generating the driving signals.

The signal compensator is positioned between the power supply unit and the liquid crystal panel.

The plurality of supply signals may include a common voltage signal applied to a common electrode of the liquid crystal panel and a gate low voltage signal applied to a gate line of the liquid crystal panel.

The signal compensator may add the at least two or more of the plurality of supply signals from the liquid crystal panel to add and amplify the compensation signal to generate the compensation signal.

The signal compensator includes an operational amplifier connected to a common voltage fed back from the liquid crystal panel and a gate low voltage fed back to an inverting terminal, and a common voltage generated from the power supply unit to a non-inverted terminal, an inverting terminal of the operational amplifier and the feedback. A first resistor connected between the common common voltage, a second resistor connected between the inverting terminal of the operational amplifier and the feedback gate low voltage, and a third connected between the inverting terminal of the operational amplifier and the output terminal of the operational amplifier It is characterized by including a resistance.

In order to achieve the above object, the driving method of the line-on-glass type liquid crystal display device according to the present invention comprises the steps of supplying a plurality of driving signals to the liquid crystal panel through the line-on-glass type signal lines formed on the liquid crystal panel, Generating a compensation signal by adding and inverting and amplifying at least two drive signals among a plurality of drive signals, and supplying the compensation signal to the liquid crystal panel to compensate for any one of the at least two drive signals. Characterized in that it comprises a step.

The supplying of the plurality of driving signals may include supplying a gate low voltage signal to a gate line formed in the liquid crystal panel, and supplying a common voltage signal to a common electrode formed in the liquid crystal panel. .

The generating of the compensation signal may include adding the gate low voltage signal and the common voltage signal fed back from the liquid crystal panel and the common voltage signal generated by the power supply unit, and inverting and amplifying the compensation signal.

The compensation signal and the drive signal are characterized in that the supply in the same horizontal period.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 9 to 13.

9 is a view showing a LOG type liquid crystal display device according to the present invention.

Referring to FIG. 9, a LOG type liquid crystal display according to the present invention includes a liquid crystal panel 36 having a liquid crystal cell matrix, and a gate drive IC for driving gate lines GL1 to GLn of the liquid crystal panel 36. 40, a data drive IC 44 for driving the data lines DL1 to DLm of the liquid crystal panel 36, a timing controller for controlling the gate drive IC 40 and the data drive IC 44. 52, a power supply unit 54 for generating a driving voltage for driving the liquid crystal display device, and a signal compensator 70 for compensating for distortion of driving signals applied to the liquid crystal panel 36.

The power supply unit 54 uses driving voltages (gate high voltage VGH, gate low voltage VGL, reference gamma voltage, and common voltage) required for driving the liquid crystal display using a voltage input from a system power supply (not shown). (VCOM) and the like, are supplied to the timing controller 52, the data drive IC 44, the gate drive IC 40, and the like.

The timing controller 52 relays video data (R, G, B) from the graphics card and supplies it to the data drive IC 44. In addition, the timing controller 52 generates timing signals and control signals for controlling data and driving timing of the gate drive ICs 44 and 40 in response to the control signal from the graphics card.

The liquid crystal panel 36 is formed by bonding the thin film transistor array substrate 32 and the color filter array substrate 34 with the liquid crystal interposed therebetween. The liquid crystal panel 36 is provided with liquid crystal cells independently driven by thin film transistors in regions defined by intersections of the gate lines GL and the data lines DL. The thin film transistor supplies the pixel signal from the data line DL to the liquid crystal cell in response to the scan signal from the gate line GL.

The data drive ICs 44 are connected to the data lines DL via the data TCP 42 and the data pad portion of the liquid crystal panel 36. Here, the data drive ICs 44 are mounted in the IC area opened in the data TCP 42 or mounted on the base film of the data TCP 42 in a COF manner. The data drive ICs 44 convert pixel data into analog pixel signals and supply them to the data lines DL. To this end, the data drive ICs 44 receive data control signals, pixel data, and power signals from the timing controller 52 and the power supply unit 54 on the main PCB 50 through the data PCB 46.

The gate drive ICs 40 are connected to the gate lines GL via the gate TCP 38 and the gate pad portion of the liquid crystal panel 36. Here, the gate drive ICs 40 are mounted in the IC region opened at the gate TCP 38 or mounted on the base film of the gate TCP 38 in a COF manner. The gate drive ICs 40 sequentially supply scan signals of the gate high voltage VGH to the gate lines GL. In addition, the gate drive ICs 40 supply the gate low voltage VGL to the gate lines GL in a period other than the period in which the gate high voltage VGH is supplied.

For this purpose, gate gate control signals and power signals from the timing controller 52 and the power supply 54 are supplied to the data TCP 42 via the data PCB 46. Gate control signals and power signals supplied through the data TCP 42 are supplied to the gate TCP 38 via the LOG signal line group 56 formed in the edge region of the thin film transistor array substrate 32. Gate control signals and power signals supplied to the gate TCP 38 are input into the gate drive IC 40 through the input terminals of the gate drive IC 40 and used. The gate control signals and the power signals are output through the output terminals of the gate drive IC 40, and the gate drive mounted on the next gate TCP 38 via the gate TCP 38 and the LOG signal line group 56. It is supplied to IC 40.

The LOG signal line group 56 is normally supplied from the power supply unit 54 such as a gate low voltage VGL, a gate high voltage VGH, a common voltage VCOM, a ground voltage GND, and a base driving voltage VCC. DC drive voltages; It is composed of signal lines for supplying each of the gate control signals supplied from the timing controller 52, such as the gate start pulse GSP, the gate shift clock signal GSC, and the gate enable signal GOE.

The signal compensator 70 is positioned between the power supply 54 and the liquid crystal panel 36. For example, the signal compensator 70 is positioned on any one of the main PCB 50, the data PCB 46, and the thin film transistor array substrate 32. The gate low voltage FVGL fed back through the first LOG type line LVGL supplied with the gate low voltage VGL, and the second LOG type line supplied with the Ag dot (not shown) and the common voltage VCOM. At least one of the compensation common voltage BVCOM and the compensation gate low voltage BVGL is generated using at least one of the common voltage FVCOM fed back through the LVCOM.

In detail, the signal compensator 70 is provided with the operational amplifier OP, the inverting (−) input terminal of the operational amplifier OP, and the common fed back fed back to the kth horizontal period. A first resistor R1 connected between the voltage FVCOM and connected between the inverting (−) input terminal of the operational amplifier OP and the gate low voltage FVGL fed back during the kth horizontal period; A second resistor R2 is connected between the output terminal of the operational amplifier OP and the inverting (−) input terminal of the operational amplifier OP. Meanwhile, the common voltage VCOM generated by the power supply unit 74 is connected to the non-inverting (+) input terminal of the operational amplifier OP.

The signal compensator 70 generates a compensation common voltage BVCOM by inverting and amplifying the gate low voltage FVGL and the common voltage FVCOM fed back after being applied in the kth horizontal period as shown in Equation 1 below. Done. At this time, the polarities of the compensation common voltage BVCOM, the pad back gate low voltage FVGL, and the common voltage FVCOM are opposite to each other.

The compensation common voltage BVCOM generated by the signal compensator 70 is applied to the liquid crystal cell through the second LOG line LVCOM and Ag dots in the same horizontal period. At least one of the compensation common voltage BVCOM applied to the liquid crystal cell and the swing unstable gate low voltage VGL and the common voltage VCOM applied to the liquid crystal cell cancel each other as shown in FIG. Accordingly, the variable voltage of the video data is compensated for by the gate low voltage VGL and the common voltage VCOM.

Meanwhile, as illustrated in FIG. 12, the signal compensator 80 provides an operational amplifier OP, an inverting (−) input terminal of the operational amplifier OP, and a gate low voltage fed back to the kth horizontal period ( And a fourth resistor R4 connected between the FVGLs, and a fifth resistor R5 connected between the output terminal of the operational amplifier OP and the inverting (−) input terminal of the operational amplifier OP. On the other hand, the ground voltage GND is supplied to the non-inverting (+) input terminal of the operational amplifier OP.

The signal compensator 80 generates a compensation gate low voltage BVGL obtained by inverting and amplifying the gate low voltage FVGL fed back after being applied in the k-th horizontal period as shown in Equation (2). At this time, the polarities of the compensation gate low voltage BVGL and the feedback gate low voltage FVGL are opposite to each other.

The compensation gate low voltage BVGL generated by the signal compensator 80 is applied to the liquid crystal cell through the first LOG line LVGL in the same horizontal period. The compensation gate low voltage BVGL applied to the liquid crystal cell and the swing unstable gate low voltage VGL applied to the liquid crystal cell are canceled with each other as shown in FIG. Accordingly, the variable voltage of the video data is compensated for by the gate low voltage VGL.

Meanwhile, as shown in FIG. 12, the signal compensator 80 supplies the operational amplifier OP, the inverting (−) input terminal of the operational amplifier OP, and the common voltage FVCOM fed back to the kth horizontal period. The fourth resistor (R4) is connected between) and the fifth resistor (R5) connected between the output terminal of the operational amplifier (OP) and the inverting (-) input terminal of the operational amplifier (OP). On the other hand, the ground voltage GND is supplied to the non-inverting (+) input terminal of the operational amplifier OP.

The signal compensator 80 generates the compensated common voltage BVCOM in which the fed back common voltage FVCOM is inverted and amplified after being applied in the k-th horizontal period as shown in Equation 3 below. At this time, the polarities of the compensation common voltage BVCOM and the common voltage FVCOM are opposite to each other.

The compensation common voltage BVCOM generated by the signal compensator 80 is applied to the liquid crystal cell through the second LOG line LVCOM and Ag dots in the same horizontal period. The compensation common voltage BVCOM applied to the liquid crystal cell and the swing unstable common voltage VCOM applied to the liquid crystal cell are canceled with each other as shown in FIG. Accordingly, the variable voltage of the video data is compensated for by the common voltage VCOM.

As described above, in the LOG type liquid crystal display according to the exemplary embodiment of the present invention, at least one of the compensation gate low voltage and the compensation common voltage is fed back by feeding back at least one of the gate low voltage and the common voltage supplied in the kth horizontal period. It is generated and supplied to the liquid crystal cell for the same horizontal period. Accordingly, the swing gate low voltage and the common voltage are canceled by at least one of the compensation gate low voltage and the compensation common voltage. In this case, horizontal streaks or spots that are conspicuous by at least one of the swing gate low voltage and the common voltage are eliminated. As a result, the greenish and the horizontal crosstalk can be eliminated by the compensation gate voltage and the compensation common voltage.

As described above, the LOG type liquid crystal display and the driving method thereof according to the present invention provide a gate by supplying a compensation signal voltage generated by feeding back at least one of a feedback gate low voltage and a common voltage to the liquid crystal panel for the same horizontal period. The swing voltage of the low voltage and the common voltage can be canceled out. The horizontal stripes due to the offset gate low voltage and the swing voltage of the common voltage can be minimized. In addition, it is possible to improve the greenish and horizontal crosstalk by minimizing the swing voltage.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

A liquid crystal panel including a plurality of liquid crystal cells formed at intersections of signal lines, and a line-on-glass signal line directly formed on a substrate for supplying a gate low voltage signal and a common voltage signal to the liquid crystal cells; And A gate low voltage signal supplied to the liquid crystal panel by adding and inverting the gate low voltage signal or the common voltage signal supplied to the liquid crystal panel together with the gate low voltage signal and the common voltage signal fed back from the liquid crystal panel; And a signal compensating unit for compensating for the common voltage signal. The method of claim 1, And a power supply unit for generating the gate low voltage signal and the common voltage signal. The method of claim 2, The signal compensation unit And a line-on-glass type liquid crystal display device positioned between the power supply unit and the liquid crystal panel. delete delete The method of claim 1, The signal compensation unit An operational amplifier having a common voltage signal fed back from the liquid crystal panel and a gate low voltage connected to an inverting terminal, and a common voltage signal from a power supply unit connected to a non-inverting terminal; A first resistor connected between the inverting terminal of the operational amplifier and the fed back common voltage, A second resistor connected between the inverting terminal of the operational amplifier and the feedback gate low voltage; and And a third resistor connected between the inverting terminal of the operational amplifier and the output terminal of the operational amplifier. Supplying a gate low voltage signal and a common voltage signal to the liquid crystal panel through line-on-glass signal lines formed on the liquid crystal panel; Generating a compensation signal by adding and inverting the gate low voltage signal or the common voltage signal supplied to the liquid crystal panel together with the gate low voltage signal and the common voltage signal fed back from the liquid crystal panel; And And compensating the gate low voltage signal or the common voltage signal by supplying the compensation signal to the liquid crystal panel. delete delete The method of claim 7, wherein And the compensation signal, the gate low voltage signal, and the common voltage signal are supplied in the same horizontal period.

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