KR100920349B1 - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

The thin film transistor array panel according to the present invention is formed on an insulating substrate, an insulating substrate, a polycrystalline silicon layer including a source region, a drain region and a channel region, a gate insulating film covering the polycrystalline silicon layer, a gate insulating film formed on the gate insulating film, and a portion of the channel region. The overlapping gate line, the transmissive electrode formed on the gate insulating film, the first interlayer insulating film formed on the substrate, the drain electrode formed on the first interlayer insulating film and connected to the data line and the drain region connected to the source region, And a reflective electrode formed on the second interlayer insulating film formed on the substrate and the second interlayer insulating film and connected to the drain electrode and having a transmission window.

Polycrystalline, Transmissive Electrode, Reflective Electrode

Description

Thin film transistor array panel and manufacturing method thereof

1 is a schematic layout view of a thin film transistor array panel.

2A is a layout view of a pixel area of a thin film transistor array panel according to a first exemplary embodiment of the present invention.

FIG. 2B is a cross-sectional view taken along line IIb-IIb ′ of FIG. 2A.

3A is a layout view of a driving unit of a thin film transistor array panel according to a first exemplary embodiment of the present invention.

FIG. 3B is a cross-sectional view taken along line IIIb-IIIb 'of FIG. 3A.

4A to 8B are diagrams illustrating a manufacturing method of a thin film transistor array panel according to a first exemplary embodiment of the present invention in order of process.

9 is a cross-sectional view of a thin film transistor array panel according to a second exemplary embodiment of the present invention.

※ Explanation of symbols about main part of drawing ※

121: gate line 123: gate electrode

140: gate insulating film 150: polysilicon layer

152 lightly doped region 153 source region

154: channel region 155: drain region                 

80 reflective electrode 90 transmissive electrode

601, 602, 603: interlayer insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor display panel and a method for manufacturing the same, and more particularly, to a polycrystalline silicon thin film transistor display panel and a method for manufacturing the same.

A thin film transistor (TFT) is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like. The thin film transistor array panel includes a scan signal line or a gate line for transmitting a scan signal, an image signal line or a data line for transferring an image signal, and a thin film transistor and a thin film transistor connected to the gate line and the data line. And a pixel electrode, a gate insulating film covering and insulating the gate wiring, and an interlayer insulating film covering and insulating the thin film transistor and the data wiring.

The thin film transistor includes a semiconductor layer forming a gate electrode and a channel which are part of a gate wiring, a source electrode and a drain electrode which are part of a data wiring, a gate insulating film and an interlayer insulating film, and the like. The thin film transistor is a switching device that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line.                         

The semiconductor layer included in such a thin film transistor is formed using amorphous silicon or polycrystalline silicon. Among these, the use of polycrystalline silicon has an advantage in that the operation speed is faster than that in the case of using amorphous silicon, and a driving circuit can be formed together on the substrate. However, when the thin film transistor array panel using amorphous silicon is used, more mask processing is required, which complicates the process. Therefore, there is a problem that the yield is reduced and the production cost is increased.

The present invention provides a thin film transistor array panel and a method of manufacturing the same to solve the above problems and to simplify a manufacturing process of a thin film transistor array panel.

In order to achieve the above object, the thin film transistor array panel according to the present invention is formed on an insulating substrate and an insulating substrate, and includes a polycrystalline silicon layer including a source region, a drain region, and a channel region, a gate insulating layer covering the polycrystalline silicon layer, and a gate insulating layer. A gate line formed partially overlapping the channel region, a transmission electrode formed on the gate insulating layer, a first interlayer insulating layer formed on the substrate, a data line and a drain region formed on the first interlayer insulating layer and connected to the source region; And a drain electrode connected to the drain electrode, a second interlayer insulating film formed on the substrate, and a reflective electrode formed on the second interlayer insulating film and connected to the drain electrode.                     

At this time, the gate line and the transmissive electrode are formed of a double layer of the transmissive conductor pattern and the wiring conductor pattern formed in the transmissive conductor pattern, and the transmissive window preferably exposes the transmissive conductor pattern.

The other thin film transistor array panel is formed on an insulating substrate, an insulating substrate, a polycrystalline silicon layer including a source region, a drain region and a channel region, a gate insulating film covering the polycrystalline silicon layer, a gate insulating film formed on the gate insulating film, and partially overlapping the channel region. A gate line, a first interlayer insulating film formed over the substrate, a data line formed over the first interlayer insulating film, a drain electrode connected to the drain region, a transmissive electrode formed over the first interlayer insulating film, and a substrate And a reflective electrode formed on the formed second interlayer insulating film and the second interlayer insulating film and connected to the drain electrode and having a transmission window. At this time, it is preferable that the data line and the transmission electrode are formed of a double layer of the transmission conductor pattern and the wiring conductor pattern formed on the transmission conductor pattern, and the transmission window exposes the transmission conductor pattern.

The transmissive electrode is preferably located in the pixel region defined by the gate line and the data line, the transmissive conductor pattern is formed of IZO, and the wiring conductor pattern is formed of molybdenum-tungsten. In addition, it is preferable to further include a lightly doped region between the source region and the channel region, between the drain region and the channel region.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array panel, including forming a blocking layer and an amorphous silicon layer on an insulating substrate, heat treating the amorphous silicon layer, and then patterning the polysilicon pattern to form a polycrystalline silicon pattern. Forming a gate insulating film on the gate insulating film, forming a transmission conductive layer and a wiring conductive layer on the gate insulating film, and then patterning the wiring conductive layer and the transmission conductive layer to form a gate line and a transmission line formed of a wiring conductor pattern and a transmission conductor pattern. Forming an electrode pattern for the semiconductor layer, doping a polycrystalline silicon pattern with a gate line as a mask to form a source region, a drain region, and a channel region which is not doped with impurities, and exposing the source region over the entire substrate. 1 contact hole, the second contact hole exposing the drain region and the electrode pattern for transmitting the exposed Forming a first interlayer insulating film having a first exposure opening, and exposing a transmission conductor pattern of the transmission conductor pattern by removing a predetermined region of the wiring conductor pattern of the transmission electrode pattern through the first exposure opening; Forming a transmissive electrode having a transparent region, forming a metal layer on the first interlayer insulating layer, and patterning the data line to be connected to the source region through the first contact hole, and the drain electrode connected to the drain region through the second contact hole Forming a second interlayer insulating film having a third contact hole exposing the drain electrode on the front surface of the substrate and a second exposing hole exposing the transparent area, and draining the third interlayer insulating film over the second interlayer insulating film. And forming a reflective electrode connected to the electrode and having a transmission window exposing the second exposure opening.

Alternatively, forming a blocking layer and an amorphous silicon layer on an insulating substrate, heat treating and patterning the amorphous silicon layer to form a polycrystalline silicon pattern, forming a gate insulating film on the entire surface of the substrate, and forming a metal layer on the gate insulating film. Forming a gate layer by patterning a metal layer after the formation, forming a source region and a drain region by doping a polycrystalline silicon pattern with a gate line as a mask to form a source region and a drain region, and exposing the source region over the entire surface of the substrate. Forming a first interlayer insulating film having a second contact hole exposing a sphere and a drain region; forming a transmission conductive layer and a wiring conductive layer on the first interlayer insulating film and then patterning the electrode layer for transmission and the first contact hole Forming a data line connected to the source region through a second contact hole and a drain electrode connected to the drain region through a second contact hole Forming a second interlayer insulating film having a third contact hole exposing the drain electrode and an exposure hole exposing the wiring metal pattern on the entire surface of the substrate; and removing a predetermined region of the metal pattern for wiring through the exposed hole to transmit the conductive material. Forming a transmissive electrode having a transparent region exposing the pattern, wherein the reflective electrode is connected to the drain electrode through a third contact hole on the second interlayer insulating layer and has a transmissive window exposing the transmissive conductor pattern through the exposed hole; Forming a step.

It is preferable that the permeable conductive layer is formed of IZO, and the conductive layer for wiring is formed of molybdenum tungsten.

In addition, the transmission electrode is preferably located in the pixel region defined by the gate line and the data line.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Referring now to the accompanying drawings, a preferred embodiment according to the present invention will be described in detail.

[First Embodiment]

1 is a schematic layout view of a thin film transistor substrate for a transflective liquid crystal display according to a first embodiment of the present invention.

As illustrated, the thin film transistor array panel includes driving regions 410 and 510 for controlling the display region A together with the display region A. FIG. In the display area A, a thin film transistor, a gate line connected to the thin film transistor, a data line, a pixel electrode, and the like are formed. In the driving circuit unit, an N-type, a P-type thin film transistor, a complementary thin film transistor connected to the display area, or a mixture thereof is formed.

Hereinafter, the display area A according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. The display area A is described using an N-type thin film transistor as an example. FIG. 2A is a layout view illustrating one pixel area of the display area, and FIG. 2B is a cross-sectional view taken along line IIb-IIb ′ of FIG. 2A.                     

As illustrated, a blocking layer 111 is formed on the transparent insulating substrate 110. The first polycrystalline silicon pattern 150a including the source region 153a, the drain region 155a, and the channel region 154a is formed on the blocking layer 111. A lightly doped drain 152 is formed between the source region 153a and the channel region 154a and between the drain region 155a and the channel region 154a. The lightly doped region 152 prevents leakage current or punch through. The source region 153a and the drain region 155a are heavily doped with N-type or P-type conductive impurities, and the channel region 154a is not doped with impurities.

The gate insulating layer 140 is formed on the polysilicon layer 150a. The gate line 121a, the storage electrode line 131, and the transmission electrode 90 are formed on the gate insulating layer 140. The gate line 121 is formed to be elongated in one direction and includes a gate electrode 123a that extends a part of the gate line 121 to overlap the channel region 154a. One end of the gate line 121 is extended in width to connect to an external circuit. The storage electrode line 131 is for increasing the storage capacitance of the pixel region PX and is formed in parallel with the gate line 121. The transmissive electrode 90, together with the reflective electrode 80 described later, constitutes a pixel electrode and transmits the light transmitted from the backlight to the liquid crystal.

The gate line 121, the gate electrode 123a, the storage electrode line 131a, and the transmission electrode 90 are formed of a double layer of the transmission conductor pattern 901 and the wiring conductor pattern 902. Among them, light is transmitted through the transparent electrode T in which the predetermined portion of the wiring conductor pattern 902 is removed. The transparent conductor pattern 901 is made of IZO, and the wiring conductor pattern 902 is formed of molybdenum-tungsten.

First and second interlayer insulating films 601 and 602 are formed on the gate line 121, the gate electrode 123a, and the storage electrode line 131. The first interlayer insulating film 601 is formed of SiO 2, and the second interlayer insulating film 602 is formed of SiN. When the SiO2 and SiN bilayers are formed rather than the SiO2 single layer, the reliability of the thin film transistor is improved compared with that formed by the SiO single layer.

First and second contact holes 161 and 162 are formed over the first and second interlayer insulating layers 601 and 602 and the gate insulating layer 140. The first contact hole 161 exposes the source region 153a of the first polycrystalline silicon layer 150a, and the second contact hole 162 exposes the drain region 155a.

A data line 171a defining the pixel region PX is formed on the second interlayer insulating layer 602 to cross the gate line 121a. The source electrode 173a overlapping the source region 153a and connected to the source region 153a through the first contact hole 161 is formed to have a portion of the data line 171a extended. A drain electrode 175a connected to the drain region 155a through the second contact hole 162 is formed on the second interlayer insulating layer 601 overlapping the drain region 155a. One end of the data line 171a is also widened to connect to an external circuit.

A third interlayer insulating layer 603 having a fifth contact hole 165 and a sixth contact hole 166 is formed on the data line 171a, the source electrode 173a, and the drain electrode 175a. The fifth contact hole 165 exposes the drain electrode 175a, and the sixth contact hole 166 exposes the first interlayer insulating layer 601 corresponding to the predetermined region of the storage electrode line 131. The reflective electrode 80 is formed on the third interlayer insulating layer 603 including the fifth and sixth contact holes 165 and 166. The reflective electrode 80 is connected to the drain electrode 175a through the fifth contact hole 165 and corresponds to the storage electrode line 131 through the sixth contact hole 166. In addition, the reflective electrode 80 has a transmission window 82 exposing the transmission electrode 90. The interlayer insulating films 601 and 602 under the transmission window 82 are removed. Therefore, the transmissive electrode 90 is exposed through the transmissive window 82, and the light transmitted through the transmissive electrode 90 is transmitted to the liquid crystal. The third interlayer insulating film 603 may be formed of an organic film to form embossing on the surface thereof. Embossing improves the reflectivity when using reflective electrodes.

Next, the driving circuit units 410 and 510 according to the present invention will be described using P-type thin film transistors as an example. FIG. 3A is a layout view of one P-type thin film transistor in the driving circuit units 410 and 510, and FIG. 3B is a cross-sectional view taken along line IIIb-IIIb '. As illustrated, the second polycrystalline silicon pattern 150b including the source region 153b, the drain region 155b, and the channel region 154b is formed on the transparent insulating substrate 110. Formed. The gate insulating layer 140 is formed on the second polycrystalline silicon pattern 150b, and the gate electrode 123b is formed on the gate insulating layer 140. The gate electrode 123b is connected to a gate line (not shown) for applying a voltage.

First and second interlayer insulating layers 601 and 602 are formed to cover the gate electrode 123b and have third and fourth contact holes 163 and 164 exposing the source region 154b and the drain region 155b. It is. A source electrode 173b and a drain electrode 175b connected to the source region 154b, the drain region 155b are formed on the second interlayer insulating layer 602, respectively. The source electrode 173b and the drain electrode 175b are also connected to data lines (not shown) for applying a voltage to them. An interlayer insulating layer may be further formed on the source electrode 173b and the drain electrode 175b according to the structure of the thin film transistor formed in the pixel region.

A method of manufacturing the thin film transistor array panel according to the first embodiment of the present invention described above will be described in detail. Hereinafter, one P-type thin film transistor in the pixel area PX and the driving circuit units 410 and 510 in the display area A will be described as an example. Their connection is not shown. 4A to 8B are diagrams illustrating a method of manufacturing a thin film transistor array panel according to a first exemplary embodiment of the present invention in the order of process.

First, as shown in FIGS. 4A and 4C, the blocking layer 111 and the amorphous silicon layer are formed on the transparent insulating substrate 110 on which the display area and the driving circuits 410 and 510 are defined. The blocking layer 111 is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx). After that, the amorphous silicon layer is crystallized by laser annealing or furnace annealing and patterned to form first and second polycrystalline silicon patterns 501 and 502 in the display area and the driving circuit (first mask). ).

As shown in FIGS. 5A to 5C, the gate insulating layer 140, the transparent conductive layer 201, and the wiring conductive layer 202 are formed on the polycrystalline silicon patterns 501 and 502. The gate insulation layer 140 is formed by depositing an insulating material such as silicon nitride or silicon oxide by a chemical vapor deposition method. Thereafter, after forming the photosensitive layer on the wiring conductive layer 202, the wiring conductive layer 202 and the transparent conductive layer 201 are sequentially etched to form the P-type gate electrode 123b (second mask). In this case, the photosensitive layer is formed to protect the pixel area and to expose a portion of the second polycrystalline silicon pattern 502. The P-type gate electrode 123b is formed of a double layer of a wiring conductor pattern 902 and a transmission conductor pattern 901.

The P-type source region 153b and the drain region 155b are formed by doping the P-type conductive impurity with the P-type gate electrode 123b as a mask. The undoped portion under the P-type gate electrode 123b becomes the channel region 154b.

6A to 6C, after the photosensitive layer is removed, a chromium (Cr) layer is stacked on the entire surface of the substrate 110. After the photosensitive layer is formed on the chromium layer, the wiring conductive layer 202 and the transparent conductive layer 201 are patterned to form a doping conductor pattern MP, a gate line 121 of the pixel region, and a gate electrode 123a. The storage electrode line 131 and the transmission electrode pattern 90A are formed (third mask). These also consist of a double layer of the transparent conductor pattern 901 and the wiring conductor pattern 902.

When the storage capacitor is sufficient, the storage electrode line 131 may not be formed. The doping conductor pattern MP is used to form the source region 153a and the drain region 155a by doping the first polycrystalline silicon pattern 501 with impurities to form the gate line 121 and the gate electrode of the pixel region. 123a, the sustain electrode line 131, and the transmission electrode pattern 90A are patterned in the same pattern, and the driving circuit portion is formed so as not to be exposed to protect the second polycrystalline silicon pattern 150b and the gate electrode 123b of the driving portion. do. In this case, etching is performed using an etchant having an etching ratio difference between the lower layers 121, 123a, and 131 and the chromium layer. Accordingly, the lower layers 901 and 902 are overetched compared to the chromium layer, so that the gate lines 121, the gate electrodes 123a, the sustain electrode lines 131, and the transmissive electrode patterns are narrower than the doping conductor pattern MP. 90A can be formed. Thereafter, the first polycrystalline silicon pattern 501 is heavily doped with N-type conductive impurities using the doping conductor pattern MP as a mask to form the source region 153a and the drain region 155a.

As shown in FIGS. 7A to 7C, after the doping conductor pattern MP is removed, the gate line 121, the gate electrode 123a, the sustain electrode line 131, and the transmissive electrode pattern 90A are polycrystalline with a mask. The N-type conductive dopant is doped to the silicon pattern 501 at a lower concentration than the source region 153a and the drain region 155a to form a low concentration doped region 152. At this time, impurities are not doped under the gate electrode 123a, and the portion becomes the channel region 154a of the polysilicon layer 150a.

Thereafter, the first and second interlayer insulating layers 601 and 602 are formed on the entire surface of the substrate 110, and then the second interlayer insulating layer 602, the first interlayer insulating layer 601 and the gate insulating layer 140 are etched by a photolithography process. The first to fourth contact holes 161 to 164 are formed to form a first exposure hole 167 exposing the transmission electrode pattern 90A (fourth mask). Subsequently, the upper layer 902 of the transmissive electrode pattern 90A is etched and removed through the first exposure hole 167 to form the transmissive electrode 90 having the transparent region T formed only of the IZO pattern 901. do. At this time, the etching proceeds to dry etching, and the first and second interlayer insulating layers 601 and 602, the gate insulating layer 140, and the wiring conductor pattern 902 are etched by using different etching gases to etch each layer.

As shown in FIGS. 8A to 8C, the metal layer is formed on the second interlayer insulating layer 601 and then patterned to form the source regions 153a and 153b and the drain region through the first to fourth contact holes 161 to 164. Source electrodes 173a and 173b and drain electrodes 175a and 175b connected to 155a and 155b are formed (a fifth mask).

Subsequently, a third interlayer insulating layer 603 is formed on the source electrodes 173a and 173b and the drain electrodes 175a and 175b and then etched by a photolithography process to form a fifth contact hole 165 (a sixth mask). . In this case, together with the first exposure opening 167, a second exposure opening 168 exposing the transparent region T is also formed.

Embossing is also formed on the surface of the third interlayer insulating film 603 positioned below the reflective electrode 80. Embossing can be formed using a slit or a semipermeable membrane. Since they are low in light transmittance, only a part of the photosensitive layer is exposed, so that the photosensitive layer can be formed with a thickness different from that of other portions. Therefore, the embossing can be formed together with the contact holes 163 and 164.

Thereafter, a metal layer is formed on the entire surface of the substrate including the fifth contact hole 165 and then patterned to form the reflective electrode 80 (seventh mask). In this case, the reflective electrode 80 has a transmission window 82 exposing the transparent region T. The reflective electrode 80 is formed of a metal having high reflectance, for example, metal such as aluminum (see FIGS. 2A to 2C).

Second Embodiment                     

7 is a cross-sectional view of a thin film transistor array panel according to a second exemplary embodiment of the present invention.

First, as illustrated in the pixel area, the blocking layer 111 is formed on the transparent insulating substrate 110. The polysilicon layer 150a including the source region 153a, the drain region 155a, and the channel region 154a is formed on the blocking layer 111. A lightly doped region 152 is formed between the source region 153a and the channel region 154a and between the drain region 155a and the channel region 154.

A gate insulating layer 140 is formed on the polysilicon layer 150a. The gate line 121 and the storage electrode line 131 are formed on the gate insulating layer 140. The gate line 121 is formed to be elongated in one direction and includes a gate electrode 123a that extends a part of the gate line 121 to overlap the channel region 154a. One end of the gate line 121 may be extended to receive an external signal. The storage electrode line 131 is for increasing the storage capacitance of the pixel region PX and is formed in parallel with the gate line 121.

First and second interlayer insulating films 601 and 602 are formed on the gate line 121, the gate electrode 123a, and the storage electrode line 131. First and second contact holes 161 and 162 are formed over the first and second interlayer insulating layers 601 and 602 and the gate insulating layer 140. The first contact hole 161 exposes the source region 153a of the polycrystalline silicon layer 150, and the second contact hole 162 exposes the drain region 155a.

The data line 171 and the transmission electrode 90 are formed on the second interlayer insulating layer 602. The data line 171 crosses the gate line 121 to define a pixel area. The source electrode 173a overlapping the source region 153a and connected to the source region 153a through the first contact hole 161 is formed to have a portion of the data line 171 extended. A drain electrode 175a connected to the drain region 155a through the second contact hole 162 is formed on the second interlayer insulating layer 601 overlapping the drain region 155a. One end of the data line 171 may be extended to receive an external signal. These data lines 171, the source electrode 173a, the drain electrode 175a, and the transmission electrode 90 are formed of a double layer of a transmission conductor pattern 901 and a wiring conductor pattern 901. At this time, the transmissive electrode 90 has a transparent region T formed by partially removing the wiring conductor pattern 901. The transmission conductor pattern 901 is made of IZO, and the wiring conductor pattern 902 is made of molybdenum-tungsten.

A third interlayer insulating layer 603 including fifth and sixth contact holes 165 and 166 is formed on the data line 171, the source electrode 173a, the drain electrode 175a, and the transmission electrode 90. . The fifth contact hole 165 exposes the drain electrode 175a, and the sixth contact hole 166 exposes the second interlayer insulating layer 602 corresponding to the storage electrode line 131. The reflective electrode 80 is formed on the third interlayer insulating layer 602 including the fifth and sixth contact holes 165 and 166. The reflective electrode 80 is connected to the drain electrode 175a through the fifth contact hole 165 and has a transmission window 82 exposing the transmission electrode 80. The interlayer insulating film 603 under the transmission window 82 is removed. Therefore, the transmission electrode 90 is exposed through the transmission window 82, and the light transmitted through the transmission electrode 90 is transmitted to the liquid crystal. The third interlayer insulating film 603 may be formed of an organic film to form embossing on the surface thereof. Embossing improves the reflective ability of the reflective electrode 90.

The driving circuits 410 and 510 are formed in the same structure as in the first embodiment. However, in the second embodiment, the source electrode 173b and the drain electrode 175b are formed of a double layer of the transmission conductor pattern 901 and the wiring conductor pattern 902. The gate electrode 123a is formed in the same manner as the gate electrode 123a of the pixel region in the above-described second embodiment.

As described above, when the gate line or the data line is formed of the transparent metal layer and the wiring metal layer, the transmission electrode is formed at the same time, and the wiring metal layer is removed to form the transmission electrode, the process for forming the transmission electrode can be omitted. As a result, the total number of processes can be reduced.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

As described above, when the transmissive electrode is formed according to the present invention, the process for forming the thin film transistor array panel may be simplified to improve productivity and yield.

Claims (11)

Insulation board, A polysilicon layer formed on the insulating substrate and including a source region, a drain region, and a channel region. A gate insulating film covering the polycrystalline silicon layer, A gate line and a transmission electrode formed on the gate insulating layer and formed of a double layer of a transmission conductor pattern and a wiring conductor pattern; A first interlayer insulating film formed on the substrate, A drain electrode formed on the first interlayer insulating layer and connected to the source region and the drain region; A second interlayer insulating film formed on the substrate, A reflective electrode formed on the second insulating interlayer, the reflective electrode having a transmission window connected to the drain electrode and exposing a transmission conductor pattern of the transmission electrode; The reflective electrode is in contact with the transparent conductive pattern of the transmission electrode of the thin film transistor array panel. Insulation board, A polysilicon layer formed on the insulating substrate and including a source region, a drain region, and a channel region. A gate insulating film covering the polycrystalline silicon layer, A gate line formed on the gate insulating layer and overlapping the channel region; A first interlayer insulating film formed on the substrate, A data line, a drain electrode, and a transmission electrode formed on the first interlayer insulating layer and formed of a double layer of a transmission conductor pattern and a wiring conductor pattern; A second interlayer insulating film formed on the substrate, A reflective electrode formed on the second interlayer insulating layer and connected to the drain electrode and having a transmission window exposing a transmission conductor pattern of the transmission electrode, The reflective electrode is in contact with the transparent conductive pattern of the transmission electrode of the thin film transistor array panel. delete delete The method of claim 1 or 2, A storage electrode line formed on the insulating substrate and overlapping the reflective electrode; And the second interlayer insulating layer positioned on the storage electrode line is removed. The method of claim 1 or 2, The transmission conductor pattern is formed of IZO, and the wiring conductor pattern is formed of molybdenum-tungsten. The method of claim 1 or 2, And a lightly doped region between the source region and the channel region and between the drain region and the channel region. Forming a blocking layer and an amorphous silicon layer on the insulating substrate, Heat-treating and patterning the amorphous silicon layer to form a polycrystalline silicon pattern, Forming a gate insulating film on the entire surface of the substrate; Forming a transmission conductive layer and a wiring conductive layer on the gate insulating film, and then patterning the wiring conductive layer and the transmission conductive layer to form a gate line and a transmission electrode pattern consisting of a wiring conductor pattern and a transmission conductor pattern. step, Doping the polysilicon pattern with conductive impurities using the gate line as a mask to form a source region and a drain region including conductive impurities and a channel region positioned between the source region and the drain region; Forming a first interlayer insulating layer having a first contact hole exposing the source region, a second contact hole exposing the drain region, and a first exposure hole exposing the transmission electrode pattern on an entire surface of the substrate; Removing a wiring conductor pattern of the transmission electrode pattern exposed through the first exposure hole to form a transmission electrode having a transmission region exposing the transmission conductor pattern; Forming and patterning a metal layer on the first interlayer insulating layer to form a data line connected to the source region through the first contact hole and a drain electrode connected to the drain region through the second contact hole; Forming a second interlayer insulating film having a third contact hole exposing the drain electrode and a second exposure hole exposing the transmissive region on the entire surface of the substrate; The second interlayer insulating layer is connected to the drain electrode through the third contact hole, and is connected to the transmission conductor pattern through the second exposure hole, and has a transmission window exposing the transmission conductor pattern. A method of manufacturing a thin film transistor array panel comprising forming a reflective electrode. Forming a blocking layer and an amorphous silicon layer on the insulating substrate, Heat-treating and patterning the amorphous silicon layer to form a polycrystalline silicon pattern, Forming a gate insulating film on the entire surface of the substrate; Forming a metal layer on the gate insulating layer and then patterning the metal layer to form a gate line; Forming a source region and a drain region by doping the polycrystalline silicon pattern with conductive impurities using the gate line as a mask; Forming a first interlayer insulating film having a first contact hole exposing the source region and a second contact hole exposing the drain region on an entire surface of the substrate; A transmissive electrode pattern formed on the first interlayer insulating layer and a wiring conductive layer and patterned thereon, the transmission electrode pattern comprising a wiring conductor pattern and a transmission conductor pattern and connected to the source region through the first contact hole Forming a drain electrode connected to the drain region through the data line and the second contact hole; Forming a second interlayer insulating film having a third contact hole exposing the drain electrode and an exposure hole exposing the wiring metal pattern on an entire surface of the substrate; Removing the metal pattern for wiring exposed through the exposure hole to form a transmission electrode having a transmission region exposing the transmission conductor pattern; Forming a reflective electrode on the second interlayer insulating layer, the reflective electrode having a transmission window connected to the drain electrode through the third contact hole and exposing the transmission conductor pattern through the exposure hole; Manufacturing method. The method of claim 8 or 9, And the transmission conductive layer is formed of IZO, and the wiring conductive layer is formed of molybdenum tungsten. The method of claim 8 or 9, And the transmission electrode is in a pixel region defined by the gate line and the data line.

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