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KR100919080B1 - Semiconductor device and fabricating method thereof - Google Patents

Semiconductor device and fabricating method thereof

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Publication number
KR100919080B1
KR100919080B1 KR1020080005728A KR20080005728A KR100919080B1 KR 100919080 B1 KR100919080 B1 KR 100919080B1 KR 1020080005728 A KR1020080005728 A KR 1020080005728A KR 20080005728 A KR20080005728 A KR 20080005728A KR 100919080 B1 KR100919080 B1 KR 100919080B1
Authority
KR
South Korea
Prior art keywords
metal layer
semiconductor die
solder
wafer
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020080005728A
Other languages
Korean (ko)
Other versions
KR20090079618A (en
Inventor
진정기
이기욱
박성수
Original Assignee
앰코 테크놀로지 코리아 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 앰코 테크놀로지 코리아 주식회사 filed Critical 앰코 테크놀로지 코리아 주식회사
Priority to KR1020080005728A priority Critical patent/KR100919080B1/en
Publication of KR20090079618A publication Critical patent/KR20090079618A/en
Application granted granted Critical
Publication of KR100919080B1 publication Critical patent/KR100919080B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
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    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
    • H01L25/073—Apertured devices mounted on one or more rods passed through the apertures
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Abstract

본 발명은 정밀한 반도체 다이 본딩 장비가 없더라도 실리콘 관통 전극을 갖는 반도체 다이가 용이하게 스택될 수 있는 반도체 디바이스 및 그 제조 방법에 관한 것이다.The present invention relates to a semiconductor device and a method of manufacturing the semiconductor die having a silicon through electrode can be easily stacked even without precise semiconductor die bonding equipment.

이를 위해 본 발명의 반도체 디바이스는 평평하게 형성된 제 1면 및 상기 제 1면의 반대면으로서 평평하게 형성된 제2면을 갖고, 제 1면에 다수의 본드 패드를 갖는 반도체 다이, 본드 패드의 에지를 덮도록 반도체 다이의 제 1면에 형성되는 패시베이션층, 본드 패드가 형성된 영역에서 반도체 다이를 관통하며, 단부에 반도체 다이의 제 2면으로 돌출되는 돌출부를 갖는 관통 전극, 돌출부를 덮도록 반도체 다이의 제 2면에 형성되는 금속층 및 금속층을 덮도록 반도체 다이의 제 2면에 형성되는 솔더를 포함한다.To this end, the semiconductor device of the present invention has a first surface formed flat and a second surface formed flat as an opposite surface of the first surface, and a semiconductor die having a plurality of bond pads on the first surface, the edges of the bond pads. A passivation layer formed on the first surface of the semiconductor die to cover, a through electrode having a protrusion extending through the semiconductor die in a region where the bond pad is formed, and protruding at the end thereof to the second surface of the semiconductor die; A metal layer formed on the second surface and a solder formed on the second surface of the semiconductor die to cover the metal layer.

Description

반도체 디바이스 및 그 제조 방법{SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF}Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF}

본 발명은 반도체 디바이스 및 그 제조 방법에 관한 것으로, 더욱 상세하게는 정밀한 반도체 다이 본딩 장비가 없더라도 실리콘 관통 전극을 갖는 반도체 다이가 용이하게 스택될 수 있는 반도체 디바이스 및 그 제조 방법에 관한 것이다.The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the semiconductor die having a silicon through electrode can be easily stacked even without precise semiconductor die bonding equipment.

현재 제품의 경박단소화 경향에 의해 제품에 들어가는 반도체 디바이스 역시 그 기능은 증가하고 크기는 작아질 것이 요구되고 있다. 이러한 요구를 만족시키기 위해 여러 반도체 디바이스의 패키징 기술이 개발되어 왔다.Due to the current trend toward thin and short products, semiconductor devices entering products are also required to increase in function and size. To meet these demands, packaging technologies for various semiconductor devices have been developed.

그리고 그 중 대표적인 하나가 반도체 다이의 본드 패드와 대응되는 영역에 반도체 다이를 관통하는 실리콘 관통 비아(Through Silicon Via, TSV)를 형성하고, 금속을 채워넣어 관통 전극을 형성하는 TSV 패키지이다. 이러한 패키지는 반도체 다이나 반도체 패키지 사이의 연결 길이를 짧게 할 수 있어서 고성능, 초소형의 반도체 패키지의 기술로 주목받고 있다.One representative example is a TSV package forming a through silicon via (TSV) through the semiconductor die in a region corresponding to the bond pad of the semiconductor die, and filling the metal to form a through electrode. Such a package has attracted attention as a technology of a high performance, ultra small semiconductor package because it can shorten the connection length between semiconductor dies and semiconductor packages.

또한, 관통 전극의 직경이 크면, 반도체 다이와 관통 전극의 재질이 다르므로 열팽창률(CTE : Coeffienct of Thermal Expansion)의 차이에 의한 스트레스가 발생하여 반도체 다이에 가해질 염려가 있다. 따라서, 관통 전극들의 폭이 한정될 수 밖에 없기 때문에 반도체 다이를 스택하고자 하는 경우, 스택되는 상하부 관통 전극들 간에 피치가 어긋나는 문제가 발생할 수 있다. 또한, 이러한 TSV 패키지 스택에서 불량을 줄이기 위해, 높은 정밀도의 반도체 다이 본딩 장비를 사용하면 비용이 많이 들게 되어 문제가 있다.In addition, when the diameter of the through electrode is large, the materials of the semiconductor die and the through electrode are different, so that stress due to a difference in the coefficient of thermal expansion (CTE) may occur and may be applied to the semiconductor die. Therefore, when the semiconductor die is to be stacked because the width of the through electrodes is limited, a pitch shift may occur between the stacked upper and lower through electrodes. In addition, in order to reduce defects in such a TSV package stack, the use of high precision semiconductor die bonding equipment is expensive and problematic.

본 발명은 상술한 종래의 문제점을 극복하기 위한 것으로서, 본 발명의 목적은 정밀한 반도체 다이 본딩 장비가 없더라도 실리콘 관통 전극을 갖는 반도체 다이가 용이하게 스택될 수 있는 반도체 디바이스 및 그 제조 방법에 관한 것이다.SUMMARY OF THE INVENTION The present invention has been made to overcome the above-mentioned conventional problems, and an object of the present invention relates to a semiconductor device and a method of manufacturing the semiconductor die having a silicon through electrode can be easily stacked even without precise semiconductor die bonding equipment.

상기한 목적을 달성하기 위해 본 발명에 따른 반도체 디바이스는 평평하게 형성된 제 1면 및 상기 제 1면의 반대면으로서 평평하게 형성된 제2면을 갖고, 제 1면에 다수의 본드 패드를 갖는 반도체 다이, 본드 패드의 에지를 덮도록 반도체 다이의 제 1면에 형성되는 패시베이션층, 본드 패드가 형성된 영역에서 반도체 다이를 관통하며, 단부에 반도체 다이의 제 2면으로 돌출되는 돌출부를 갖는 관통 전극, 돌출부를 덮도록 반도체 다이의 제 2면에 형성되는 금속층 및 금속층을 덮도록 반도체 다이의 제 2면에 형성되는 솔더를 포함할 수 있다.In order to achieve the above object, a semiconductor device according to the present invention has a first surface formed flat and a second surface formed flat as an opposite surface of the first surface, and a semiconductor die having a plurality of bond pads on the first surface. A passivation layer formed on the first surface of the semiconductor die so as to cover the edge of the bond pad, a through electrode having a protrusion extending through the semiconductor die in a region where the bond pad is formed and protruding to the second surface of the semiconductor die at the end thereof; It may include a metal layer formed on the second surface of the semiconductor die to cover and a solder formed on the second surface of the semiconductor die to cover the metal layer.

여기서, 관통 전극은 금, 은 및 구리 중에서 선택된 어느 하나 또는 이들의 조합으로 형성될 수 있다.Here, the through electrode may be formed of any one selected from gold, silver, and copper, or a combination thereof.

그리고 돌출부는 반도체 다이의 제 2면으로부터 제 2면에 수직한 방향으로 5㎛ 내지 50㎛로 돌출될 수 있다.The protrusion may protrude from 5 μm to 50 μm in a direction perpendicular to the second surface of the semiconductor die.

또한, 금속층은 상호간에 이격되어 배열될 수 있다.In addition, the metal layers may be arranged spaced apart from each other.

또한, 솔더는 상호간에 이격되어 형성될 수 있다.In addition, the solder may be formed spaced apart from each other.

또한, 관통 전극의 돌출부와 금속층 사이에는 UBM이 더 형성될 수 있다.In addition, a UBM may be further formed between the protrusion of the through electrode and the metal layer.

더불어 상기한 목적을 달성하기 위해 본 발명에 따른 반도체 디바이스는 평평하게 형성된 제 1면 및 제 1면의 반대면으로서 평평하게 형성된 제2면을 갖고, 제 1면에 다수의 본드 패드를 갖는 반도체 다이, 본드 패드의 에지를 덮으면서 반도체 다이의 제 1면에 형성되는 패시베이션층, 본드 패드가 형성된 영역에서 반도체 다이를 관통하며, 그 단부에 반도체 다이의 제 2면으로 돌출되는 돌출부를 갖는 관통 전극, 일단이 관통 전극의 돌출부를 덮고, 타단이 돌출부로부터 연장되어 반도체 다이의 제 2면에 형성되는 연장부를 갖는 UBM, UBM의 연장부를 제외한 영역을 덮으면서 반도체 다이의 제 2면에 형성되는 금속층 및 금속층을 덮으면서 UBM을 따라 접하도록 반도체 다이의 제 2면에 형성되는 솔더를 포함할 수 있다.In addition, in order to achieve the above object, the semiconductor device according to the present invention has a first surface formed flat and a second surface formed flat as an opposite surface of the first surface, and a semiconductor die having a plurality of bond pads on the first surface. A passivation layer formed on the first surface of the semiconductor die while covering the edge of the bond pad, a through electrode having a protrusion extending through the semiconductor die in a region where the bond pad is formed, and protruding to the second surface of the semiconductor die at an end thereof; A metal layer and a metal layer formed on the second surface of the semiconductor die, with one end covering the protrusion of the through electrode, the other end extending from the protrusion, and covering the area except the extension of the UBM having an extension formed on the second surface of the semiconductor die. It may include a solder formed on the second surface of the semiconductor die to contact along the UBM while covering.

여기서, UBM의 연장부는 반도체 다이의 제 2면에서 관통 전극에 수직한 일방향으로 배열될 수 있다.Here, the extension portion of the UBM may be arranged in one direction perpendicular to the through electrode on the second surface of the semiconductor die.

더불어 상기한 목적을 달성하기 위해 본 발명에 따른 반도체 디바이스의 제조 방법은 상부에 다수의 본드 패드를 갖고, 본드 패드가 형성된 영역에서 웨이퍼를 관통하는 관통 전극을 갖는 웨이퍼를 구비하는 웨이퍼 구비 단계, 웨이퍼의 하면을 식각하여 관통 전극의 단부인 돌출부가 노출되도록 하고, 제 1면 및 그 반대면인 제 2면을 갖는 반도체 다이를 구비하는 웨이퍼 백 에칭 단계, 돌출부를 덮도록 웨이퍼의 제 2면에 금속층을 형성하는 금속층 형성 단계 및 금속층을 덮도록 웨이퍼의 제 2면에 솔더를 형성하는 솔더 형성 단계를 포함할 수 있다.In addition, in order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a wafer providing step including a wafer having a plurality of bond pads thereon and a through electrode penetrating the wafer in a region where the bond pads are formed; Etching the lower surface of the wafer to expose the protrusion, which is an end of the through electrode, and having a semiconductor die having a first surface and a second surface that is opposite, a wafer back etching step; a metal layer on the second surface of the wafer to cover the protrusion And forming a solder layer on the second surface of the wafer to cover the metal layer.

여기서, 웨이퍼 백 에칭 단계는 관통 전극의 돌출부가 5㎛ 내지 50㎛로 노출되도록 웨이퍼의 제 2면을 식각하는 것일 수 있다.Here, the wafer back etching step may be to etch the second surface of the wafer so that the protrusion of the through electrode is exposed to 5 μm to 50 μm.

그리고 웨이퍼 백 에칭 단계는 건식 식각 방법으로 이루어질 수 있다.The wafer back etching step may be performed by a dry etching method.

또한, 웨이퍼 백 에칭 단계는 식각 가스로서 SF6 또는 CF4를 사용할 수 있다.In addition, the wafer back etching step may use SF 6 or CF 4 as an etching gas.

또한, 금속층 형성 단계는 돌출부의 주변에만 금속층을 형성하고, 금속층은 상호간에 이격되어 형성되도록 하는 것일 수 있다.In addition, the metal layer forming step may be to form a metal layer only on the periphery of the protrusion, the metal layer is formed spaced apart from each other.

또한, 금속층 형성 단계는 전해 도금 방법을 이용하여 이루어질 수 있다.In addition, the metal layer forming step may be performed using an electrolytic plating method.

또한, 금속층 형성 단계는 금속층을 금, 은, 구리 중에서 선택된 적어도 어느 하나 또는 이들의 조합으로 형성하는 것일 수 있다.In addition, the metal layer forming step may be to form a metal layer of at least one selected from gold, silver, copper or a combination thereof.

또한, 솔더 형성 단계는 금속층의 주변에만 솔더를 형성하고, 솔더를 상호간에 이격되도록 형성하는 것일 수 있다.In addition, the solder forming step may be to form a solder only on the periphery of the metal layer, and to form the solder to be spaced apart from each other.

또한, 솔더 형성 단계는 전해 도금 방법을 이용하여 이루어질 수 있다.In addition, the solder forming step may be performed using an electrolytic plating method.

또한, 솔더 형성 단계는 솔더를 주석으로 형성할 수 있다.In addition, the solder forming step may form the solder with tin.

더불어 상기한 목적을 달성하기 위해 본 발명에 따른 반도체 디바이스의 제조 방법은 상부면에 다수의 본드 패드를 갖고, 본드 패드가 형성된 영역에서 관통되는 관통 전극을 갖는 웨이퍼를 구비하는 웨이퍼 구비 단계, 웨이퍼의 하부면을 식각하여 관통 전극의 단부인 돌출부를 노출시키도록 하는 웨이퍼 백 에칭 단계, 관통 전극의 돌출부를 덮도록 웨이퍼의 하부면에 UBM층을 형성하는 UBM층 형성 단계, 웨이퍼의 하부면에 전면적으로 포토레지스트를 도포하는 포토레지스트 도포 단계, 포토레지스트를 노광하고 현상하여 포토레지스트에 패턴을 형성하는 포토레지스트 패턴 단계, 포토레지스트의 패턴에 금속을 채워넣어 돌출부를 덮는 금속층 및 솔더를 형성하는 금속층 및 솔더 형성 단계, 포토레지스트를 제거하는 포토레지스트 제거 단계 및 UBM층을 패턴하여 전기적으로 독립한 UBM을 형성하는 UBM층 식각 단계를 포함할 수 있다.In addition, in order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes a wafer providing step having a wafer having a plurality of bond pads on an upper surface and a through electrode penetrating through a region where the bond pads are formed; A wafer back etching step of etching the bottom surface to expose the protrusion, which is an end of the through electrode, a step of forming a UBM layer on the bottom surface of the wafer so as to cover the protrusion of the through electrode, and an entire surface of the bottom surface of the wafer A photoresist coating step of applying a photoresist, a photoresist pattern step of exposing and developing the photoresist to form a pattern in the photoresist, a metal layer covering the protrusion by filling a metal into the pattern of the photoresist, and a metal layer and solder forming a solder Formation step, photoresist removal step to remove photoresist and UBM layer Pattern may include a UBM layer etching step of forming a UBM electrically independent.

여기서, 금속층 및 솔더 형성 단계는 금속층을 전해 도금 방법을 이용하여 형성하는 것일 수 있다.Here, the metal layer and the solder forming step may be to form a metal layer using an electroplating method.

그리고 금속층 및 솔더 형성 단계는 솔더를 전해 도금 방법을 이용하여 형성하는 것일 수 있다.The metal layer and the solder forming step may be to form a solder using an electroplating method.

또한, 금속층 및 솔더 형성 단계는 UBM층을 시드층(seed layer)으로 하는 전해 도금 방법으로 이루어질 수 있다.In addition, the metal layer and the solder forming step may be performed by an electroplating method using the UBM layer as a seed layer.

또한, UBM층 식각 단계는 웨이퍼의 하부면을 따라 관통 전극의 돌출부로부터 일방향으로 연장되어 형성되는 연장부를 갖는 UBM을 형성하는 것일 수 있다.In addition, the UBM layer etching step may be to form a UBM having an extension which is formed extending in one direction from the protrusion of the through electrode along the lower surface of the wafer.

상기와 같이 하여 본 발명에 의한 반도체 디바이스 및 그 제조 방법은 관통 전극의 하부를 반도체 다이의 외부로 노출시키고, 그 노출된 부분에 금속층 또는 솔더를 도포하여 단면적을 증가시켜 고가의 반도체 다이 본딩 장비 없이도 관통 전극이 용이하게 정렬될 수 있도록 함으로써 반도체 다이 또는 반도체 디바이스를 용이하게 스택할 수 있다.As described above, the semiconductor device and the method of manufacturing the same according to the present invention expose the lower portion of the through electrode to the outside of the semiconductor die, and apply a metal layer or solder to the exposed portion to increase the cross-sectional area, thereby eliminating expensive semiconductor die bonding equipment. By allowing the through electrodes to be easily aligned, the semiconductor die or the semiconductor device can be easily stacked.

또한, 고가의 반도체 다이 본딩 장비를 사용하지 않아도 반도체 디바이스를 용이하게 스택(stack)할 수 있으므로, 반도체 디바이스의 제조 비용을 줄일 수 있다.In addition, since the semiconductor devices can be easily stacked without using expensive semiconductor die bonding equipment, manufacturing costs of the semiconductor devices can be reduced.

도 1a는 본 발명의 일 실시예에 따른 반도체 디바이스를 도시한 평면도이다.1A is a plan view illustrating a semiconductor device in accordance with an embodiment of the present invention.

도 1b는 본 발명의 일 실시예에 따른 반도체 디바이스를 스택한 구조를 도시한 평면도이다.1B is a plan view illustrating a stacked structure of semiconductor devices according to an embodiment of the present invention.

도 2a는 본 발명의 다른 실시예에 따른 반도체 디바이스를 도시한 평면도이다.2A is a plan view illustrating a semiconductor device in accordance with another embodiment of the present invention.

도 2b는 본 발명의 다른 실시예에 따른 반도체 디바이스를 스택한 구조를 도시한 평면도이다.2B is a plan view illustrating a stacked structure of semiconductor devices according to another embodiment of the present invention.

도 3a 본 발명의 또다른 실시예에 따른 반도체 디바이스를 도시한 평면도이다.3A is a plan view illustrating a semiconductor device according to another embodiment of the present invention.

도 3b는 본 발명의 또다른 실시예에 따른 반도체 디바이스를 스택한 구조를 도시한 평면도이다.3B is a plan view illustrating a stacked structure of semiconductor devices according to still another embodiment of the present invention.

도 4는 본 발명의 일 실시예에 따른 반도체 디바이스의 제조 방법을 설명하기 위한 플로우 챠트이다.4 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

도 5a 내지 도 5d는 본 발명의 일 실시예에 다른 반도체 디바이스의 제조 방법을 설명하기 위한 단면도이다.5A to 5D are cross-sectional views for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention.

도 6은 본 발명의 다른 실시예에 따른 반도체 디바이스의 제조 방법을 설명하기 위한 플로우 챠트이다.6 is a flowchart illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

도 7a 내지 도 7h는 본 발명의 다른 실시예에 따른 반도체 디바이스의 제조 방법을 설명하기 위한 단면도이다.7A to 7H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>

100,200,300; 본 발명의 실시예에 따른 반도체 디바이스100,200,300; Semiconductor device according to an embodiment of the present invention

1100,1200,1300; 본 발명의 실시예에 따른 반도체 디바이스의 스택된 구조1100,1200,1300; Stacked Structure of Semiconductor Device According to Embodiment of the Invention

110; 반도체 다이 120; 본드 패드110; Semiconductor die 120; Bond pad

130; 패시베이션층 140; 관통 전극130; Passivation layer 140; Through electrode

141; 돌출부 150,250,350; 금속층141; Protrusions 150,250,350; Metal layer

160,260,360; 솔더 245,345; UBM160,260,360; Solder 245,345; UBM

본 발명이 속하는 기술분야에 있어서 통상의 지식을 가진 자가 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present invention.

이하에서는 본 발명의 일 실시예에 따른 반도체 디바이스(100)의 구조를 설명하도록 한다.Hereinafter, the structure of the semiconductor device 100 according to an embodiment of the present invention will be described.

도 1a는 본 발명의 일 실시예에 따른 반도체 디바이스(100)의 구조를 도시한 단면도이다. 도 1b는 본 발명의 일 실시예 따른 반도체 디바이스(100)가 스택된 구조를 도시한 것이다.1A is a cross-sectional view illustrating a structure of a semiconductor device 100 according to an embodiment of the present invention. 1B illustrates a structure in which the semiconductor device 100 is stacked in accordance with an embodiment of the present invention.

도 1a 및 도 1b에 도시된 바와 같이, 본 발명의 일 실시예에 따른 반도체 디바이스(100)는 반도체 다이(110), 상기 반도체 다이(110)에 형성된 본드 패드(120), 상기 본드 패드(120)의 에지를 덮는 패시베이션층(130), 상기 반도체 다이(110)를 관통하는 관통 전극(140), 상기 관통 전극(140)의 하부에 구비되는 금속층(150), 상기 금속층(150)의 하부에 형성되는 솔더(160)를 포함할 수 있다.As shown in FIGS. 1A and 1B, a semiconductor device 100 according to an exemplary embodiment may include a semiconductor die 110, a bond pad 120 formed on the semiconductor die 110, and the bond pad 120. Passivation layer 130 covering the edge of the semiconductor layer 140, a penetrating electrode 140 penetrating through the semiconductor die 110, a metal layer 150 provided below the penetrating electrode 140, and a lower portion of the metal layer 150. It may include a solder 160 is formed.

상기 반도체 다이(110)는 대략 평평한 제 1면(110a) 및 상기 제 1면(110a)의 반대면으로서 대략 평평한 제 2면(110b)을 갖는다. 상기 반도체 다이(110)는 기본적으로 실리콘 재질로 구성되며 그 내부에 다수의 반도체 소자들이 형성되어 있다.The semiconductor die 110 has a substantially flat first surface 110a and a substantially flat second surface 110b as an opposite surface of the first surface 110a. The semiconductor die 110 is basically made of a silicon material, and a plurality of semiconductor elements are formed therein.

상기 본드 패드(120)는 상기 반도체 다이(110)의 제 1면(110a)에 다수 형성된다. 상기 본드 패드(120)는 상기 반도체 다이(110)의 내부로 형성될 수 있으나, 설명의 편의를 위해 외부로 돌출된 구조로 도시하였다. 상기 본드 패드(120)는 상기 반도체 다이(110)의 제 1면(110a) 중 가장 자리 또는 중앙 부분에 형성될 수 있다.The bond pads 120 are formed on the first surface 110a of the semiconductor die 110. The bond pad 120 may be formed inside the semiconductor die 110, but is illustrated as a structure protruding outward for convenience of description. The bond pad 120 may be formed at an edge or a center portion of the first surface 110a of the semiconductor die 110.

상기 패시베이션층(130)은 상기 반도체 다이(110)의 제 1면(110a)에 형성된다. 즉, 패시베이션층(130)은 상기 반도체 다이(110)의 제 1면(110a)을 덮도록 형성되며, 상기 반도체 다이(110)에 형성된 본드 패드(120)의 에지를 덮는다. 상기 패시베이션층(130)은 상기 본드 패드(120)의 외주연인 반도체 다이(110)의 제 1면(110a)을 보호하는 역할을 한다. 상기 패시베이션층(130)은 통상의 산화막, 질화막 및 폴리이미드 또는 그 등가물 중 선택된 어느 하나의 재질로 형성될 수 있으나, 본 발명의 내용을 상기 재질로서 한정하는 것은 아니다.The passivation layer 130 is formed on the first surface 110a of the semiconductor die 110. That is, the passivation layer 130 is formed to cover the first surface 110a of the semiconductor die 110, and covers the edge of the bond pad 120 formed on the semiconductor die 110. The passivation layer 130 protects the first surface 110a of the semiconductor die 110, which is an outer circumference of the bond pad 120. The passivation layer 130 may be formed of any one material selected from a common oxide film, a nitride film, a polyimide, or an equivalent thereof, but is not limited to the material of the present invention as the material.

상기 관통 전극(140)은 상기 본드 패드(120)를 관통하여 형성될 수 있다. 또한, 상기 관통 전극(140)은 상기 본드 패드(120)의 하부에 위치한 반도체 다이(110)를 관통하도록 형성된다. 즉, 상기 관통 전극(140)은 상기 본드 패드(120)로부터 상기 반도체 다이(110)의 제 2면(110b)에 이르는 전기적인 통로를 형성한다. 또한, 별도로 도시하지는 않았지만, 상기 반도체 다이(110)와 관통 전극(140)의 사이에는 절연체가 더 형성되어 반도체 다이(110)와 관통 전극(140) 사이의 열팽창 계수 차이에 따른 스트레스를 완화시킬 수도 있다.The through electrode 140 may be formed to penetrate through the bond pad 120. In addition, the through electrode 140 is formed to penetrate the semiconductor die 110 disposed under the bond pad 120. That is, the through electrode 140 forms an electrical passage from the bond pad 120 to the second surface 110b of the semiconductor die 110. In addition, although not separately illustrated, an insulator may be further formed between the semiconductor die 110 and the through electrode 140 to relieve stress due to a difference in thermal expansion coefficient between the semiconductor die 110 and the through electrode 140. have.

상기 관통 전극(140)은 그 단부에 상기 반도체 다이(110)의 제 2면(110b)으로 노출된 돌출부(141)를 갖는다. 상기 돌출부(141)는 공정 중 웨이퍼 상태인 반도체 다이의 하부를 식각하여 형성된다. 즉, 반도체 다이의 하부를 선택성이 있는 물질로 식각함으로써 상기 관통 전극(140)의 돌출부(141)만을 남길 수 있다.The through electrode 140 has a protrusion 141 exposed at the end thereof to the second surface 110b of the semiconductor die 110. The protrusion 141 is formed by etching a lower portion of the semiconductor die in a wafer state during the process. That is, only the protrusion 141 of the through electrode 140 may be left by etching the lower portion of the semiconductor die with a selective material.

상기 돌출부(141)의 길이(h)는 상기 반도체 다이(110)의 제 2면(110b)으로부터 5㎛ 내지 50㎛의 길이로 형성될 수 있다. 상기 돌출부(141)의 길이(h)가 5㎛ 미만인 경우, 이후 상기 돌출부(141)를 감싸는 상기 금속층(150) 및 솔더(160)의 구조를 형성하기 어렵다. 또한, 상기 돌출부(141)의 길이(h)가 50㎛를 초과하는 경우, 상기 돌출부(141)의 형성을 위한 식각 공정 시간이 과도하게 길어지고, 스택된 반도체 디바이스 간의 간격이 넓어지게 되어 반도체 디바이스의 경박단소화에 제약이 된다.The length h of the protrusion 141 may be formed to have a length of 5 μm to 50 μm from the second surface 110 b of the semiconductor die 110. When the length h of the protrusion 141 is less than 5 μm, it is difficult to form the structures of the metal layer 150 and the solder 160 surrounding the protrusion 141. In addition, when the length h of the protrusion 141 exceeds 50 μm, an etching process time for forming the protrusion 141 is excessively long, and a gap between stacked semiconductor devices is widened. It is a constraint on the light weight and shortness of.

상기 금속층(150)은 상기 관통 전극(140)의 돌출부(141)의 외주연에 형성된다. 즉, 상기 금속층(150)은 상기 반도체 다이(110)의 제 2면(110b)에 상기 돌출부(141)를 감싸도록 형성된다. 또한, 상기 금속층(150)은 상호간에 이격되도록 배열되어 각각 전기적으로 독립된다. 상기 금속층(150)은 전기적으로 전도성이 좋은 도체인 금속이며, 무전해 도금으로 형성될 수 있다. 상기 금속층(150)은 전기 전도도가 높은 금, 은, 구리 등일 수 있다.The metal layer 150 is formed on the outer circumference of the protrusion 141 of the through electrode 140. That is, the metal layer 150 is formed to surround the protrusion 141 on the second surface 110b of the semiconductor die 110. In addition, the metal layers 150 are arranged to be spaced apart from each other and are electrically independent of each other. The metal layer 150 is a metal that is a good conductor of electrical conductivity, and may be formed by electroless plating. The metal layer 150 may be gold, silver, copper, or the like having high electrical conductivity.

상기 솔더(160)는 상기 금속층(150)의 외주연에 형성된다. 그리고 상기 솔더(160)는 상기 반도체 다이(110)의 제 2면(110b)에 상기 금속층(150)을 감싸도록 형성된다. 상기 솔더(160)도 역시 상호간에 이격되도록 배열되므로 각각 전기적으로 독립될 수 있다. 상기 솔더(160)는 반도체 디바이스(100)에 솔더볼이 부착되거나 또는 반도체 디바이스(100)가 스택되는 경우 결합력을 증가시킨다. 상기 솔더(160)는 주석을 이용하여 형성될 수 있고, 상기 솔더(160)를 형성하는 방법으로는 무전해 주석 도금이 가능하다.The solder 160 is formed on the outer circumference of the metal layer 150. The solder 160 is formed to surround the metal layer 150 on the second surface 110b of the semiconductor die 110. The solder 160 is also arranged so as to be spaced apart from each other, so that each may be electrically independent. The solder 160 increases the bonding force when the solder ball is attached to the semiconductor device 100 or the semiconductor devices 100 are stacked. The solder 160 may be formed using tin, and the solder 160 may be electroless tin plated as a method of forming the solder 160.

도 1b에 도시되어 있듯이, 본 발명의 일 실시예에 따른 스택된 반도체 디바이스(1100)는 상기 반도체 다이(110)의 제 2면(110b)을 마주보게 하여 반도체 디바이스(100)를 스택함으로써 형성될 수 있다. 이 경우, 상기 솔더(160)가 접하면서 두 개의 반도체 디바이스(100)가 스택된다. 또한, 상기 관통 전극(140)의 돌출부(141)에 비해 상기 솔더(160)의 단면적이 더 넓으므로 정밀한 반도체 다이 본딩 장치가 없더라도 반도체 다이(110) 또는 본 발명의 일 실시예에 따른 반도체 디바이스(100)가 용이하게 스택될 수 있다.As shown in FIG. 1B, a stacked semiconductor device 1100 according to an embodiment of the present invention may be formed by stacking the semiconductor device 100 so as to face the second surface 110b of the semiconductor die 110. Can be. In this case, two semiconductor devices 100 are stacked while the solder 160 is in contact. In addition, since the cross-sectional area of the solder 160 is larger than that of the protrusion 141 of the through electrode 140, the semiconductor die 110 or the semiconductor device according to the embodiment of the present invention may be manufactured even without a precise semiconductor die bonding apparatus. 100 can be easily stacked.

상기와 같이 하여, 본 발명의 일 실시예에 따른 반도체 디바이스(100)는 반도체 다이(110)의 제 2면(110b)을 통해 돌출되는 관통 전극(140)의 돌출부(141)를 구비하고, 상기 돌출부(141)의 외주연에 금속층(150)과 솔더(160)를 더 형성한다. 따라서, 상기 관통 전극(140)과 전기적으로 연결되는 부분의 단면적이 넓어지게 되므로, 정밀한 반도체 다이 본딩 장치가 없더라도 반도체 디바이스(100)를 용이하게 스택할 수 있다. 또한, 정밀한 반도체 다이 본딩 장치는 고가이기 때문에 본 발명의 일 실시예에 따른 반도체 디바이스(100)는 이러한 고가 장비를 사용하지 않아도 되므로 그 제조 비용을 줄일 수 있다.As described above, the semiconductor device 100 according to the exemplary embodiment of the present invention includes a protrusion 141 of the through electrode 140 protruding through the second surface 110b of the semiconductor die 110. The metal layer 150 and the solder 160 are further formed on the outer circumference of the protrusion 141. Therefore, since the cross-sectional area of the portion electrically connected to the through electrode 140 is widened, the semiconductor device 100 can be easily stacked even without a precise semiconductor die bonding apparatus. In addition, since the precise semiconductor die bonding apparatus is expensive, the semiconductor device 100 according to the exemplary embodiment of the present invention does not need to use such expensive equipment, and thus the manufacturing cost thereof can be reduced.

이하에서는 본 발명의 다른 실시예에 따른 반도체 디바이스(200)의 구조를 설명하도록 한다.Hereinafter, the structure of the semiconductor device 200 according to another embodiment of the present invention will be described.

도 2a를 참조하면, 본 발명의 다른 실시예에 따른 반도체 디바이스(200)가 단면도로서 도시되어 있다. 도 2b를 참조하면, 본 발명의 다른 실시예에 따른 반도체 디바이스(200)가 스택된 구조가 도시되어 있다. 동일한 구성 및 작용을 갖는 부분에 대해서는 동일한 도면 부호를 붙였으며, 이하에서는 앞서 설명한 실시예와의 차이점을 위주로 설명하도록 한다.2A, a semiconductor device 200 in accordance with another embodiment of the present invention is shown in cross section. Referring to FIG. 2B, a structure in which a semiconductor device 200 is stacked in accordance with another embodiment of the present invention is illustrated. Parts having the same configuration and action have been given the same reference numerals, and will be described below with reference to differences from the above-described embodiment.

도 2a 및 도 2b에 도시된 바와 같이, 본 발명의 다른 실시예에 따른 반도체 디바이스(200)는 반도체 다이(110), 본드 패드(120), 패시베이션층(130), 돌출부(141)를 갖는 관통 전극(140), 상기 돌출부(141)의 외주연에 형성된 UBM(245), 상기 UBM(245)의 외주연에 형성된 금속층(250), 상기 금속층(250)의 외주연에 형성된 솔더(260)를 포함할 수 있다.As shown in FIGS. 2A and 2B, a semiconductor device 200 according to another embodiment of the present invention has a through-hole having a semiconductor die 110, a bond pad 120, a passivation layer 130, and a protrusion 141. The electrode 140, the UBM 245 formed on the outer periphery of the protrusion 141, the metal layer 250 formed on the outer periphery of the UBM 245, and the solder 260 formed on the outer periphery of the metal layer 250. It may include.

상기 UBM(Under Bump Metal, 245)(이하, UBM이라 한다)은 상기 관통 전극(140)의 돌출부(141)의 외주연에 형성된다. 즉, 상기 UBM(245)은 상기 반도체 다이(110)의 제 2면(110b)에 상기 관통 전극(140)의 돌출부(141)를 감싸도록 형성된다. 상기 UBM(245)은 상기 관통 전극(140)과 상기 금속층(250)을 용이하게 결합하도록 한다. 상기 UBM(245)은 도면에 하나의 층으로 도시되어 있지만, 크롬/크롬-구리 합금/구리, 티타늄-텅스텐 합금/구리 또는 알루미늄/니켈/구리 등의 다층으로 구성될 수 있다. The under bump metal 245 (hereinafter, referred to as UBM) is formed at the outer circumference of the protrusion 141 of the through electrode 140. That is, the UBM 245 is formed to surround the protrusion 141 of the through electrode 140 on the second surface 110b of the semiconductor die 110. The UBM 245 facilitates coupling the through electrode 140 and the metal layer 250. The UBM 245 is shown as one layer in the figure, but may be composed of multiple layers such as chromium / chromium-copper alloy / copper, titanium-tungsten alloy / copper or aluminum / nickel / copper.

또한, 상기 UBM(245)은 상기 금속층(250) 및 솔더(260)가 형성되기 위한 시드층(seed layer)의 역할을 할 수 있다. 상기 금속층(250)과 솔더(260)를 형성하기 위해 전기 도금 공정이 이용될 수 있고, 이 경우 상기 UBM은 반도체 다이(110)의 전면에 도포되어 전류가 흐르는 경로를 제공하여 상기 금속층(250) 및 솔더(260)가 도금될 수 있도록 한다.In addition, the UBM 245 may serve as a seed layer for forming the metal layer 250 and the solder 260. An electroplating process may be used to form the metal layer 250 and the solder 260, in which case the UBM is applied to the entire surface of the semiconductor die 110 to provide a path through which current flows. And solder 260 to be plated.

상기 금속층(250)은 상기 UBM(245)의 외주연에 형성된다. 상기 금속층(250)은 상기 반도체 다이(110)의 제 2면(110b)에 상기 UBM(245)을 감싸도록 형성된다. 상기 금속층(250)은 내부에 상기 UBM(245)을 감싸면서 형성되는 것을 제외하고는 앞에서 설명한 반도체 디바이스(100)의 금속층(150)과 동일하다.The metal layer 250 is formed on the outer circumference of the UBM 245. The metal layer 250 is formed to surround the UBM 245 on the second surface 110b of the semiconductor die 110. The metal layer 250 is the same as the metal layer 150 of the semiconductor device 100 described above, except that the metal layer 250 is formed to surround the UBM 245 therein.

상기 솔더(260)는 상기 금속층(250)의 하부에 형성된다. 상기 솔더(260)는 상기 금속층(250)의 하면을 감싼다. 다만, 상기 솔더(260)는 상기 금속층(250)을 감싸도록 상기 금속층(250)의 외주연에 형성될 수도 있다. 즉, 도 2b에 도시된 바와 같이, 상기 솔더(260)는 상기 금속층(250)의 외부에 형성된다. 그리고 반도체 디바이스(100)를 스택하여 스택된 반도체 디바이스(1200)를 형성할 때, 상기 솔더(260)가 용융되어 스택을 용이하게 돕는다.The solder 260 is formed under the metal layer 250. The solder 260 surrounds the bottom surface of the metal layer 250. However, the solder 260 may be formed on the outer circumference of the metal layer 250 to surround the metal layer 250. That is, as shown in FIG. 2B, the solder 260 is formed outside the metal layer 250. And when stacking the semiconductor device 100 to form a stacked semiconductor device 1200, the solder 260 is melted to facilitate the stack.

상기와 같이 하여, 본 발명의 다른 실시예에 따른 반도체 디바이스(200)는 관통 전극(140)의 돌출부(141)를 감싸는 UBM(245), 금속층(250), 솔더(260)를 형성한다. 따라서 정밀한 반도체 다이 본딩 장치가 없어도 반도체 디바이스(200)가 용이하게 스택될 수 있다. 또한, 그 결과 반도체 디바이스(200)의 제조 단가를 낮출 수 있다.As described above, the semiconductor device 200 according to another exemplary embodiment of the present invention forms the UBM 245, the metal layer 250, and the solder 260 that surround the protrusion 141 of the through electrode 140. Therefore, the semiconductor device 200 can be easily stacked without the precise semiconductor die bonding apparatus. As a result, the manufacturing cost of the semiconductor device 200 can be lowered.

이하에서는 본 발명의 또다른 실시예에 따른 반도체 디바이스(300)의 구성에 대해 설명하도록 한다.Hereinafter, the configuration of the semiconductor device 300 according to another embodiment of the present invention will be described.

도 3a는 본 발명의 또다른 실시예에 따른 반도체 디바이스(300)의 구성을 나타낸 단면도이다. 도 3b는 본 발명의 또다른 실시예에 따른 반도체 디바이스(300)가 스택된 구성을 나타낸 단면도이다. 동일한 구성 및 작용을 갖는 부분에 대해서는 동일한 도면 부호를 붙였으며, 이하에서는 앞서 설명한 실시예들과의 차이점을 위주로 설명하도록 한다.3A is a cross-sectional view illustrating a configuration of a semiconductor device 300 according to still another embodiment of the present invention. 3B is a cross-sectional view illustrating a stacked structure of a semiconductor device 300 according to another exemplary embodiment of the present invention. Parts having the same configuration and action have been given the same reference numerals, and will be described below with focus on differences from the above-described embodiments.

도 3a 및 도 3b에 도시된 바와 같이, 본 발명의 또다른 실시예에 따른 반도체 디바이스(300)는 반도체 다이(110), 본드 패드(120), 패시베이션층(130), 관통 전극(140), 상기 관통 전극(140)의 돌출부(141)의 외주연을 감싸는 UBM(345), 상기 UBM(345)의 일부를 감싸는 금속층(350), 상기 금속층(350)의 하부에 형성되는 솔더(360)를 포함할 수 있다.As shown in FIGS. 3A and 3B, a semiconductor device 300 according to another embodiment of the present invention may include a semiconductor die 110, a bond pad 120, a passivation layer 130, a through electrode 140, A UBM 345 surrounding the outer circumference of the protrusion 141 of the through electrode 140, a metal layer 350 covering a portion of the UBM 345, and a solder 360 formed under the metal layer 350. It may include.

상기 UBM(345)은 상기 관통 전극(140)의 돌출부(141)의 외주연을 감싸면서 형성된다. 상기 UBM(345)은 그 단부에 상기 반도체 다이(110)의 제 2면(110b)을 따라 연장되어 형성된 연장부(345a)를 포함한다. 또한, 상기 UBM(345)은 상기 반도체 다이(110)의 제 2면(110b)에서 다수개로 형성되며 같은 방향으로 정렬되고 상호간에 접하지 않도록 배열되어 각자 전기적으로 독립될 수 있다.The UBM 345 is formed while surrounding the outer circumference of the protrusion 141 of the through electrode 140. The UBM 345 includes an extension 345a formed at an end thereof extending along the second surface 110b of the semiconductor die 110. In addition, the UBMs 345 may be formed in plural on the second surface 110b of the semiconductor die 110 and arranged in the same direction and not arranged to be in contact with each other, and may be electrically independent of each other.

도 3b에 도시되어 있듯이, 본 발명의 또다른 실시예에 따른 반도체 디바이스(300)가 스택되어 형성된 스택된 반도체 디바이스(1300)의 경우, 상기 연장부(345a)에 스택되는 다른 반도체 디바이스의 솔더(360)가 결합될 수 있다. 즉, 반도체 디바이스(300)가 스택되는 경우 솔더(360)를 상호간에 정렬시켜서 연결하지 않더라도, 솔더(360)가 다른 반도체 디바이스(300)의 연장부(345a)에 연결되도록 지그재그로 배열할 수 있다. 또한, 상기 연장부(345a)의 연장된 길이는 상기 솔더(360)의 폭보다도 길게 형성될 수 있으므로 반도체 디바이스(300)의 스택시 솔더(360)를 정렬하던 구조에 비해 상대적으로 정밀도가 낮게 요구된다. 따라서, 본 발명의 또다른 실시예에 따른 반도체 디바이스(300)는 고가의 정밀한 반도체 다이 본딩 장치 없이도 반도체 디바이스(300)를 용이하게 스택할 수 있고, 반도체 디바이스(300)를 스택하는 공정에서의 단가를 낮출 수 있다. 더불어, 상기 솔더(360)가 서로 엇갈려서 스택되므로 전체적인 반도체 디바이스(300)의 높이를 줄일 수 있다.As shown in FIG. 3B, in the case of the stacked semiconductor device 1300 in which the semiconductor device 300 is stacked according to another embodiment of the present invention, solder of another semiconductor device stacked on the extension part 345a may be used. 360 may be combined. That is, when the semiconductor devices 300 are stacked, the solders 360 may be arranged in a zigzag manner so that the solders 360 may be connected to the extension portions 345a of the other semiconductor devices 300 even though the solders 360 are not aligned with each other. . In addition, since the extended length of the extension portion 345a may be longer than the width of the solder 360, the precision of the extension portion 345a may be lower than that of the structure in which the solder 360 is aligned when the semiconductor device 300 is stacked. do. Therefore, the semiconductor device 300 according to another embodiment of the present invention can easily stack the semiconductor device 300 without the expensive and precise semiconductor die bonding apparatus, and the unit cost in the process of stacking the semiconductor device 300. Can be lowered. In addition, since the solder 360 is stacked alternately, the height of the entire semiconductor device 300 may be reduced.

상기 금속층(350)은 상기 UBM(345)의 상기 연장부(345a)를 제외한 영역을 감싸면서 형성된다. 이점을 제외하면, 상기 금속층(350)은 앞서 설명한 실시예에서의 금속층(150)과 동일하다.The metal layer 350 is formed to surround an area except the extension part 345a of the UBM 345. Except for this, the metal layer 350 is the same as the metal layer 150 in the above-described embodiment.

상기 솔더(360)는 상기 금속층(350)의 하부에 형성된다. 도 3b에 도시된 바와 같이, 상기 솔더(360)는 반도체 디바이스(300)가 스택될 때 다른 반도체 디바이스의 상기 UBM(345)의 연장부(345a)에 연결될 수 있다. 상기 솔더(360)는 그 외에는 앞서 설명한 실시예에서의 솔더(360)와 동일하다.The solder 360 is formed under the metal layer 350. As shown in FIG. 3B, the solder 360 may be connected to an extension 345a of the UBM 345 of another semiconductor device when the semiconductor device 300 is stacked. The solder 360 is otherwise identical to the solder 360 in the above-described embodiment.

상기와 같이 하여, 본 발명의 또다른 실시예에 따른 반도체 디바이스(300)는 UBM(345)의 단부에 연장부(345a)를 구비한다. 따라서, 반도체 디바이스(300)가 지그재그로 배열됨으로써 용이하게 스택될 수 있고, 스택된 전체적인 반도체 디바이스(300)의 높이를 줄일 수 있다. 그리고 정밀한 반도체 다이 본딩 장치가 요구되지 않으므로 반도체 디바이스의 스택시에 그 제조 단가를 낮출 수 있다.As described above, the semiconductor device 300 according to another embodiment of the present invention includes an extension 345a at the end of the UBM 345. Accordingly, the semiconductor devices 300 can be easily stacked by being arranged in a zigzag, and the height of the stacked whole semiconductor devices 300 can be reduced. And since a precise semiconductor die bonding apparatus is not required, the manufacturing cost can be reduced at the time of stacking a semiconductor device.

이하에서는 본 발명의 일 실시예에 따른 반도체 디바이스(100)의 제조 방법에 대해 설명하도록 한다.Hereinafter, a method of manufacturing the semiconductor device 100 according to an embodiment of the present invention will be described.

도 4는 본 발명의 일 실시예에 따른 반도체 디바이스(100)의 제조 방법을 설명하기 위한 플로우 챠트이다. 도 5a 내지 도 5d는 본 발명의 일 실시예에 따른 반도체 디바이스(100)의 제조 방법을 설명하기 위한 단면도이다.4 is a flowchart illustrating a method of manufacturing the semiconductor device 100 according to an embodiment of the present invention. 5A through 5D are cross-sectional views illustrating a method of manufacturing the semiconductor device 100 in accordance with an embodiment of the present invention.

도 4를 참조하면, 본 발명의 일 실시예에 따른 반도체 디바이스(100)는 웨이퍼 구비 단계(S1), 웨이퍼 백 에칭 단계(S2), 금속층 형성 단계(S3), 솔더 형성 단계(S4)를 포함할 수 있다. 이하에서는 도 4의 각 단계들을 도 5a 내지 도 5d를 참조하여 설명하도록 한다.Referring to FIG. 4, the semiconductor device 100 according to an embodiment of the present invention includes a wafer provision step S1, a wafer back etching step S2, a metal layer formation step S3, and a solder formation step S4. can do. Hereinafter, each step of FIG. 4 will be described with reference to FIGS. 5A to 5D.

도 4 및 도 5a에 도시된 바와 같이, 우선 상부에 다수의 본드 패드(120)를 갖고, 상기 본드 패드(120)를 관통하는 관통 전극(140)이 형성된 웨이퍼(110')를 구비하는 웨이퍼 구비 단계(S1)가 이루어진다. 상기 관통 전극(140)은 상기 본드 패드(120) 및 상기 웨이퍼(110')를 관통하도록 형성된다.As shown in FIGS. 4 and 5A, a wafer having a plurality of bond pads 120 thereon and a wafer 110 ′ having a through electrode 140 penetrating through the bond pads 120 are provided. Step S1 is made. The through electrode 140 is formed to penetrate the bond pad 120 and the wafer 110 ′.

도 4 및 도 5b에 도시된 바와 같이, 이후 상기 웨이퍼(110')의 하부를 식각하여 상기 관통 전극(140)의 단부인 노출부(141)가 노출되도록 하는 웨이퍼 백 에칭 단계(S2)가 이루어진다. 상기 웨이퍼 백 에칭 단계(S2)는 상기 웨이퍼(110')의 하부를 건식 식각함으로써 이루어질 수 있다. 이 때, 건식 식각을 위한 기체로는 선택성이 좋은 SF6 가스 또는 CF4 가스가 이용될 수 있다.As shown in FIG. 4 and FIG. 5B, a wafer back etching step S2 is performed to etch the lower portion of the wafer 110 ′ so that the exposed portion 141, which is an end of the through electrode 140, is exposed. . The wafer back etching step S2 may be performed by dry etching a lower portion of the wafer 110 ′. In this case, SF 6 gas or CF 4 gas having good selectivity may be used as a gas for dry etching.

또한, 상술한 바와 같이 상기 관통 전극(140)의 노출부(141)는 백 에칭 되어 형성된 상기 웨이퍼(110')의 하부면으로부터 5㎛ 내지 50㎛의 길이를 가지면서 노출될 수 있다.In addition, as described above, the exposed portion 141 of the through electrode 140 may be exposed while having a length of 5 μm to 50 μm from the bottom surface of the wafer 110 ′ formed by back etching.

도 4 및 도 5c에 도시된 바와 같이, 이후 상기 관통 전극(140)의 노출부(141)를 금속층(150)으로 감싸는 금속층 형성 단계(S3)가 이루어진다. 상기 금속층(150)은 금, 은, 구리 등일 수 있다. 또한, 상기 금속층(150)은 무전해 도금 방법을 이용하여 형성될 수 있다. 그리고, 상기 금속층(150)은 상호간에 이격되어 배열되므로 각자 전기적으로 독립될 수 있다.As shown in FIG. 4 and FIG. 5C, a metal layer forming step S3 is formed to surround the exposed portion 141 of the through electrode 140 with the metal layer 150. The metal layer 150 may be gold, silver, copper, or the like. In addition, the metal layer 150 may be formed using an electroless plating method. In addition, since the metal layers 150 are arranged to be spaced apart from each other, they may be electrically independent of each other.

도 4 및 도 5d에 도시된 바와 같이, 이후 상기 금속층(150)을 솔더(160)로 감싸는 솔더 형성 단계(S4)가 이루어진다. 상기 솔더(160)는 주석일 수 있다. 또한, 상기 솔더(160)는 무전해 주석 도금 방법을 이용하여 형성될 수 있다.As shown in FIG. 4 and FIG. 5D, a solder forming step S4 is formed to surround the metal layer 150 with the solder 160. The solder 160 may be tin. In addition, the solder 160 may be formed using an electroless tin plating method.

그리고 별도로 도시하지 않았지만, 이후 블레이드를 통해 상기 웨이퍼(110')를 낱개로 소잉(sawing)하여 본 발명의 일 실시예에 사용되는 반도체 다이(110)가 형성될 수 있다. 상기와 같이 하여 본 발명의 일 실시예에 따른 반도체 디바이스(100)가 제조될 수 있다. 또한, 별도로 도시하지 않았지만 상기 솔더(160)를 접합하도록 하여, 두 개의 반도체 디바이스(100)가 스택되는 것이 가능하다.Although not shown separately, the semiconductor die 110 used in the exemplary embodiment of the present invention may be formed by sawing the wafers 110 'individually through the blades. As described above, the semiconductor device 100 according to the exemplary embodiment may be manufactured. In addition, although not separately illustrated, two semiconductor devices 100 may be stacked by bonding the solder 160.

이하에서는 본 발명의 다른 실시예에 따른 반도체 디바이스(200)의 제조 방법에 대해 설명하도록 한다.Hereinafter, a method of manufacturing the semiconductor device 200 according to another embodiment of the present invention will be described.

도 6은 본 발명의 다른 실시예에 따른 반도체 디바이스(200)의 제조 방법을 설명하기 위한 플로우 챠트이다. 도 7a 내지 도 7h는 본 발명의 다른 실시예에 따른 반도체 디바이스(200)의 제조 방법을 설명하기 위한 단면도이다. 동일한 구성 및 작용을 갖는 부분에 대해서는 동일한 도면 부호를 붙였으며, 이하에서는 앞선 실시예와의 차이점을 위주로 설명하도록 한다.6 is a flowchart illustrating a method of manufacturing the semiconductor device 200 according to another embodiment of the present invention. 7A to 7H are cross-sectional views illustrating a method of manufacturing the semiconductor device 200 in accordance with another embodiment of the present invention. Parts having the same configuration and action have been given the same reference numerals, and will be described below with emphasis on differences from the foregoing embodiments.

도 6을 참조하면, 본 발명의 다른 실시예에 따른 반도체 디바이스(200)의 제조 방법은 웨이퍼 구비 단계(S1), 웨이퍼 백 에칭 단계(S2), UBM 형성 단계(S3), 포토레지스트 도포 단계(S4), 포토레지스트 패턴 단계(S5), 금속층 및 솔더 형성 단계(S6), 포토레지스트 제거 단계(S7), UBM 식각 단계(S8)를 포함하여 형성될 수 있다. 이하에서는 도 6의 각 단계들을 도 7a 내지 도 7h를 참조하여 설명하도록 한다.Referring to FIG. 6, a method of manufacturing a semiconductor device 200 according to another embodiment of the present invention may include a wafer providing step S1, a wafer back etching step S2, a UBM forming step S3, and a photoresist coating step ( S4), the photoresist pattern step S5, the metal layer and the solder forming step S6, the photoresist removing step S7, and the UBM etching step S8 may be formed. Hereinafter, each step of FIG. 6 will be described with reference to FIGS. 7A to 7H.

도 6 및 도 7a에 도시된 바와 같이, 먼저 상부에 다수의 본드 패드(120)를 갖고, 상기 본드 패드(120)를 관통하는 관통 전극(140)을 갖는 웨이퍼(110')가 구비되는 웨이퍼 구비 단계(S1)가 이루어진다. 상기 관통 전극(140)은 상기 웨이퍼(110') 및 본드 패드(120)를 모두 관통하도록 구비된다.As shown in FIGS. 6 and 7A, a wafer having a plurality of bond pads 120 thereon and a wafer 110 ′ having a through electrode 140 penetrating through the bond pads 120 are provided. Step S1 is made. The through electrode 140 is provided to penetrate both the wafer 110 ′ and the bond pad 120.

도 6 및 도 7b에 도시된 바와 같이, 이후 웨이퍼(110')의 하부를 식각하여 관통 전극(140)의 돌출부(141)가 노출되도록 하는 웨이퍼 백 에칭 단계(S2)가 이루어진다. 상기 관통 전극(140)의 돌출부(141)는 상기 웨이퍼(110')의 하부면으로부터 5㎛ 내지 50㎛의 높이로 돌출될 수 있다. 상기 웨이퍼 백 에칭 단계(S2)는 상기 웨이퍼(110')의 하부를 SF6 가스 또는 CF4 가스를 이용하여 건식 식각함으로써 이루어질 수 있다.6 and 7B, a wafer back etching step S2 is performed to etch the lower portion of the wafer 110 ′ to expose the protrusion 141 of the through electrode 140. The protrusion 141 of the through electrode 140 may protrude from a bottom surface of the wafer 110 ′ to a height of 5 μm to 50 μm. The wafer back etching step S2 may be performed by dry etching a lower portion of the wafer 110 ′ using SF 6 gas or CF 4 gas.

도 6 및 도 7c에 도시된 바와 같이, 이후 상기 웨이퍼(110')의 하부면에 전체적으로 UBM층(245')이 도포되는 UBM층 형성 단계(S3)가 이루어진다. 상기 UBM층(245')은 상기 관통 전극(140)의 돌출부(141)와 이후 형성되는 금속층(250) 사이에 결합이 용이하도록 하기 위해 형성된다. 또한, 상기 UBM층(245')은 상기 금속층(250)의 형성을 위한 시드층(seed layer)의 역할을 할 수 있다. 즉, 상기 UBM층(245')을 이용하여 이후에 상기 금속층(250)이 전해 도금으로 형성될 수 있다.As shown in FIGS. 6 and 7C, a UBM layer forming step S3 is performed in which a UBM layer 245 ′ is applied to the entire bottom surface of the wafer 110 ′. The UBM layer 245 ′ is formed to facilitate coupling between the protrusion 141 of the through electrode 140 and the metal layer 250 formed thereafter. In addition, the UBM layer 245 ′ may serve as a seed layer for forming the metal layer 250. That is, the metal layer 250 may be formed by electroplating after using the UBM layer 245 ′.

도 6 및 도 7d에 도시된 바와 같이, 이후 상기 UBM층(245')의 하부에 전면적으로 포토레지스트(10)를 도포하는 포토레지스트 도포 단계(S4)가 이루어진다. 상기 포토레지스트(10)는 빛의 조사 유무에 따라 경화될 수 있다.As shown in FIG. 6 and FIG. 7D, a photoresist coating step S4 is performed to apply the photoresist 10 to the entire surface of the UBM layer 245 ′. The photoresist 10 may be cured according to the presence or absence of light irradiation.

도 6 및 도 7e에 도시된 바와 같이, 이후 상기 포토레지스트(10)에 노광 및 현상 공정을 수행하여 패턴된 포토레지스트(10')를 형성하는 포토레지스트 패턴 단계(S5)가 이루어진다. 상기 패턴된 포토레지스트(10')는 이후에 금속층(250)과 솔더(260)가 형성될 영역을 제외한 영역에만 남도록 형성된다. 따라서, 상기 금속층(250)과 솔더(260)는 패턴된 포토레지스트(10')의 패턴들 사이에 형성될 수 있다.As shown in FIGS. 6 and 7E, a photoresist pattern step S5 is performed to form a patterned photoresist 10 'by performing an exposure and development process on the photoresist 10. The patterned photoresist 10 ′ is formed so as to remain only in the region except for the region where the metal layer 250 and the solder 260 are to be formed later. Thus, the metal layer 250 and the solder 260 may be formed between the patterns of the patterned photoresist 10 ′.

도 6 및 도 7f에 도시된 바와 같이, 이후 상기 패턴된 포토레지스트(10')의 패턴 사이에 금속층(250)과 솔더(260)를 형성하는 금속층 및 솔더 형성 단계(S6)가 이루어진다. 상기 금속층(250)은 상기 패턴된 포토레지스트(10')의 사이에 전해 도금의 방법으로 형성될 수 있다. 또한, 상기 금속층(250)은 금, 은, 구리 등으로 형성될 수 있고, 상기 UBM층(245')을 시드층(seed layer)으로 하여 전해 도금 방법으로 형성될 수 있다. 상기 솔더(260)는 상기 금속층(250)의 하부에 형성될 수 있다. 또한, 상기 솔더(260)는 주석일 수 있으며, 역시 전해 도금 방법에 의해 형성될 수 있다.As shown in FIGS. 6 and 7F, a metal layer and a solder forming step S6 are formed to form a metal layer 250 and a solder 260 between the patterns of the patterned photoresist 10 ′. The metal layer 250 may be formed by electroplating between the patterned photoresist 10 ′. In addition, the metal layer 250 may be formed of gold, silver, copper, or the like, and may be formed by an electroplating method using the UBM layer 245 ′ as a seed layer. The solder 260 may be formed under the metal layer 250. In addition, the solder 260 may be tin and may also be formed by an electroplating method.

도 6 및 도 7g에 도시된 바와 같이, 이후 상기 패턴된 포토레지스트(10')를 제거하는 포토레지스트 제거 단계(S7)가 이루어진다. 상기 패턴된 포토 레지스트(10')를 제거하는 방법으로는 에싱(ashing) 방법이 이용될 수 있다.As shown in FIGS. 6 and 7G, a photoresist removal step S7 is then performed to remove the patterned photoresist 10 ′. An ashing method may be used to remove the patterned photoresist 10 '.

도 6 및 도 7h에 도시된 바와 같이, 이후 UBM층(245')을 식각하여 UBM(245)을 형성하는 UBM층 식각 단계(S8)가 이루어진다. 식각 전의 상기 UBM층(245')은 관통 전극(140)의 돌출부(141)를 모두 감싸면서 상기 반도체 다이(110)의 제 2면(110b) 전체에 형성되어 있으므로, 상기 UBM층(245')에 의해 상기 관통 전극(140)들이 전기적으로 단락될 수 있다. 따라서 상기 UBM층(245')을 식각하여 패턴된 형태의 UBM(245)을 형성함으로써, 각 관통 전극(140)들이 전기적으로 독립될 수 있도록 한다.As shown in FIGS. 6 and 7H, the UBM layer etching step S8 is performed to etch the UBM layer 245 ′ to form the UBM 245. Since the UBM layer 245 ′ before etching is formed on the entirety of the second surface 110 b of the semiconductor die 110 while covering all of the protrusions 141 of the through electrode 140, the UBM layer 245 ′. The through electrodes 140 may be electrically shorted by each other. Accordingly, the UBM layer 245 'is etched to form a patterned UBM 245 so that each through electrode 140 can be electrically independent.

또한, 블레이드를 통해 상기 웨이퍼(110')를 소잉(sawing)함으로써 반도체 다이(110)를 형성할 수 있고, 결과적으로 본 발명의 다른 실시예에 따른 반도체 디바이스(200)를 제조할 수 있다. 또한, 별도로 도시하지는 않았지만, 반도체 디바이스(200)의 솔더(260)간에 접합하도록 하여 반도체 디바이스(200)를 스택하는 것이 가능하다.In addition, the semiconductor die 110 may be formed by sawing the wafer 110 'through a blade, and as a result, the semiconductor device 200 may be manufactured according to another embodiment of the present invention. In addition, although not separately illustrated, the semiconductor device 200 may be stacked by bonding the solder 260 of the semiconductor device 200 to each other.

Claims (23)

평평하게 형성된 제 1면 및 상기 제 1면의 반대면으로서 평평하게 형성된 제2면을 갖고, 상기 제 1면에 다수의 본드 패드를 갖는 반도체 다이;A semiconductor die having a first surface formed flat and a second surface formed flat as an opposite surface to the first surface, the semiconductor die having a plurality of bond pads on the first surface; 상기 본드 패드의 에지를 덮도록 상기 반도체 다이의 제 1면에 형성되는 패시베이션층;A passivation layer formed on the first surface of the semiconductor die to cover an edge of the bond pad; 상기 본드 패드가 형성된 영역에서 상기 반도체 다이를 관통하며, 단부에 상기 반도체 다이의 제 2면으로 돌출되는 돌출부를 갖는 관통 전극;A through electrode penetrating the semiconductor die in a region where the bond pad is formed and having a protrusion at an end thereof protruding to the second surface of the semiconductor die; 상기 돌출부를 덮도록 상기 반도체 다이의 제 2면에 형성되는 금속층; 및A metal layer formed on a second surface of the semiconductor die to cover the protrusion; And 상기 금속층을 덮도록 상기 반도체 다이의 제 2면에 형성되는 솔더를 포함하고, 상기 관통 전극의 돌출부와 상기 금속층 사이에는 UBM이 더 형성된 것을 특징으로 하는 반도체 디바이스.And a solder formed on the second surface of the semiconductor die to cover the metal layer, wherein a UBM is further formed between the protrusion of the through electrode and the metal layer. 제 1항에 있어서,The method of claim 1, 상기 관통 전극은 금, 은 및 구리 중에서 선택된 어느 하나 또는 이들의 조합으로 형성되는 것을 특징으로 하는 반도체 디바이스.And the through electrode is formed of any one or a combination of gold, silver and copper. 제 1항에 있어서,The method of claim 1, 상기 돌출부는 상기 반도체 다이의 제 2면으로부터 상기 제 2면에 수직한 방향으로 5㎛ 내지 50㎛로 돌출되어 있는 것을 특징으로 하는 반도체 디바이스.And the projecting portion protrudes from 5 탆 to 50 탆 in a direction perpendicular to the second surface from the second surface of the semiconductor die. 제 1항에 있어서,The method of claim 1, 상기 금속층은 상호간에 이격되어 배열된 것을 특징으로 하는 반도체 디바이스.And the metal layers are spaced apart from each other. 제 1항에 있어서,The method of claim 1, 상기 솔더는 상호간에 이격되어 형성되는 것을 특징으로 하는 반도체 디바이스.And the solders are formed spaced apart from each other. 삭제delete 평평하게 형성된 제 1면 및 상기 제 1면의 반대면으로서 평평하게 형성된 제2면을 갖고, 상기 제 1면에 다수의 본드 패드를 갖는 반도체 다이;A semiconductor die having a first surface formed flat and a second surface formed flat as an opposite surface to the first surface, the semiconductor die having a plurality of bond pads on the first surface; 상기 본드 패드의 에지를 덮으면서 상기 반도체 다이의 제 1면에 형성되는 패시베이션층;A passivation layer formed on the first surface of the semiconductor die while covering an edge of the bond pad; 상기 본드 패드가 형성된 영역에서 상기 반도체 다이를 관통하며, 그 단부에 상기 반도체 다이의 제 2면으로 돌출되는 돌출부를 갖는 관통 전극;A through electrode penetrating the semiconductor die in a region where the bond pad is formed and having a protrusion at an end thereof protruding to the second surface of the semiconductor die; 일단이 상기 관통 전극의 돌출부를 덮고, 타단이 상기 돌출부로부터 연장되어 상기 반도체 다이의 제 2면에 형성되는 연장부를 갖는 UBM;An UBM having one end covering the protrusion of the through electrode and the other end extending from the protrusion to be formed on the second surface of the semiconductor die; 상기 UBM의 상기 연장부를 제외한 영역을 덮으면서 상기 반도체 다이의 제 2면에 형성되는 금속층; 및A metal layer formed on a second surface of the semiconductor die while covering an area except the extension portion of the UBM; And 상기 금속층을 덮으면서 상기 UBM을 따라 접하도록 상기 반도체 다이의 제 2면에 형성되는 솔더를 포함하는 것을 특징으로 하는 반도체 디바이스.And a solder formed on the second surface of the semiconductor die to be in contact with the UBM while covering the metal layer. 제 7항에 있어서,The method of claim 7, wherein 상기 UBM의 연장부는 상기 반도체 다이의 제 2면에서 상기 관통 전극에 수직한 일방향으로 배열되는 것을 특징으로 하는 반도체 디바이스.And an extension of the UBM is arranged in one direction perpendicular to the through electrode on the second surface of the semiconductor die. 상부에 다수의 본드 패드를 갖고, 상기 본드 패드가 형성된 영역에서 상기 웨이퍼를 관통하는 관통 전극을 갖는 웨이퍼를 구비하는 웨이퍼 구비 단계;Providing a wafer having a plurality of bond pads thereon and having a through electrode penetrating through the wafer in a region where the bond pads are formed; 상기 웨이퍼의 하면을 식각하여 상기 관통 전극의 단부인 돌출부가 노출되도록 하고, 제 1면 및 그 반대면인 제 2면을 갖는 반도체 다이를 구비하는 웨이퍼 백 에칭 단계;Etching a lower surface of the wafer to expose a protrusion, which is an end of the through electrode, and having a semiconductor die having a first surface and a second surface opposite to the wafer; 상기 돌출부를 덮도록 상기 웨이퍼의 제 2면에 금속층을 형성하는 금속층 형성 단계; 및A metal layer forming step of forming a metal layer on a second surface of the wafer to cover the protrusion; And 상기 금속층을 덮도록 상기 웨이퍼의 제 2면에 솔더를 형성하는 솔더 형성 단계를 포함하는 것을 특징으로 하는 반도체 디바이스의 제조 방법.And forming a solder on the second surface of the wafer to cover the metal layer. 제 9항에 있어서,The method of claim 9, 상기 웨이퍼 백 에칭 단계는 상기 관통 전극의 돌출부가 5㎛ 내지 50㎛로 노출되도록 상기 웨이퍼의 제 2면을 식각하는 것을 특징으로 하는 반도체 디바이스의 제조 방법.And the wafer back etching step etches the second surface of the wafer such that the protrusion of the through electrode is exposed to 5 μm to 50 μm. 제 9항에 있어서,The method of claim 9, 상기 웨이퍼 백 에칭 단계는 건식 식각 방법으로 이루어지는 것을 특징으로하는 반도체 디바이스의 제조 방법.And said wafer back etching step comprises a dry etching method. 제 9항에 있어서,The method of claim 9, 상기 웨이퍼 백 에칭 단계는 식각 가스로서 SF6 또는 CF4를 사용하는 것을 특징으로 하는 반도체 디바이스의 제조 방법.And the wafer back etching step uses SF 6 or CF 4 as an etching gas. 제 9항에 있어서,The method of claim 9, 상기 금속층 형성 단계는 상기 돌출부의 주변에만 상기 금속층을 형성하고, 상기 금속층은 상호간에 이격되어 형성되도록 하는 것을 특징으로 하는 반도체 디바이스의 제조 방법.In the forming of the metal layer, the metal layer is formed only around the protrusions, and the metal layers are formed to be spaced apart from each other. 제 9항에 있어서,The method of claim 9, 상기 금속층 형성 단계는 전해 도금 방법을 이용하여 이루어지는 것을 특징으로 하는 반도체 디바이스의 제조 방법.The metal layer forming step is performed using an electrolytic plating method. 제 9항에 있어서,The method of claim 9, 상기 금속층 형성 단계는 상기 금속층을 금, 은, 구리 중에서 선택된 적어도 어느 하나 또는 이들의 조합으로 형성하는 것을 특징으로 하는 반도체 디바이스의 제조 방법.In the metal layer forming step, the metal layer is formed of at least one selected from gold, silver, and copper, or a combination thereof. 제 9항에 있어서,The method of claim 9, 상기 솔더 형성 단계는 상기 금속층의 주변에만 상기 솔더를 형성하고, 상기 솔더를 상호간에 이격되도록 형성하는 것을 특징으로 하는 반도체 디바이스의 제조 방법.In the solder forming step, the solder is formed only around the metal layer, and the solder is formed so as to be spaced apart from each other. 제 9항에 있어서,The method of claim 9, 상기 솔더 형성 단계는 전해 도금 방법을 이용하여 이루어지는 것을 특징으로 하는 반도체 디바이스의 제조 방법.The solder forming step is performed using an electrolytic plating method. 제 9항에 있어서,The method of claim 9, 상기 솔더 형성 단계는 상기 솔더를 주석으로 형성하는 것을 특징으로 하는 반도체 디바이스의 제조 방법.And wherein said solder forming step forms said solder with tin. 상부면에 다수의 본드 패드를 갖고, 상기 본드 패드가 형성된 영역에서 관통되는 관통 전극을 갖는 웨이퍼를 구비하는 웨이퍼 구비 단계;Providing a wafer having a plurality of bond pads on an upper surface, the wafer having a through electrode penetrating through a region where the bond pads are formed; 상기 웨이퍼의 하부면을 식각하여 상기 관통 전극의 단부인 돌출부를 노출시키도록 하는 웨이퍼 백 에칭 단계;A wafer back etching step of etching the lower surface of the wafer to expose the protrusion which is an end of the through electrode; 상기 관통 전극의 돌출부를 덮도록 상기 웨이퍼의 하부면에 UBM층을 형성하는 UBM층 형성 단계;Forming a UBM layer on the bottom surface of the wafer so as to cover the protrusion of the through electrode; 상기 웨이퍼의 하부면에 전면적으로 포토레지스트를 도포하는 포토레지스트 도포 단계;A photoresist coating step of applying photoresist on the entire bottom surface of the wafer; 상기 포토레지스트를 노광하고 현상하여 포토레지스트에 패턴을 형성하는 포토레지스트 패턴 단계;A photoresist pattern step of exposing and developing the photoresist to form a pattern in the photoresist; 상기 포토레지스트의 패턴에 금속을 채워넣어 상기 돌출부를 덮는 금속층 및 솔더를 형성하는 금속층 및 솔더 형성 단계;A metal layer and a solder forming step of forming a metal layer and a solder to fill the pattern of the photoresist to cover the protrusions; 상기 포토레지스트를 제거하는 포토레지스트 제거 단계; 및A photoresist removing step of removing the photoresist; And 상기 UBM층을 패턴하여 전기적으로 독립한 UBM을 형성하는 UBM층 식각 단계를 포함하는 것을 특징으로 하는 반도체 디바이스의 제조 방법.And etching the UBM layer to form an electrically independent UBM by patterning the UBM layer. 제 19항에 있어서,The method of claim 19, 상기 금속층 및 솔더 형성 단계는 상기 금속층을 전해 도금 방법을 이용하여 형성하는 것을 특징으로 하는 반도체 디바이스의 제조 방법.And said metal layer and solder forming step form said metal layer using an electroplating method. 제 19항에 있어서,The method of claim 19, 상기 금속층 및 솔더 형성 단계는 상기 솔더를 전해 도금 방법을 이용하여 형성하는 것을 특징으로 하는 반도체 디바이스의 제조 방법.The metal layer and the solder forming step is to form the solder using an electroplating method of manufacturing a semiconductor device. 제 19항에 있어서,The method of claim 19, 상기 금속층 및 솔더 형성 단계는 상기 UBM층을 시드층(seed layer)으로 하는 전해 도금 방법으로 이루어지는 것을 특징으로 하는 반도체 디바이스의 제조 방법.And said metal layer and solder forming step are made by an electroplating method using said UBM layer as a seed layer. 제 19항에 있어서,The method of claim 19, 상기 UBM층 식각 단계는 상기 웨이퍼의 하부면을 따라 상기 관통 전극의 돌출부로부터 일방향으로 연장되어 형성되는 연장부를 갖는 UBM을 형성하는 것을 특징으로 하는 반도체 디바이스의 제조 방법.And etching the UBM layer to form an UBM having an extension part extending in one direction from the protrusion of the through electrode along the lower surface of the wafer.
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US9082764B2 (en) 2012-03-05 2015-07-14 Corning Incorporated Three-dimensional integrated circuit which incorporates a glass interposer and method for fabricating the same

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JP2001210667A (en) * 2000-01-28 2001-08-03 New Japan Radio Co Ltd Manufacturing method for semiconductor device
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JP2001210667A (en) * 2000-01-28 2001-08-03 New Japan Radio Co Ltd Manufacturing method for semiconductor device
JP2003100802A (en) * 2001-09-25 2003-04-04 Kyocera Corp Wiring board

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9082764B2 (en) 2012-03-05 2015-07-14 Corning Incorporated Three-dimensional integrated circuit which incorporates a glass interposer and method for fabricating the same

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