KR100913797B1 - CMOS image sensor - Google Patents

Abstract

The present invention relates to a CMOS image sensor, and discloses a technique for improving sensing sensitivity by adding or averaging pixels of the same color in an analog domain. To this end, the present invention provides a pixel array including a plurality of unit pixels arranged in a matrix, a row driver for selecting a row line of the pixel array, and fixed pattern noise of the plurality of unit pixels. A plurality of CDS circuits for removing a plurality of pixels, a plurality of ADCs for combining pixel information of unit pixels having the same color among the plurality of unit pixels, and converting analog image signals output from the plurality of CDS circuits into digital image signals; A plurality of line memories for storing the digital image signals output from the ADC, and a column decoder for decoding the address signals in the column direction and outputting the image information stored in the plurality of line memories.

Image Sensors, CDS, ADCs, Pixels, Switches

Description

CMOS image sensor {Complementary Metal-Oxide Semiconductor image sensor}

1 is a block diagram showing a general CMOS image sensor.

2 illustrates another embodiment of a general CMOS image sensor.

3 is a block diagram showing a CMOS image sensor according to the present invention.

4 is a circuit diagram illustrating a unit pixel, a correlated double sampling (CDS) circuit, and an analog digital converter (ADC) in FIG. 3.

5 is a circuit diagram schematically showing the CDS circuit and the ADC of FIG.

6 is an operation timing diagram of a CMOS image sensor according to the present invention;

7 is another embodiment of a CMOS image sensor in accordance with the present invention.

FIG. 8 is a circuit diagram illustrating a unit pixel, a CDS circuit, and an ADC of FIG. 7.

9 is a circuit diagram schematically showing the CDS circuit and ADC of FIG.

<Explanation of symbols for main parts of the drawings>

200: pixel array

210: unit pixels

220: roo driver

230: CDS (Correlated Double Sampling) Circuit

240: ADC (Analog-Digital Converter)

250: analog control block

260: line memory

270: Timing Generator

280; Column decoder

The present invention relates to a complementary metal oxide semiconductor (CMOS) image sensor, and is a technology for improving sensing sensitivity by adding or averaging pixels of the same color in an analog domain.

In general, an image sensor is a device that converts an external optical image signal into an electrical image signal. Image sensors are largely divided into CMOS image sensors using complementary-MOS (CMOS) technology and CCD image sensors using Charge Coupled Device (CCD) technology, all of which are manufactured using semiconductor technology.

In particular, CMOS image sensors are image sensors fabricated using CMOS fabrication techniques. Each pixel in the CMOS image sensor converts the light signal radiated from the corresponding part of the subject into electrons using a photodiode and stores it, and then converts the amount of charge that appears in proportion to the number of accumulated electrons into a voltage signal and outputs the voltage signal. Use

Such a CMOS image sensor is a device widely used in various electronic products, for example, a mobile phone, a camera for a personal computer (PC), a video camera, a digital camera, and the like.

The CMOS image sensor is simpler to drive than the CCD used as an image sensor, and it is possible to integrate a signal processing circuit into one chip so that a system on chip (SoC) can be used to make the module smaller. Let's do it. In addition, since the conventional set-up (CMOS) technology can be used interchangeably, there are many advantages such as lowering the manufacturing cost, so the demand is increasing rapidly.

Recently, CMOS image sensors are using smaller and smaller pixels in high resolution sensors to meet market demands for cheaper and better image quality. By the way, a small pixel means a small photodiode, and a small photodiode means that the amount of light that is acceptable is limited.

That is, limiting the amount of light that is acceptable means that the number of electrons generated and absorbed by the light is reduced, and thus there is a problem in that a limit in generating a good image is obtained.

In order to solve this problem, a shared pixel structure that increases the area of a photodiode is relatively widely used by sharing a transistor used in a CMOS image sensor pixel with neighboring pixels. This shared pixel structure increases the image quality by increasing the size of the photodiode and increasing the number of acceptable electrons in pixels of the same size.

However, as the parasitic capacitance of the floating diffusion node increases when the structure of the shared pixel is used, sensitivity deterioration may occur due to the reduction of the conversion gain, and the arrangement of the photodiodes is asymmetric, rather There are disadvantages that can degrade image quality.

1 is a block diagram illustrating a general full mode image sensor that reads out all pixel information.

Typical image sensors include a pixel array (10), a row driver (20), a read out circuit (30), an analog control block (40), a line memory (50), and a TG. (Timing Generator 60) and Column Decoder (70).

Here, the pixel array 10 includes a plurality of unit pixels 11 arranged in a matrix in the row and column directions. The row driver 20 selects a row line of the pixel array 10.

The readout circuit 30 may include a plurality of correlated double sampling (CDS) circuits and a plurality of analog to digital converters (ADCs). The CDS circuit eliminates fixed pattern noise of the unit pixel 11. The ADC converts the analog video signal output from the corresponding CDS circuit into a digital video signal.

The analog control block 40 also controls the operation of the readout circuit 30. Each line memory 50 stores image information of a column line corresponding to the pixel array 10. Here, each line memory 50 may be composed of two latches for sequentially storing pixel information of two row lines.

In addition, the TG 60 represents a timing generator, and generates a timing required for the operation of the sensor and supplies the generated timing to each block. That is, the TG 60 generates a supply signal for the row driver 20, the analog control block 40, and the column decoder 70.

In addition, the column decoder 70 decodes the address signal in the column direction and outputs pixel information stored in the line memory 50.

In a typical image sensor having such a configuration, one CDS circuit, an ADC, and one line memory 50 are connected through one column bus per unit pixel 11. Accordingly, information of all the pixel arrays 10 is read and transferred to the readout circuit 30, and the information is stored in the line memory 50.

FIG. 2 is a diagram illustrating a conventional sub sampling mode image sensor that reads out information of a pixel and reads it out (1 × 2 sub sampling mode read out).

The image sensor includes a pixel array 100, a row driver 120, a read out circuit 130, an analog control block 140, a line memory 150, a TG 160, and a column decoder 170.

Here, the pixel array 100 includes a plurality of unit pixels 110 arranged in a matrix in the row and column directions. The row driver 120 selects a row line of the pixel array 100.

The readout circuit 130 includes a plurality of correlated double sampling (CDS) circuits and a plurality of analog to digital converters (ADCs). The CDS circuit eliminates fixed pattern noise of the unit pixel 110.

In general, CMOS image sensors use CDS circuits to eliminate the reset noise component that occurs at the pixel when the signal charge is read out. The CDS circuit reads the voltage during the pixel reset operation, stores the signal charge, reads the signal level, and outputs the difference.

The ADC converts the analog video signal output from the corresponding CDS circuit into a digital video signal. In addition, the analog control block 140 controls the operation of the readout circuit 130.

Each line memory 150 stores image information of a column line corresponding to the pixel array 110. Here, each line memory 150 may be composed of two latches for sequentially storing pixel information of two row lines.

In addition, the TG 160 represents a timing generator, and generates and supplies a timing necessary for the operation of the sensor. That is, the TG 160 generates the supply signals required for the row driver 120, the analog control block 140, and the column decoder 170.

In addition, the column decoder 170 decodes the address signal in the column direction and outputs pixel information stored in the line memory 150.

In a typical image sensor having such a configuration, one CDS circuit, an ADC, and one line memory 150 are connected through one column bus per unit pixel 110. In the sub-sampling mode, all pixel information is not read out, but some pixel information is sampled to read out the corresponding pixel information, and some pixel information is not read out. Do not.

As a result, the time taken to read out the pixel information is reduced, thereby increasing the frame rate. However, in the sub-sampling mode, the information of some pixels is skipped and the image quality is lower than that of reading out the information of all the pixels.

In addition, the conventional image sensor may bin the color in the charge domain of the pixel. However, in this case, the conversion gain is lowered due to the increase in floating diffusion capacitance and parasitical capacitance.

The present invention was created to solve the above problems, and can implement sub-sampling by adding or averaging pixels of the same color in an analog domain to perform analog-to-digital conversion (ADC). The purpose is to make it.

The present invention is to reduce the time required to read out the information of the pixel while reading the information of all the pixels in the sub-sampling mode and add or average the pixels of the same color to improve the sensing sensitivity. have.

According to an aspect of the present invention, a CMOS image sensor includes: a pixel array including a plurality of unit pixels arranged in a matrix; A row driver for selecting row lines of the pixel array; A plurality of CDS circuits for removing fixed pattern noise of a plurality of unit pixels; A plurality of ADCs for adding pixel information of unit pixels having the same color among a plurality of unit pixels, and converting analog image signals output from a plurality of CDS circuits into digital image signals; A plurality of line memories for storing digital image signals output from the plurality of ADCs; And a column decoder for decoding the address signal in the column direction and outputting image information stored in a plurality of line memories.

In addition, the present invention provides a pixel array including a plurality of unit pixels arranged in a matrix; A row driver for selecting row lines of the pixel array; A plurality of CDS circuits for removing fixed pattern noise of a plurality of unit pixels and averaging pixel information of unit pixels having the same color among the plurality of unit pixels; A plurality of ADCs for converting analog video signals output from a plurality of CDS circuits into digital video signals; A plurality of line memories for storing digital image signals output from the plurality of ADCs; And a column decoder for decoding the address signal in the column direction and outputting image information stored in a plurality of line memories.

In addition, the present invention includes a first unit pixel for storing the first pixel information; A second unit pixel for storing second pixel information having the same color as the first pixel information; A first switch for selectively supplying an output of the first unit pixel; A second switch for selectively supplying an output of a second unit pixel; A first capacitor for discharging the output voltage of the first switch; A second capacitor for discharging the output voltage of the second switch; A third capacitor for storing a signal voltage applied from the first switch; A fourth capacitor for storing a signal voltage applied from the second switch; And an amplifier comparing the output of the third capacitor with the output of the fourth capacitor and outputting a corresponding digital value.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a CMOS image sensor of the present invention. In the present invention, a case where the information of the pixel is sampled and read out in a 1 × 2 sub sampling mode will be described as an embodiment.

The present invention relates to a pixel array 200, a row driver 220, a correlated double sampling (CDS) circuit 230, an analog to digital converter 240, an analog control block An analog control block 250, a line memory 260, a timing generator 270, and a column decoder 280.

Here, the pixel array 200 includes a plurality of unit pixels 210 arranged in a matrix in the row and column directions. The row driver 220 selects a row line of the pixel array 200.

The CDS circuit 230 removes fixed pattern noise of the unit pixel 210. The ADC 240 converts the analog video signal output from the corresponding CDS circuit 230 into a digital video signal.

The analog control block 250 also controls the operation of the CDS circuit 230 and the ADC 240. Each line memory 260 stores image information of a column line corresponding to the pixel array 200. Here, each line memory 260 may be composed of two latches for sequentially storing pixel information of two row lines.

In addition, the TG 270 represents a timing generator, and generates a timing required for the operation of the sensor and supplies the generated timing to each block. That is, the TG 270 generates a supply signal for the row driver 220, the analog control block 250, and the column decoder 280.

In addition, the column decoder 280 decodes the address signal in the column direction and outputs pixel information stored in the line memory 260.

In the image sensor of the present invention having such a configuration, information of all the pixel arrays 200 is read out so that color pixel information is summed through the CDS circuit 230 and the ADC 240. The color information summed by the CDS circuit 230 and the ADC 240 is stored in the line memory 260 via the ADC 240.

Referring to the operation of the present invention having such a configuration as follows.

In the pixel array 200 of FIG. 3, color pixels in the order of R, Gr, R, Gr ... are listed in the first row line, and Gb, B, Gb, B .. Assume that the sequence of color pixels is listed.

In the conventional structure of FIG. 2, pixel information read in the first and second column lines of the pixel array is read out through the column decoder through the CDS circuit and the ADC. The pixel information of the third and fourth column lines is skipped without reading out.

That is, R, Gr pixels of the first and second column lines are read out on one row line, and R, GR of the third and fourth column lines are skipped, and the next row line In the same way, the pixel is read out.

However, in the present invention, all the unit pixels 210 of the pixel array 200 are read out. That is, after the pixel information of all the pixel arrays 200 is transferred to the CDS circuit 230 and the ADC 240, pixels of the same color are added by an analog binning operation.

And, after analog-to-digital conversion in one amplifier A through the CDS circuit 230, the digital data is stored in the line memory 260. Thereafter, the digital data value stored in the line memory 260 is transferred to the image signal processing (ISP) at a later stage through the column decoder 280.

Here, the ISP corrects the difference between the image signal detected by the CMOS image sensor and the image signal to be displayed on the screen (gamma correction), and inputs a pixel for insufficient color among the gamma corrected image signals. To convert the complete image data.

4 is a detailed circuit diagram illustrating the pixel array 200, the correlated double sampling (CDS) circuit 230, and the ADC 240 of FIG. 3. According to the exemplary embodiment of the present invention, the unit pixel 210 of the pixel array 200 has a 4TR structure.

Each unit pixel 210 includes a photodiode PD, a reset transistor T1, a transfer transistor T2, a driving transistor T3, and a selection transistor T4.

Here, the photodiode PD is connected between the transfer transistor T2 and the ground voltage terminal to generate a photocharge corresponding to the optical image of the subject. The reset transistor T1 is connected between the supply voltage VDD applying stage and the floating diffusion node FD. This reset transistor T1 discharges the charge stored in the floating diffusion node FD in response to the reset signal RT for detection of the next image information.

Then, the transfer transistor T2 is connected between the floating diffusion node FD and the photodiode PD, and transmits the photocharge generated in the photodiode PD to the floating diffusion node FD in response to the transmission signal TX.

The driving transistor T3 is connected between the supply voltage VDD applying terminal and the selection transistor T4 to serve as a source follower. In addition, the selection transistor T4 is connected between the driving transistor T3 and the pixel information output terminal, and may perform addressing by switching in response to the selection signal LS.

The unit pixel 210 having such a configuration outputs pixel information P0_Gr0 through the unit pixel 210_1 and outputs pixel information P0_R0 through the unit pixel 210_2. The pixel information P0_Gr1 is output through the unit pixel 210_3, and the pixel information P0_R1 is output through the unit pixel 210_4.

On the other hand, the CDS circuit 230_1 includes a switch SW1 and capacitors Ch1 and Cs1. The CDS circuit 230_2 includes a switch SW2 and capacitors Ch2 and Cs2. The CDS circuit 230_3 includes a switch SW3 and capacitors Ch3, Cs3. CDS circuit 230_4 includes switch SW4 and capacitors Ch4, Cs4.

Here, the array of unit pixels 210_1 to 210_4 and the CDS circuits 230_1 to 230_4 are formed in one-to-one correspondence, and the number thereof is the same. In the exemplary embodiment of the present invention, for the convenience of description, four unit pixels 210_1 to 210_4 and four CDS circuits 230_1 to 230_4 are provided. However, the present invention is not limited thereto. The number is not limited.

The switches SW1 to SW4 selectively connect the unit pixel 210 and the CDS circuit 230. The switches SW1 and SW3 connected to the odd column are driven by the same control switch, and the switches SW2 and SW4 connected to the even column are driven by another control switch. The number of switches SW1 to SW4 increases with the number of pixel arrays. In addition, when the switches SW1 to SW4 are turned on, pixel information of the unit pixel 210 is transmitted to the CDS circuit 230.

The capacitors Ch1 to Ch4 are connected between the switches SW1 to SW4 and the ground voltage terminal, respectively, to discharge the signal voltages applied from the switches SW1 to SW4. In addition, capacitors Cs1 to Cs4 are connected between the switches SW1 to SW4 and the negative input terminals of the amplifiers A1 to A4, respectively. The capacitors Cs1 to Cs4 store the sensing voltage of the unit pixel 210 applied through the switches SW1 to SW4.

Here, the sizes of the capacitors Ch1 to Ch4 are all the same, and the sizes of the capacitors Cs1 to Cs4 are all set the same.

In addition, ADC 240_1 includes switches SS1, S1, SW5, and amplifier A1. ADC 240_2 includes switches SS2, S2, SW6 and amplifier A2. ADC 240_3 includes switches S3, SW7 and amplifier A3. ADC 240_4 includes switches S4, SW8 and amplifier A4.

Switches SW5 and SW7 connected to odd columns are connected and driven by switches SS1, and switches SW6 and SW8 connected to even columns are connected and driven by other switches SS2. The switches SW5 and SW7 connected to the odd columns are connected and driven by the same control switch, and the switches SW6 and SW8 connected to the even columns are connected and driven by another control switch.

Here, the switch SS1 connects the positive input terminal of the amplifier A1 and the negative input terminal of the amplifier A3 in the unit pixels 210_1 and 210_3 having the same color. The switch SS2 connects the positive input terminal of the amplifier A2 and the negative input terminal of the amplifier A4 in the unit pixels 210_2 and 210_4 having the same color.

In addition, the switches S1 to S4 allow the voltage VRAMP to be selectively supplied or cut off. Here, one switch S1 to S4 is provided in each column line, and its driving is controlled at the same timing.

The switches SS1, SS2, S1 to S4 operate only in the 1 × 2 subsampling mode. In the full mode, which reads out all pixel information, the switches SS1 and SS2 are always in the OFF state. , Switches S1 ~ S4 are always turned on.

In the present invention, one switch SS1 is provided per two columns (eg, odd columns) and one switch SS2 is provided per two columns (eg, even columns).

FIG. 5 is a circuit diagram schematically illustrating a correlated double sampling (CDS) circuit 230 and an ADC 240 of FIG. 4. In the present invention, one switch S1 is included in two unit pixels 210_1 and 210_3, and one amplifier A1 is connected. In addition, one switch S2 is included in the two unit pixels 210_2 and 210_4, and one amplifier A2 is connected.

In FIG. 5, a case in which the pixel information of the unit pixels 210_1 and 210_3 having the green color are added together will be described as an exemplary embodiment.

Assume that the switch SS1 connecting the unit pixels 210_1 and 210_3 having the green color is turned on. In this case, the node NDB which is the negative terminal of the amplifier A1 is connected to the unit pixel 210_1, and the node NDA which is the positive terminal is connected to the unit pixel 210_3.

The amplifier A1 receives and compares pixel information P0_Gr0 and P0_Gr1 applied from the nodes NDB and NDA, and outputs corresponding digital values.

In the present invention, a case in which two unit pixel information having the same color is added is described as an embodiment. However, the present invention is not limited thereto, and in some cases, at least two unit pixel information may be summed through a switching element. .

An operation process of the present invention having such a configuration will be described below with reference to the operation timing diagram of FIG. 6.

First, it is assumed that there are four column lines and four unit pixels 210_1 to 210_4 in one row line as shown in FIG. 4. In this case, the unit pixels 210_1 to 210_4 in the four column lines are sequentially arranged to read signals in the order of Green, Red, Green, Red, and the like. That is, each unit pixel 210_1 to 210_4 outputs pixel information P0_Gr0, P0_R0, P0_Gr1, and P0_R1.

The unit pixels 210_1 and 210_3 that output the green information are connected through the switch SS1. In this case, the positive terminal (+) of the amplifier A1 in the unit pixel 210_1 and the negative (−) terminal of the amplifier A3 in the unit pixel 210_3 are connected to each other through the switch SS1.

On the other hand, unit pixels 210_2 and 210_4 that output red information are connected through the switch SS2. At this time, the positive terminal (+) of the amplifier A2 in the unit pixel 210_2 and the negative terminal (-) of the amplifier A4 in the unit pixel 210_4 are connected to each other through the switch SS2.

In the present invention, a case in which there are four column lines is described as an embodiment. However, the present invention is not limited thereto, and the four column lines may be repeatedly formed in succession so that the pixel and the column lines are connected to the entire array. have.

In addition, in the present invention, the switches SS1 and SS2 are always turned on in the 1 × 2 sub sampling mode.

In addition, when the selection signal LS is activated to perform signal sampling in the interval 1, the selection transistor T4 is turned on. In this state, the reset transistor T1 is turned on when the reset signal RT is activated. Accordingly, the charge stored in the floating diffusion node FD is discharged to lead the reset voltage.

Then, while the switch S1 is turned on, the switches SW1 and SW3 are turned on to read the reset signals of the unit pixels 210_1 and 210_3. At this time, it is preferable that the reference voltage VREFP is applied to the positive terminal of the amplifier A1. In addition, the transmission signals TX and TX_S remain in an inactive state, and thus the transmission transistor T2 is maintained in a turned off state.

Thereafter, the reset signal RT is deactivated between the interval 1 and the interval 2 so that the reset transistor T1 is turned off to stop the reset operation. The switch S1 is turned off between the section 1 and the section 2. Accordingly, the voltage VRAMP is not supplied to the amplifier A1.

Next, when the transmission signal TX_S is activated in the section 2, the transmission transistor T2 of the unit pixels 210_3 and 210_4 is turned on. Accordingly, the pixel information P0_Gr1 of the unit pixel 210_3 and the pixel information P0_R1 of the unit pixel 210_4 are read. Accordingly, the voltage of VREF-ΔV1 is stored in the node NDA of FIG. 5. Here, ΔV1 = Vreset of Gr1-Vsignal of Gr1.

Subsequently, when the switch SW5 is turned on in the section 3, the sampling voltage VREF-ΔV1 of the node NDA is transferred to the node NDB and sampled by the node NDB of the amplifier A1.

Next, when the transmission signal TX of the pixel to be added later is activated in the interval 4, the transmission transistor T2 of the unit pixels 210_1 and 210_2 is turned on. Accordingly, the pixel information P0_Gr0 of the unit pixel 210_1 and the pixel information P0_R0 of the unit pixel 210_2 are read.

At this time, the node NDB has a potential change to VREF-ΔV1-ΔV0. DELTA V0 = Vreset of Gr0-Vsignal of Gr0. Then, the switch SW1, which is a sampling switch, is turned off to prepare for performing analog-to-digital conversion.

Thereafter, the switch S1 is turned on to perform the analog-to-digital conversion. In operation 5, the ADC 240 operates when the voltage VRAMP drops to a voltage ΔV1 + ΔV0 representing a sum of signals of two identical colors (eg, Gr).

Information counted by the ADC 240 is stored in a latch of the line memory 260. At this time, the swing range of the voltage VRAMP should be doubled when compared to the full mode.

Table 1 shows voltage levels of respective sections in the operation timing diagram of FIG. 6.

Section (1) Section (2) Section (3) Section (4) Section (5) Voltage at node NDA VREFP VREFP-ΔV1 VREFP-ΔV1 VREFP-ΔV1 from VREFP to VREFN Voltage at node NDB unknown unknown VREFP-ΔV1 VREFP-ΔV1-ΔV0 VREFP-ΔV1-ΔV0

As shown in Table 1, the time point at which the ADC 240 operates in the section 5 is when the voltage VRAMP level is smaller than the VREFP- (ΔV1 + ΔV0) voltages. Therefore, the ADC 240 operates at the time when the voltage DELTA V1 + DELTA V0 is exactly reached. Accordingly, analog-to-digital conversion is performed by changing the voltage VRAMP level from the VREFP voltage to the VREFN voltage level in the section 5.

That is, the output of the amplifier A is provided to the line memory 260, the ADC operation by storing the value of the digital code that is sequentially changed in the period of the ADC in the line memory 260 from the moment the output voltage of the amplifier A is changed Is done

The present invention accurately adds signal voltages of pixels having the same color to perform ADC operation. Accordingly, the signal sensitivity is increased by adding the values of the pixels corresponding to the same signal. This invention does not require the addition of a separate capacitor and can be implemented in a simple manner through a switch.

7 is another embodiment of the CMOS image sensor of the present invention. In the present invention, a case where the information of the pixel is sampled and read out in a 1 × 2 sub sampling mode will be described as an embodiment.

The present invention relates to a pixel array 300, a row driver 320, a correlated double sampling (CDS) circuit 330, an analog to digital converter (ADC) 340, an analog control block ( An analog control block 350, a line memory 360, a timing generator 370, and a column decoder 380.

Here, the pixel array 300 includes a plurality of unit pixels 310 arranged in a matrix in the row and column directions. The row driver 320 selects a row line of the pixel array 300.

The CDS circuit 330 removes fixed pattern noise of the unit pixel 310. The ADC 340 converts the analog video signal output from the corresponding CDS circuit 330 into a digital video signal.

The analog control block 350 also controls the operation of the CDS circuit 330 and the ADC 340. Each line memory 360 stores image information of a column line corresponding to the pixel array 300. Here, each line memory 360 may include two latches for sequentially storing pixel information of two row lines.

In addition, the TG 370 represents a timing generator and generates and supplies a timing necessary for the operation of the sensor. That is, the TG 370 generates the supply signals required for the row driver 320, the analog control block 350, and the column decoder 380.

In addition, the column decoder 380 decodes the address signal in the column direction and outputs pixel information stored in the line memory 360.

In the image sensor of the present invention having such a configuration, information of all the pixel arrays 300 is read out and the color pixel information is summed and averaged through the CDS circuit 330 and the ADC 340. Color information averaged through the CDS circuit 330 and the ADC 340 is stored in the line memory 260 via the ADC 340.

Referring to the operation of the present invention having such a configuration as follows.

In the pixel array 300 of FIG. 7, color pixels in the order of R, Gr, R, Gr ... are listed in the first row line, and Gb, B, Gb, B .. Assume that the sequence of color pixels is listed.

In the conventional structure of FIG. 2, pixel information read in the first and second column lines of the pixel array is read out through the column decoder through the CDS circuit and the ADC. The pixel information of the third and fourth column lines is skipped without reading out.

That is, R, Gr pixels of the first and second column lines are read out on one row line, and R, GR of the third and fourth column lines are skipped, and the next row line In the same way, the pixel is read out.

However, in the present invention, all the unit pixels 310 of the pixel array 300 are read out. That is, after the pixel information of all the pixel arrays 300 are transferred to the CDS circuit 330 and the ADC 340, pixels of the same color are added and averaged by an analog binning operation.

Then, after analog-to-digital conversion in one amplifier A through the CDS circuit 330, it is stored in the line memory 360. Thereafter, the digital data value stored in the line memory 360 is transferred to the image signal processing (ISP) at a later stage through the column decoder 380.

Here, the ISP corrects the difference between the image signal detected by the CMOS image sensor and the image signal to be displayed on the screen (gamma correction), and inputs a pixel for insufficient color among the gamma corrected image signals. To convert the complete image data.

FIG. 8 is a detailed circuit diagram of the pixel array 300, the correlated double sampling (CDS) circuit 330, and the ADC 340 of FIG. 7. In the present invention, the unit pixel 310 of the pixel array 300 has a 4TR structure.

Each unit pixel 310 includes a photodiode PD, a reset transistor T1, a transfer transistor T2, a driving transistor T3, and a selection transistor T4.

Here, the photodiode PD is connected between the transfer transistor T2 and the ground voltage terminal to generate an optical charge corresponding to the optical image of the subject. The reset transistor T1 is connected between the supply voltage VDD applying stage and the floating diffusion node FD. This reset transistor T1 discharges the charge stored in the floating diffusion node FD in response to the reset signal RT for detection of the next image information.

Then, the transfer transistor T2 is connected between the floating diffusion node FD and the photodiode PD, and transmits the optical charge generated at the photodiode PD to the floating diffusion node FD in response to the transmission signal TX.

The driving transistor T3 is connected between the supply voltage VDD applying terminal and the selection transistor T4 to serve as a source follower. In addition, the selection transistor T4 is connected between the driving transistor T3 and the pixel information output terminal, and may perform addressing by switching in response to the selection signal LS.

The unit pixel 310 having such a configuration outputs pixel information P0_Gr0 through the unit pixel 310_1 and outputs pixel information P0_R0 through the unit pixel 310_2. The pixel information P0_Gr1 is output through the unit pixel 310_3, and the pixel information P0_R1 is output through the unit pixel 310_4.

Meanwhile, the CDS circuit 330_1 includes switches SW1 and SS3 and capacitors Ch1, Cs1 and Chhr1. The CDS circuit 330_2 includes switches SW2 and SS4 and capacitors Ch2, Cs2 and Chhr2. The CDS circuit 330_3 includes switches SW3 and SS5 and capacitors Ch3, Cs3 and Chhr3. The CDS circuit 330_4 includes switches SW4 and SS6 and capacitors Ch4, Cs4 and Chhr4.

Here, the switches SW1 to SW4 are connected between the output terminal of the unit pixel 310 and the capacitors Cs1 to Cs4, respectively, to selectively connect the unit pixel 310 and the CDS circuit 330. When the switches SW1 to SW4 are turned on, pixel information of the unit pixel 310 is transferred to the CDS circuit 330.

The capacitors Ch1 to Ch4 are connected between the switches SW1 to SW4 and the ground voltage terminal to discharge signal voltages applied from the switches SW1 to SW4.

In addition, the capacitors Cs1 to Cs4 are connected between the switches SW1 to SW4 and the negative terminals of the amplifiers A1 to A4 to store the sensing voltages of the unit pixels 310 applied through the switches SW1 to SW4. When the value of the capacitor Cs and the value of the capacitor Chr are the same, the average value of the signal read out from two pixels having the same color is transferred to the ADC 340.

In addition, the capacitors Chr1 to Chhr4 are connected between the switches SS3 to SS6 and the ground voltage terminal to discharge signal voltages applied from the switches SS3 to SS6. The switches SS3 to SS6 are connected between the capacitors Cs1 to Cs4 and the capacitors Chr1 to Chhr4, respectively, and selectively connect the capacitors Cs1 to Cs4 and the capacitors Chr1 to Chr4.

In addition, ADC 340_1 includes switches SS1, S1, SW5 and amplifier A1. ADC 340_2 includes switches SS2, S2, SW6 and amplifier A2. In addition, ADC 340_3 includes switches S3, SW7 and amplifier A3. In addition, ADC 340_4 includes switches S4, SW8 and amplifier A4.

Here, the switch SS1 connects the positive input terminal of the amplifier A1 and the negative input terminal of the amplifier A3 at the unit pixels 310_1 and 310_3 having the same color, and the switch SS2 has the unit pixel 310_2 having the same color. (310_4) is a configuration for connecting the positive input terminal of amplifier A2 and the negative input terminal of amplifier A4.

In addition, the switches S1 to S4 are connected between the positive (+) terminals of the amplifiers A1 to A4 and the voltage VRAMP applying terminal, respectively, to selectively supply or cut off the voltage VRAMP.

Each CDS circuit 330_1 to 330_4 divides a capacitance value by a ratio of capacitors Cs1 to Cs4 and capacitors Chr1 to Chhr4. That is, as shown in FIG. 4, pixels of the same color are summed with each other, but the values are summed by a ratio between the sampling capacitors Cs1 to Cs4 and the hold capacitance of the node NDB (or node NDA). Here, the sizes of the capacitors Chr1 to Chhr4 are all set the same.

The switches SS1, SS2, S1 to S4, and SS3 to SS6 operate only in the 1 × 2 subsampling mode, and the switches SS1 and SS2 are always in the OFF state in a full resolution read out mode. It is preferable that the switches S1 to S4 always be turned on. In addition, the switches SS3 to SS6 should always be turned off.

9 is a circuit diagram schematically illustrating a correlated double sampling (CDS) circuit 330 and an ADC 340 of FIG. 8. In FIG. 9, a case in which the pixel information of the unit pixels 310_1 and 310_3 having the green color is summed will be described as an exemplary embodiment.

Assume that the switch SS1 connecting the unit pixels 310_1 and 310_3 having the green color is turned on. In this case, the node NDB which is the negative terminal of the amplifier A1 is connected to the unit pixel 310_1, and the node NDA which is the positive terminal is connected to the unit pixel 310_3.

At this time, when the switch SS3 is turned on, the value of the capacitance applied to the node NDB is determined by the ratio of the capacitor Cs1 and the capacitor Chr1. When the switch SS5 is turned on, the value of the capacitance applied to the node NDA is determined by the ratio of the capacitor Cs3 and the capacitor Chr3.

The amplifier A1 receives and compares pixel information P0_Gr0 and P0_Gr1 applied from the nodes NDB and NDA, and outputs corresponding digital values.

Table 2 shows voltage levels of respective sections in the operation timing diagram of FIG. 6 according to the embodiment of FIG. 8. It is assumed here that all of the values of the capacitors Chr1, Chr3, Ch1, Ch3 are the same.

Section (1) Section (2) Section (3) Section (4) Section (5) Voltage at node NDA VREFP VREFP- (ΔV1 / 2) VREFP- (ΔV1 / 2) VREFP- (ΔV1 / 2) from VREFP to VREFN Voltage at node NDB unknown unknown VREFP- (ΔV1 / 2 VREFP- (ΔV1 / 2)-(ΔV0 / 2) VREFP- (ΔV1 / 2)-(ΔV0 / 2)

As shown in Table 2, the time point at which the ADC 340 operates in the section 5 is when the voltage VRAMP level is smaller than the voltage VREFP- (ΔV1 / 2 + ΔV0 / 2). Therefore, the ADC 340 operates at the time when the voltage DELTA V1 + DELTA V0 / 2 is achieved.

Here, ΔV1 = Vreset of Gr1-Vsignal of Gr1. And? V0 = Vreset of Gr0-Vsignal of Gr0. At this time, the offset voltage of the amplifier A should not be considered.

If the values of the capacitors Chr3 and Cs3 are different from each other, the voltage of the node NDA becomes VREFP-ΔV1 * (Cs3 / (Cs3 + Chr3)) in the interval (3). If the values of the capacitors Chr1 and Cs1 are different, the voltage of the node NDB is VREFP- (ΔV1 * (Cs3 / (Cs3 + Chr3))-(ΔV0 * (Cs1 / (Cs1 + Chr1)) in the interval (4). do.

That is, the output of the amplifier A is provided to the line memory 360, and the ADC operation is performed by storing the value of the digital code which is sequentially changed in the period of the ADC in the line memory 360 from the moment when the output voltage of the amplifier A is changed. Is done

As such, the embodiment of FIG. 8 operates as a signal attenuator so that when the values of the capacitor Cs and the capacitor Chr are the same, the voltage VRAMP is equal to the range in the sub mode and the full mode. ) To operate. The noise is reduced by obtaining a signal average from two pixels having the same color, thereby improving the overall image quality.

As described above, the present invention has the following effects.

First, the present invention reads out pixels of the same color in the analog domain and adds information of the pixels to improve sensing sensitivity.

Second, the present invention prevents saturation during signal summation by reducing a signal attenuator circuit combined with the function of analog domain signal summation, and improves image quality by reducing noise generated at a signal node.

Third, the present invention provides an effect of reducing the time taken to read out the pixel information while improving the sensing sensitivity by reading the information of all the pixels in the sub sampling mode.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (31)

A pixel array including a plurality of unit pixels for generating pixel information corresponding to an optical image; A row driver to select a row line of the pixel array; A plurality of CDS circuits for outputting an analog image signal by removing fixed pattern noise included in pixel information generated from the plurality of unit pixels; A plurality of ADCs for adding pixel information of unit pixels having the same color among the analog image signals by an analog binning operation in the analog domain and converting the analog image signal subjected to the analog binning operation into a digital image signal; A plurality of line memories for storing the digital image signals output from the plurality of ADCs; And And a column decoder for decoding the address signals in the column direction and outputting image information stored in the plurality of line memories. The method of claim 1, An analog control block for controlling operations of the plurality of CDS circuits and the plurality of ADCs; And And a timing generator for generating a supply signal for the row driver, the analog control block and the column decoder. The CMOS image sensor of claim 1, wherein when the sum of pixel information of unit pixels having the same color is added, the plurality of ADCs operate at half of the plurality of unit pixels. The method of claim 1, wherein each of the plurality of unit pixels A photodiode for generating a photocharge corresponding to the optical image of the subject; A transfer transistor for transmitting the photocharge generated by the photodiode to a floating diffusion node in response to a transmission signal; A reset transistor for discharging charge stored in the floating diffusion node in response to a reset signal for detecting next image information; A driving transistor serving as a source follower; And And a selection transistor for performing addressing with switching in response to the selection signal. The method of claim 1, wherein each of the plurality of CDS circuits is A first switch for selectively supplying pixel information applied from the plurality of unit pixels; A first capacitor storing a signal voltage applied from the first switch; And And a second capacitor connected to the first switch. The CMOS image sensor of claim 5, wherein each of the first capacitors included in the plurality of CDS circuits has the same size. The CMOS image sensor of claim 5, wherein each of the second capacitors included in the plurality of CDS circuits has the same size. The method of claim 1, wherein each of the plurality of ADCs An amplifier for comparing the signal of the first node and the signal of the second node and outputting a corresponding digital value; A second switch for selectively connecting input terminals of an amplifier having the same color among the plurality of unit pixels; A third switch selectively connecting the second node and a reference voltage input terminal; And And a fourth switch for selectively coupling an input terminal and an output terminal of the amplifier. The method of claim 8, wherein the second switch connects a first amplifier and a second amplifier to which the same pixel information of the amplifier is applied, and connects a positive terminal of the first amplifier and a negative terminal of the second amplifier. CMOS image sensor. The CMOS image sensor of claim 8, wherein one third switch is provided for each column line, and the third switch included in the plurality of CDS circuits is controlled at the same timing. The CMOS image sensor of claim 8, wherein one second switch is provided for each of two column lines having the same color. The CMOS image sensor of claim 1, wherein the plurality of unit pixels and the plurality of CDS circuits are formed in the same number. A pixel array including a plurality of unit pixels for generating pixel information corresponding to an optical image; A row driver to select a row line of the pixel array; An analog image signal is obtained by removing fixed pattern noise included in pixel information generated by the plurality of unit pixels and averaging pixel information of unit pixels having the same color among the plurality of unit pixels by an analog binning operation in the analog domain. A plurality of CDS circuits for outputting; A plurality of ADCs for converting the analog video signal into a digital video signal; A plurality of line memories for storing the digital image signals output from the plurality of ADCs; And And a column decoder for decoding the address signals in the column direction and outputting image information stored in the plurality of line memories. The method of claim 13, An analog control block for controlling operations of the plurality of CDS circuits and the plurality of ADCs; And And a timing generator for generating a supply signal for the row driver, the analog control block and the column decoder. The CMOS image sensor of claim 13, wherein when the pixel information of the unit pixels having the same color is averaged, the plurality of ADCs operate half of the plurality of unit pixels. The method of claim 13, wherein each of the plurality of unit pixels A photodiode for generating a photocharge corresponding to the optical image of the subject; A transfer transistor for transmitting the photocharge generated by the photodiode to a floating diffusion node in response to a transmission signal; A reset transistor for discharging charge stored in the floating diffusion node in response to a reset signal for detecting next image information; A driving transistor serving as a source follower; And And a selection transistor for performing addressing with switching in response to the selection signal. The method of claim 13, wherein each of the plurality of CDS circuits is A first switch for selectively supplying pixel information applied from the plurality of unit pixels; A first capacitor storing a signal voltage applied from the first switch; A second capacitor connected to the first switch to store a signal voltage; A third capacitor for storing a signal voltage applied from the second capacitor; And And a second switch for selectively coupling the third capacitor and the second capacitor. 18. The CMOS image sensor of claim 17, wherein each of the plurality of CDS circuits has a capacitance value divided by a ratio of the second capacitor and the third capacitor. 18. The CMOS image sensor of claim 17, wherein the first capacitors each included in the plurality of CDS circuits have the same size. 18. The CMOS image sensor of claim 17, wherein the second capacitors each included in the plurality of CDS circuits have the same size. 18. The CMOS image sensor of claim 17, wherein the third capacitors each included in the plurality of CDS circuits have the same size. The method of claim 13, wherein each of the plurality of ADCs An amplifier for comparing the signal of the first node and the signal of the second node and outputting a corresponding digital value; A third switch for selectively connecting input terminals of an amplifier connected to unit pixels having the same color among the unit pixels; A fourth switch for selectively connecting the second node and a reference voltage input terminal; And And a fifth switch for selectively coupling an input terminal and an output terminal of the amplifier. The method of claim 22, wherein the third switch connects a first amplifier and a second amplifier to which the same pixel information of the amplifier is applied, and connects a positive terminal of the first amplifier and a negative terminal of the second amplifier. CMOS image sensor. The CMOS image sensor of claim 13, wherein the plurality of unit pixels and the plurality of CDS circuits are formed in the same number. A first unit pixel for storing first pixel information; A second unit pixel storing second pixel information having the same color as the first pixel information; A first switch for selectively supplying an output of the first unit pixel; A second switch for selectively supplying an output of the second unit pixel; A first capacitor storing an output voltage of the first switch; A second capacitor storing an output voltage of the second switch; A third capacitor for storing a signal voltage applied from the first switch; A fourth capacitor for storing a signal voltage applied from the second switch; And an amplifier comparing the output of the third capacitor with the output of the fourth capacitor and outputting a corresponding digital value. 27. The CMOS image sensor of claim 25, further comprising a third switch coupled between an output terminal of the amplifier and a negative input terminal. 27. The CMOS image sensor of claim 25, further comprising a fourth switch connected between the positive input terminal of the amplifier and the reference voltage applying terminal. 28. The CMMOS image sensor of claim 27, wherein the fourth switch maintains a turn-off state during a readout period of the first pixel information and the second pixel information. The method of claim 25, A fifth capacitor connected between the negative input terminal and the ground voltage terminal of the amplifier; A sixth capacitor connected between the positive input terminal and the ground voltage terminal of the amplifier; A fifth switch for selectively connecting the negative input terminal and the fifth capacitor; And And a sixth switch for selectively connecting the positive input terminal and the sixth capacitor. 26. The method of claim 25, wherein the first switch maintains a turn-on state in a section in which the first pixel information and the second pixel information are read out, and the second switch in a section in which the first pixel information is read out. CMOS image sensor, characterized in that it is kept on. 26. The CMOS image sensor of claim 25, wherein the first pixel information and the second pixel information are transmitted to the amplifier at different points in time by a transmission signal.

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