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KR100900244B1 - Device Separating Method of Semiconductor Device - Google Patents

Device Separating Method of Semiconductor Device Download PDF

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KR100900244B1
KR100900244B1 KR1020020070728A KR20020070728A KR100900244B1 KR 100900244 B1 KR100900244 B1 KR 100900244B1 KR 1020020070728 A KR1020020070728 A KR 1020020070728A KR 20020070728 A KR20020070728 A KR 20020070728A KR 100900244 B1 KR100900244 B1 KR 100900244B1
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film
oxide film
substrate
trench
nitride
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KR20040042429A (en
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윤일영
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step

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Abstract

본 발명은 반도체 소자의 소자분리막 형성방법을 개시한다. 개시된 본 발명의 반도체 소자의 소자분리막 형성방법은 반도체 기판 상에 식각 장벽 물질로서 산화막을 증착하는 단계; 상기 산화막을 식각하여 소자분리 영역에 해당하는 기판 부분을 노출시키는 단계; 상기 노출된 기판 부분을 식각하여 소정 깊이의 트렌치를 형성하는 단계; 상기 트렌치를 매립하도록 기판 결과물 상에 질화막을 증착하는 단계; 상기 질화막을 리버스 에치백(Reverse etch-back)하여 기판 소자 영역 상의 증착된 부분을 식각하는 단계; 상기 산화막이 노출되도록 상기 질화막을 CMP하는 단계; 및 상기 산화막을 제거하는 단계를 포함한다. 본 발명에 따르면 소자분리막 형성시 발생되는 디싱을 방지할 수 있다. The present invention discloses a method for forming a device isolation film of a semiconductor device. A method of forming a device isolation film of a semiconductor device according to the present invention includes depositing an oxide film as an etch barrier material on a semiconductor substrate; Etching the oxide film to expose a substrate portion corresponding to an isolation region; Etching the exposed portion of the substrate to form a trench of a predetermined depth; Depositing a nitride film on a substrate resultant to fill said trench; Reverse etch-backing the nitride layer to etch the deposited portion on the substrate device region; CMP the nitride film to expose the oxide film; And removing the oxide film. According to the present invention, dishing generated when the device isolation layer is formed can be prevented.

Description

반도체 소자의 소자분리막 형성방법{METHOD FOR FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE}METHODS FOR FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE

도 1a 내지 도 1d는 본 발명의 실시예에 따른 STI 공정에서의 반도체 소자의 소자분리막 형성방법을 설명하기 위한 공정별 단면도.1A to 1D are cross-sectional views illustrating processes of forming an isolation layer of a semiconductor device in an STI process according to an embodiment of the present invention.

-도면의 주요 부분에 대한 부호의 설명-Explanation of symbols on main parts of drawing

1 : 반도체 기판 3 : 산화막1 semiconductor substrate 3 oxide film

5 : 트렌치 7 : 질화막5: trench 7: nitride film

9 : 소자분리막 9: device isolation film

본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 보다 상세하게는, 반도체 소자의 특성을 향상시킬 수 있는 소자분리막 형성방법에 관한 것이다. The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film capable of improving the characteristics of a semiconductor device.

주지된 바와 같이, 소자들간의 전기적 분리를 위한 소자분리(isolation) 방법으로서는 LOCOS에 의한 필드 산화막의 형성이 이용되어져 왔다. 그런데, LOCOS에 의한 필드산화막은 집적도 측면에서 단점이 있는 바, 그 이용에 한계를 갖게 되었 고, 그래서, 현재의 반도체 제조 공정에서는 소자분리 방법으로서 STI(Shallow Trench Isolation) 공정을 이용하고 있다.As is well known, formation of a field oxide film by LOCOS has been used as an isolation method for electrical isolation between devices. However, since the field oxide film by LOCOS has a disadvantage in terms of integration degree, the use of the field oxide film has a limitation, and therefore, in the current semiconductor manufacturing process, a shallow trench isolation (STI) process is used as a device isolation method.

이러한 STI 공정은 반도체 기판의 적소에 얕은 깊이의 트렌치를 형성한 후, 이 트렌치 내에 절연물을 매립시킴으로써, 인접하는 소자들간을 전기적으로 분리시키는 트렌치형의 소자분리막이 형성되도록 하는 방법이다.The STI process is a method of forming a trench type device isolation film for electrically separating adjacent devices by forming a trench having a shallow depth in place in the semiconductor substrate and then filling an insulator in the trench.

자세하게, 상기 트렌치형의 소자분리막을 형성하기 위해, 우선, 벌크 실리콘으로 이루어진 반도체 기판 상에 패드산화막과 패드질화막을 차례로 증착한 후, 상기 막들을 패터닝하여 소자분리 영역에 해당하는 기판 부분을 노출시킨다. 그런다음, 상기 노출된 기판 부분을 식각하여 트렌치를 형성하고, 이 트렌치가 완전히 매립되도록 상기 결과물 상에 산화막을 증착한다. 이어서, 상기 패드질화막이 노출되도록 상기 산화막을 CMP하고, 이를 통해, 트렌치형의 소자분리막을 형성한다. 그리고나서, 잔류된 패드질화막 및 패드산화막을 제거한다.In detail, in order to form the trench type isolation layer, first, a pad oxide layer and a pad nitride layer are deposited on a semiconductor substrate made of bulk silicon, and then the layers are patterned to expose a substrate portion corresponding to the isolation region. . The exposed portion of the substrate is then etched to form a trench, and an oxide film is deposited on the resultant to fill the trench completely. Subsequently, the oxide film is CMP to expose the pad nitride film, thereby forming a trench isolation device. Then, the remaining pad nitride film and pad oxide film are removed.

그러나, 상기와 같은 반도체 소자의 소자분리막 형성방법은 산화막을 연마할때, 질화막과 산화막간의 연마 선택비 차이로 인해 트렌치 내의 산화막 표면, 즉, 소자분리막의 표면에서 디싱(Dishing) 현상이 일어나며, 이로 인해, 공정마진은 물론 소자특성 저하가 야기된다.However, in the method of forming an isolation layer of a semiconductor device as described above, dishing occurs on the surface of the oxide layer in the trench, that is, on the surface of the isolation layer due to the difference in the polishing selectivity between the nitride layer and the oxide layer when polishing the oxide layer. As a result, process margins as well as deterioration of device characteristics are caused.

특히, 이러한 디싱은 패턴 밀도가 높은 지역보다 패턴 밀도가 낮은 지역에서 더욱 심하게 나타난다.In particular, this dishing is more severe in areas with low pattern density than in areas with high pattern density.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 소자분리막 형성시 발생하는 디싱의 발생을 억제시킬 수 있는 반도체 소자의 소자분리막 형성방법을 제공하는데, 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a device isolation film of a semiconductor device capable of suppressing the occurrence of dishing occurring when the device isolation film is formed.

상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 소자분리막 형성방법은 반도체 기판 상에 식각 장벽 물질로서 산화막을 증착하는 단계; 상기 산화막을 식각하여 소자분리 영역에 해당하는 기판 부분을 노출시키는 단계; 상기 노출된 기판 부분을 식각하여 소정 깊이의 트렌치를 형성하는 단계; 상기 트렌치를 매립하도록 기판 결과물 상에 질화막을 증착하는 단계; 상기 질화막을 리버스 에치백(Reverse etch-back)하여 기판 소자 영역 상의 증착된 부분을 식각하는 단계; 상기 산화막이 노출되도록 상기 질화막을 CMP하는 단계; 및 상기 산화막을 제거하는 단계를 포함한다.Method of forming a device isolation film of a semiconductor device of the present invention for achieving the above object comprises the steps of depositing an oxide film as an etch barrier material on a semiconductor substrate; Etching the oxide film to expose a substrate portion corresponding to an isolation region; Etching the exposed portion of the substrate to form a trench of a predetermined depth; Depositing a nitride film on a substrate resultant to fill said trench; Reverse etch-backing the nitride layer to etch the deposited portion on the substrate device region; CMP the nitride film to expose the oxide film; And removing the oxide film.

여기서, 상기 산화막은 1000∼2000Å의 두께로 증착하고, 그리고, 상기 트렌치는 3000∼3500Å의 깊이로 형성한다. 또한, 상기 질화막은 LPCVD 또는 PECVD 방식으로 상기 트렌치를 매립하도록 4000∼5000Å 두께로 증착한다. Here, the oxide film is deposited to a thickness of 1000 to 2000 GPa, and the trench is formed to a depth of 3000 to 3500 GPa. In addition, the nitride film is deposited to a thickness of 4000 to 5000 하도록 to fill the trench by LPCVD or PECVD.

그리고, 상기 질화막의 리버스 에치백은 산화막 상의 질화막의 잔류 두께가 400∼500Å이 되도록 수행한다. 또한, 상기 산화막을 제거하는 단계는 BOE(HF:NH4F=1:200) 용액으로 수행한다.The reverse etch back of the nitride film is performed so that the remaining thickness of the nitride film on the oxide film is 400 to 500 kPa. In addition, the step of removing the oxide film is performed with a BOE (HF: NH4F = 1: 200) solution.

본 발명에 따르면, 질화막을 사용하여 소자분리막을 형성하기 때문에, 종래의 산화막으로 형성된 소자분리막에서 야기되는 디싱의 발생을 개선할 수 있으며, 그래서, 공정 마진 및 소자의 신뢰성을 확보할 수 있다. According to the present invention, since the device isolation film is formed using the nitride film, it is possible to improve the occurrence of dishing caused in the device isolation film formed of the conventional oxide film, and thus, the process margin and the reliability of the device can be secured.                     

(실시예)(Example)

이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1d는 본 발명의 실시예에 따른 STI 공정에서의 반도체 소자의 소자분리막 형성방법을 설명하기 위한 단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device in an STI process according to an embodiment of the present invention.

도 1a를 참조하면, 반도체 기판(1) 상에 기판 식각시의 식각 장벽 물질로서 산화막(3)을 1000∼2000Å의 높이로 증착한다. 그런다음, 상기 산화막(3)을 식각하여 소자분리 영역에 해당하는 기판 부분을 노출시킨다.Referring to FIG. 1A, an oxide film 3 is deposited on the semiconductor substrate 1 at a height of 1000 to 2000 GPa as an etch barrier material during substrate etching. Then, the oxide film 3 is etched to expose the substrate portion corresponding to the device isolation region.

도 1b를 참조하면, 상기 산화막(3)을 식각장벽으로 이용하여 노출된 기판 부분을 식각하고, 이를 통해, 트렌치(5)를 형성한다. 그런다음, 상기 트렌치(5)를 매립하도록 기판 결과물 상에 트렌치 매립 물질로서 질화막(7)을 증착한다. 이때, 상기 질화막(7)은 PECVD(Plasma Enchanced Chemica Vapor Deposition) 또는 LPCVD (Low Pressure Chemical Vapor Deposition) 방식으로 증착한다.Referring to FIG. 1B, the exposed portion of the substrate is etched using the oxide film 3 as an etch barrier, thereby forming the trench 5. Then, a nitride film 7 is deposited as a trench buried material on the substrate resultant to fill the trench 5. In this case, the nitride layer 7 is deposited by Plasma Enchanced Chemica Vapor Deposition (PECVD) or Low Pressure Chemical Vapor Deposition (LPCVD).

또한, 트렌치의 깊이가 3000∼3500Å인 경우, 질화막은 4000∼4500Å의 두께로 증착한다.In addition, when the depth of the trench is 3000 to 3500 mV, the nitride film is deposited with a thickness of 4000 to 4500 mV.

도 1c를 참조하면, 상기 질화막(7)을 리버스 에치백(Reverse etch-back)하여 기판 소자 영역 상의 증착된 부분을 식각한다. 이때, 소자분리 영역의 질화막(7)은 500Å, 바람직하게는, 400∼500Å의 높이로 잔류시킨다. 다음으로, 상기 질화막(7)이 500Å 미만의 두께가 되도록 CMP하여 산화막(3)을 노출시킨다.Referring to FIG. 1C, the nitride layer 7 is reverse etched back to etch the deposited portion on the substrate device region. At this time, the nitride film 7 of the element isolation region is left at a height of 500 mW, preferably 400 to 500 mW. Next, the nitride film 7 is CMP so as to have a thickness of less than 500 GPa to expose the oxide film 3.

여기서, 상기 산화막(3)은 질화막(7)을 CMP 할때, 전술한 바와 같이, 식각 정지층으로서 기능을 한다. 이때, 상기 산화막(3)과 질화막(7)간의 연마 선택비는 약 4:1 이므로, 상기 산화막(3)의 두께가 상대적으로 많이 감소하여 후속의 공정 마진을 증가시키고, 또한, 상기 트렌치 내의 질화막(7)에는 디싱(Dishing) 현상이 일어나지 않는다.Here, the oxide film 3 functions as an etch stop layer when the nitride film 7 is CMP, as described above. At this time, since the polishing selectivity between the oxide film 3 and the nitride film 7 is about 4: 1, the thickness of the oxide film 3 decreases relatively much, thereby increasing the subsequent process margin, and further, the nitride film in the trench. No dishing occurs in (7).

도 1d를 참조하면, HF:NH4F을 1:200으로 섞어 만든 BOE 용액을 이용하여 기판 상의 산화막을 제거하고, 이 결과로서, 소자분리막(9)의 형성을 완성한다. Referring to FIG. 1D, the oxide film on the substrate is removed using a BOE solution made by mixing HF: NH4F at 1: 200, and as a result, the formation of the device isolation film 9 is completed.

한편, 후속에 기판 결과물에 대한 후속의 세정 공정에서 상기 소자분리막(9)은 질화막으로 형성되어 있는 바, 디싱은 발생되지 않는다.On the other hand, since the device isolation film 9 is formed of a nitride film in a subsequent cleaning process for the substrate result, dishing does not occur.

이상에서와 같이, 본 발명은 질화막으로 소자분리막을 형성하므로 종래의 산화막으로 이루어진 소자분리막과 비교하여 그 형성시에 디싱의 발생을 억제할 수 있으며, 또한, 후속의 세정 공정에서도 디싱의 발생을 억제시킬 수 있다. As described above, since the device isolation film is formed of a nitride film, the present invention can suppress the occurrence of dishing at the time of its formation compared with the device isolation film made of a conventional oxide film, and also suppress the occurrence of dishing in a subsequent cleaning process. You can.

따라서, 본 발명은 공정마진은 물론, 험프(Hump), 접합 누설전류(junction leakeage), 및 인버스 내로우 위드 이펙트(Inverse narrow width effect) 현상을 개선할 수 있으며, 그래서, 소자의 신뢰성을 향상시킬 수 있다. Accordingly, the present invention can improve not only process margins, but also hum, junction leakeage, and inverse narrow width effect phenomena, thereby improving device reliability. Can be.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시 할 수 있다.In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (6)

반도체 기판 상에 식각 장벽 물질로서 산화막을 증착하는 단계;Depositing an oxide film as an etch barrier material on the semiconductor substrate; 상기 산화막을 식각하여 소자분리 영역에 해당하는 기판 부분을 노출시키는 단계;Etching the oxide film to expose a substrate portion corresponding to an isolation region; 상기 노출된 기판 부분을 식각하여 소정 깊이의 트렌치를 형성하는 단계;Etching the exposed portion of the substrate to form a trench of a predetermined depth; 상기 트렌치를 매립하도록 기판 결과물 상에 질화막을 증착하는 단계;Depositing a nitride film on a substrate resultant to fill said trench; 상기 질화막을 리버스 에치백(Reverse etch-back)하여 기판 소자 영역 상의 증착된 부분을 식각하는 단계;Reverse etch-backing the nitride layer to etch the deposited portion on the substrate device region; 상기 산화막이 노출되도록 상기 질화막을 CMP하는 단계; 및CMP the nitride film to expose the oxide film; And 상기 산화막을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.And removing the oxide film. 제 1 항에 있어서, 상기 산화막은 1000∼2000Å의 두께로 증착하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The method of claim 1, wherein the oxide film is deposited to a thickness of 1000 to 2000 GPa. 제 1 항에 있어서, 상기 트렌치는 3000∼3500Å의 깊이로 형성하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.2. The method of claim 1, wherein the trench is formed to a depth of 3000 to 3500 GPa. 제 1 항에 있어서, 상기 질화막은 LPCVD 또는 PECVD 방식으로 상기 트렌치를 매립하도록 4000∼5000Å 두께로 증착하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The method of claim 1, wherein the nitride film is deposited to a thickness of 4000 to 5000 하도록 so as to fill the trench by LPCVD or PECVD. 제 1 항에 있어서, 상기 질화막의 리버스 에치백은 산화막 상의 질화막의 잔류 두께가 400∼500Å이 되도록 수행하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The method of claim 1, wherein the reverse etch back of the nitride film is performed such that the remaining thickness of the nitride film on the oxide film is 400 to 500 kPa. 제 1 항에 있어서, 상기 산화막을 제거하는 단계는 BOE(HF:NH4F=1:200) 용액으로 수행하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The method of claim 1, wherein the removing of the oxide layer is performed using a BOE (HF: NH 4 F = 1: 200) solution.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000043559A (en) * 1998-12-29 2000-07-15 김영환 Method for forming isolation layer of semiconductor device
KR20010086597A (en) * 2001-06-07 2001-09-15 우남균 vaccum double-cover bottel
KR20020009101A (en) * 2000-07-24 2002-02-01 윤종용 Trench isolation method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000043559A (en) * 1998-12-29 2000-07-15 김영환 Method for forming isolation layer of semiconductor device
KR20020009101A (en) * 2000-07-24 2002-02-01 윤종용 Trench isolation method
KR20010086597A (en) * 2001-06-07 2001-09-15 우남균 vaccum double-cover bottel

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