KR100891411B1 - Nonvolatile memory device and reading method thereof - Google Patents

Abstract

The present invention relates to a nonvolatile memory device capable of reducing current consumption during a read or verify operation.

The nonvolatile memory device of the present invention includes a precharge unit for applying a high level voltage to a bit line, a cell string connected between the bit line and the ground terminal, and including a plurality of serially connected memory cells; And a cell current controller to control whether current paths are formed between ground terminals, wherein the cell current controller blocks the current path formation while the precharge unit precharges the bit line.

Cell Current Control Unit, Nonvolatile Memory Device

Description

Non volatile memory device and method of reading out

1A is a circuit diagram showing a part of a conventional nonvolatile memory device.

1B is a waveform diagram of a voltage applied during a read / verify operation of the nonvolatile memory device.

2 is a diagram illustrating a partial configuration of a nonvolatile memory device according to an embodiment of the present invention.

3 is a waveform diagram of a voltage applied during a read / verify operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

4 is a diagram illustrating a partial configuration of a nonvolatile memory device according to still another embodiment of the present invention.

Description of the main parts of the drawing

200: nonvolatile memory device.

210: precharge part

220: cell string

230: cell current controller

240: register section

The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device capable of reducing current consumption during a read or verify operation, and a read method thereof.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

The nonvolatile memory device typically includes a memory cell array having cells in which data is stored in a matrix form, and a page buffer for writing a memory to a specific cell of the memory cell array or reading a memory stored in a specific cell. . The page buffer may include a pair of bit lines connected to a specific memory cell, a register for temporarily storing data to be written to the memory cell array, or a register for reading and temporarily storing data of a specific cell from the memory cell array, a voltage of a specific bit line or a specific register. It includes a sensing node for sensing a level, a bit line selection unit for controlling the connection of the specific bit line and the sensing node.

The read or verify operation of the nonvolatile memory device uses a different threshold voltage distribution depending on whether a particular cell is programmed. That is, after precharging a bit line connected to a specific cell to a high level, data is sensed according to a principle that the voltage level of the bit line varies depending on whether or not a specific cell is programmed.

The time taken to precharge the bit line is determined by the size of the PMOS transistor precharging the bit line, the capacitance of the bit line, and the precharge voltage level. However, as the capacity of the memory increases recently, the size of the cell becomes smaller and the length of the bit line increases, thereby increasing the capacitance of the bit line, thereby increasing the time required for precharging. In order to solve this problem, there may be a method of increasing the PMOS transistor to reduce the precharge time, but there is a problem in that current consumption increases.

In order to solve the above-described problem, an object of the present invention is to provide a nonvolatile memory device including a control unit that can block whether a current path is formed during a read or verify operation. Another object of the present invention is to provide a method of reading the nonvolatile memory device.

A nonvolatile memory device of the present invention for achieving the above object is a cell including a precharge unit for applying a high level voltage to a bit line, and a plurality of serially connected memory cells connected between the bit line and the ground terminal. And a cell current controller for controlling whether a current path is formed between the bit line and the ground terminal, wherein the cell current controller blocks the current path formation while the precharge unit precharges the bit line. It is done.

In addition, the method of reading the nonvolatile memory device of the present invention includes precharging the bit line and preparing to form a current path through the cell string, and applying a high level control signal to the cell current controller to block the current path. And a step of evaluating a voltage level of a specific cell through a bit line according to the release of the current path blocking, wherein the preparation step applies a low level control signal to the cell current controller to establish a current path. It characterized in that it comprises a step of blocking.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1A is a circuit diagram showing a part of a conventional nonvolatile memory device, and FIG. 1B is a waveform diagram of a voltage applied during a read / verify operation of the nonvolatile memory device.

The nonvolatile memory device 100 may include a precharge unit 110 for precharging the bit line BL to a high level, a cell string 120 including memory cells, and a register unit for storing data sensed from a specific cell. 130.

The precharge unit 110 includes a PMOS transistor P110 connected between a power supply voltage terminal Vpre and a bit line. The PMOS transistor P110 applies a high level power supply voltage to the bit line in response to a low level precharge signal Prechb.

The cell string 120 includes a plurality of serially connected memory cells MC0,... MC1, and MCn that store data, and selectively select the bit line BL and the memory cell according to a drain select signal. And a drain select transistor DST for connecting and a source select transistor SST for selectively connecting the ground terminal and a memory cell according to a source select signal. A plurality of such cell strings are connected to form a memory cell.

Although the configuration of the memory cell array is not shown, word lines WL0, WL1,..., WLn, which select and activate the memory cells, and bit lines capable of inputting and outputting data of the memory cell are typically shown. (BLe0, BLo0, ..., BLem, BLom), and the plurality of word lines and the plurality of bit lines are arranged in a matrix form. Gates of the memory cells are connected to word lines, and a set of memory cells commonly connected to the same word line is called a page. A plurality of strings connected to each bit line are connected in parallel to a common source line to form a block.

The register unit 130 includes a latch for sensing and storing specific data according to the voltage level of the bit line. In the illustrated configuration, the input and output terminals of the inverters IV134 and IV136 include a latch configured to be connected.

A read or verify operation of the nonvolatile memory device will be described with reference to FIG. 1B.

First, a low level precharge signal Prechb is applied to precharge the bit line to a high level through the precharge unit 110 (T1).

Next, the low level precharge signal is transitioned back to the high level. In addition, a low level read / verify voltage is applied to the selected word line, and a high level read / verify voltage is applied to the remaining unselected word lines. At the same time, a high level drain select signal is applied to connect the bit line and the memory cell, and a high level source select signal is applied to connect the ground terminal and the memory cell (T2).

In this section, the voltage level of the bit line varies depending on whether a particular cell is programmed. When the cell to be read is a programmed cell, since the threshold voltage of the corresponding cell is higher than the read / verify voltage, the corresponding cell is not turned on and thus a current path from the bit line to the string cell and the ground terminal is not formed. Therefore, the voltage level of the bit line connected to the cell is maintained at the high level.

However, when the cell to be read is the erased cell, since the threshold voltage of the cell is lower than the read / verify voltage, the cell is turned on and a current path is formed from the bit line to the string cell and the ground terminal. Therefore, the voltage of the bit line that was precharged to the high level is discharged to the low level.

Next, the voltage level of the bit line is sensed and stored in the register unit 130. When the specific cell is a programmed cell, since the voltage level of the bit line is high level, low level data is stored in the latch by the inverter IV132. However, when the specific cell is an erased cell, since the voltage level of the bit line is low level, high level data is stored in the latch by the inverter IV132.

The read / verify operation of the prior art has the following problems. It is known that the precharge time T1 is determined by the following equation.

That is, as the capacitance C _BL of the bit line is large and the voltage level V to be precharged is large, the precharge time increases, and as the precharge current flowing through the PMOS transistor P110 increases, the precharge time decreases. do.

In addition, it is known that the sensing time T3 is determined by the following equation.

That is, the larger the capacitance C _BL of the bit line and the larger the precharged voltage level V, the longer the sensing time. The larger the cell current value Icell flowing through the cell string, the smaller the precharge time.

An object of the present invention is to provide a nonvolatile memory device capable of minimizing current consumption in a configuration in which the precharge current and the cell current are increased to reduce the precharge time and the sensing time.

2 is a diagram illustrating a partial configuration of a nonvolatile memory device according to an embodiment of the present invention.

The nonvolatile memory device 200 controls a precharge unit 210 for precharging the bit line BL to a high level, a cell string 220 including a memory cell, and whether to generate a current path of the cell string. The cell current controller 230 includes a register unit 240 in which data sensed from a specific cell is stored.

The precharge unit 210 includes a PMOS transistor P210 connected between a power supply voltage terminal Vpre and a bit line. The PMOS transistor P210 applies a high level power supply voltage to the bit line in response to a low level precharge signal Prechb.

The cell string 220 includes a plurality of serially connected memory cells MC0,..., MC1, and MCn storing data, and selectively selects the bit line BL and the memory cell according to a drain select signal. And a drain select transistor DST for connecting and a source select transistor SST for selectively connecting the ground terminal and a memory cell according to a source select signal. The cell string includes the cell current controller 230.

The cell current controller 230 controls whether a current path formed in the cell string is generated. For this purpose, an NMOS transistor (CST) connected between the memory cell and the source select transistor is included. The NMOS transistor is turned on according to the level of the control signal CS.

The register unit 240 includes a latch for sensing and storing specific data according to the voltage level of the bit line. In the illustrated configuration, the input and output terminals of the inverters IV244 and IV246 include a latch configured to be connected.

3 is a waveform diagram of a voltage applied during a read / verify operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

 First, a low level precharge signal Prechb is applied to precharge the bit line to a high level through the precharge unit 110 (T1).

At the same time, a low level read / verify voltage is applied to the selected word line and a high level read / verify voltage is applied to the remaining unselected word lines. In addition, a high level drain select signal is applied to connect the bit line and the memory cell, and a high level source select signal is applied to connect the ground terminal and the memory cell.

Next, the low level precharge signal is transitioned back to the high level. In addition, a high level control signal CS is applied to the cell current controller 230 (T2).

By this operation, the current path of the string cell is ready for formation. Therefore, the voltage level of the bit line is changed differently depending on whether the specific cell is programmed. That is, when the specific cell is programmed, the bit line maintains the precharge voltage. However, when the specific cell is erased, the voltage level of the bit line transitions to the low level.

Preferably, the voltage level of the control signal CS is applied at a voltage level higher than that of the drain selection signal or the source selection signal so that the voltage drop through the transistor CST of the cell current controller 230 becomes 0V.

Meanwhile, in order to increase the sensing speed, a method of further increasing the application time T2 of the control signal may be used. In addition, the sensing speed may be increased by increasing the transistor CST.

As such, the sensing speed may be changed by controlling various parameters of the cell current controller 230, and the amount of current consumption may be controlled.

4 is a diagram illustrating a partial configuration of a nonvolatile memory device according to still another embodiment of the present invention.

The overall configuration is similar to that of FIG. 2 except that bit line selection transistors VB and 420 may be further included to selectively control a connection between a specific bit line BL and the sensing node SO. Do.

The nonvolatile memory device 400 controls a precharge unit 410 for precharging the bit line BL to a high level, a cell string 430 including a memory cell, and whether to generate a current path of the cell string. The cell current controller 440 includes a register unit 450 in which data sensed from a specific cell is stored.

The overall operation principle also uses the technical idea of FIG. 3.

According to the configuration of the present invention described above, it is possible to freely control whether the current path is formed through the memory cell string. In addition, the sensing time may be adjusted by controlling the level, duration, and the like of the control signal supplied to the cell current controller, and the current consumption may be reduced.

Claims (9)

A precharge unit for applying a high level voltage to the bit line; A cell string connected between the bit line and the ground terminal and including a plurality of serially connected memory cells; And a cell current controller for controlling whether a current path is formed between the bit line and the ground terminal. And the cell current controller blocks the current path formation while the precharge unit precharges the bit line. 2. The nonvolatile memory as claimed in claim 1, wherein the cell string includes a drain select transistor for selectively connecting the bit line and a memory cell, and a source select transistor for selectively connecting the memory cell and a ground terminal. Device. The nonvolatile memory device of claim 1, wherein the cell current controller includes an NMOS transistor connected between a source select transistor and a memory cell. The nonvolatile memory device of claim 3, wherein the NMOS transistor of the cell current controller is turned on after precharging the bit line through the precharge unit. delete Preparing to form a current path through the cell string while precharging the bit line; Applying a high level control signal to the cell current controller to release the current path blocking; The voltage level of the specific cell is evaluated through the bit line according to the current path disconnection, And the preparing step includes applying a low level control signal to the cell current controller to cut off the current path. The method of claim 6, wherein the preparing comprises: connecting a bit line and a specific memory cell by applying a drain select signal having a high level; Connecting a ground terminal and a specific memory cell by applying a high level source select signal; Applying a read voltage to the selected word line; And applying a pass voltage to an unselected word line. delete 8. The method of claim 7, wherein the voltage level of the high level control signal is greater than the high level drain select signal and the high level source select signal.

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