KR100891406B1 - Method of erasing for non-Volatile Memory device - Google Patents

Abstract

The present invention relates to a method of erasing a nonvolatile memory device, comprising: a method of erasing a nonvolatile memory device including a memory cell array including at least one block including a multi-level cell, wherein all multi-blocks of the selected block are erased. Performing a program for the level cells to move the threshold voltage levels of all the multi-level cells to the highest level; A hard erase verification step of performing an erase operation and a verification on the preprogrammed memory block; A first soft program and verify step of performing soft program and verify on all word lines of the erased multi-level cell; And an nth soft program and a verification step of performing a soft program and verification by repeatedly dividing the first soft program into levels set for all word lines.

MLC, Soft Program

Description

Method of erasing nonvolatile memory device {Method of erasing for non-Volatile Memory device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an erase operation of a non-volatile memory device, and in particular, to improve cell distribution characteristics after an erase operation of a memory device having a multi-level cell (MLC). A method of erasing a memory device.

Recently, in order to further improve the density of such flash memories, studies on multiple bit cells capable of storing a plurality of data of one memory cell have been actively conducted. This type of memory cell is commonly referred to as a Multi Level Cell (MLC). In contrast, a single bit memory cell is referred to as a single level cell (SLC).

As described above, the MLC has a plurality of cell voltage levels for storing a plurality of bits of data, and means that data is stored differently according to each cell threshold voltage.

Therefore, when the erase operation is performed on the threshold voltage of a cell divided into a plurality of levels, the following process is performed.

First, a preprogram process is performed to collect cell threshold voltages that are divided into a plurality of cells into a cell distribution having the highest voltage level.

1A is a circuit diagram illustrating a voltage application during preprogramming for erasing a nonvolatile memory device.

Referring to FIG. 1A, a program voltage Vpgm is applied to a word line WL of all cells and a drain select line (DSL) of a drain select transistor (DST) for a pre-program process. The power supply voltage VDD is applied, and 0V is applied to the source select line SSL of the source select transistor SST. After 0V is applied to the substrate, a power supply voltage VDD is applied to the common ground line to perform a block unit program.

The block unit includes a plurality of word lines, and a general nonvolatile memory device includes a memory cell array (not shown) including a plurality of the above blocks. FIG. 1A is a diagram illustrating only a portion of strings to indicate voltage application during preprogramming.

As described above, when the voltage is applied and the program operation is performed, all the cells are collected in the cell distribution of the higher voltage level as mentioned above.

The erase operation is performed on the cell distributions.

1B is a circuit diagram illustrating a voltage application for erasing a nonvolatile memory device.

Referring to FIG. 1B, for erasing, the DSL and SSL are floated, 0 V is applied to all word lines WL, and a high voltage of 20 V is applied to the substrate Well. When such a voltage is applied, the data of all the memory cells of the block are erased, and the threshold voltage of the cell also falls below 0V. At this time, if the erase is excessively performed according to the characteristics of the memory cells, the threshold voltage falls far below the desired cell threshold voltage.

To correct this, run a soft program.

1C is a circuit diagram illustrating a voltage application during soft program for erasing a nonvolatile memory device.

Referring to FIG. 1C, 0 V is applied to a substrate, a power supply voltage VDD is applied to a DSL, and 0 V is applied to an SSL for a soft program. The program voltage Vpgm is applied to all word lines WL so that the excessively lowered threshold voltage is 0V or less and is not too low, that is, programmed to have a desired cell width. At this time, the program voltage Vpgm is a low voltage so that cells are not programmed above 0V.

After the soft program is performed as shown in FIG. 1C, verification is performed.

FIG. 1D is a circuit diagram illustrating a voltage application for the verify operation after the soft program of FIG. 1C.

Referring to FIG. 1D, the verifying operation is performed by a column by column in a block unit. DSL and SSL apply a power supply voltage (VDD) to each column and apply 0V to all word lines. It is determined whether the program is properly executed by performing the operation. At this time, the determination that the soft program has passed is determined that even if one memory cell passes the verification voltage, the entire column including the memory cell is passed.

When the erase operation of the multi-level cell is performed in the above-described manner, since the cell erase is performed in units of blocks and the unit is verified in units of columns, the cell distribution when the erasing is completed is not narrowed. The interference effect affects the surrounding cell threshold voltage, which widens the overall cell distribution characteristics.

In order to solve this problem, the verification operation may be performed by bit by bit. However, when the bit by bit method is used, verification may take a long time, thereby reducing the overall efficiency.

Accordingly, a technical problem of the present invention is to propose a new method for performing a soft program verification during an erase operation of a multi-level cell, and to erase the cells with a narrower cell distribution, thereby reducing the cell interference effect and improving the performance of the memory device. The present invention provides a method of erasing a nonvolatile memory device.

In order to solve the problem of the present invention, a nonvolatile memory device erase method,

A method of erasing a nonvolatile memory device including a memory cell array including one or more blocks including multi-level cells, the method comprising: performing a program for all multi-level cells of a block selected for erasing, thereby A pre-programming step of moving the threshold voltage level to the highest level; A hard erase verification step of performing an erase operation and a verification on the preprogrammed memory block; A first soft program and verify step of performing a soft program and verify on the memory block; Dividing the memory block into first and second groups when the verification result passes; Performing verification on the first group, and performing a soft program and verification if the path is not passed; And if the verification result for the first group passes, performing verification on the second group, and if not, performing a soft program and verification.

In addition, for another method of erasing the nonvolatile memory device of the present invention,

A method of erasing a nonvolatile memory device including a memory cell array including one or more blocks including multi-level cells, the method comprising: performing a program for all multi-level cells of a block selected for erasing, thereby A pre-programming step of moving the threshold voltage level to the highest level; A hard erase verification step of performing an erase operation and a verification on the preprogrammed memory block; A first soft program and verify step of performing a soft program and verify on the memory block; Dividing the memory block into first and second groups when the verification result passes; Performing verification on the first and second groups and flagging a group that has not passed; And performing a soft program and verification on the flagged group of the first and second groups.

As described above, the erase method of the nonvolatile memory device according to the present invention can narrow the erase cell distribution after the erase operation of the multi-level cell, thereby reducing the interference effect during subsequent programming and increasing the efficiency.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

FIG. 2A is a diagram illustrating a movement of a cell distribution according to a preprogram for an erase operation of a nonvolatile memory device, and FIG. 2B is a diagram of a movement of a cell distribution according to an erase operation after a preprogram of FIG. 2A. FIG. 2C is a diagram illustrating a movement of cell distribution according to the soft program operation after the erase operation of FIG. 2B.

Referring to FIG. 2A, each of the multi-level cells has a plurality of cell distributions 201 to 210 according to the program state. Therefore, for erasing, a pre-program is first performed to collect a plurality of cell distributions 201 to 210 into the highest level cell distribution 210.

Pre-programming is performed in units of blocks of a memory cell array (not shown) included in a nonvolatile memory device. A program voltage Vpgm is applied to all word lines WL, and a drain select line is applied. A power supply voltage VDD is applied to a line DSL, and 0V is applied to a source select line SSL to perform a program.

Therefore, when the preprogram is completed, all cell distributions 201 to 203 are gathered into the highest level cell distribution 210.

The erase operation is performed on the cell distribution 210 collected at the highest level. The cell distribution that changes according to the erase operation is shown in FIG. 2B.

Referring to FIG. 2B, when the erase operation is performed on the highest level 210, all cells collected in the cell distribution 210 of the highest level are erased to 0 V or less and moved 220. In detail, the erase operation is performed in units of blocks. After applying a high voltage of 20V or higher to the substrate Well and applying 0V to all word lines WL, the erase operation is performed by floating the DSL and SSL. Memory cells on which the erase operation is performed move below the erase reference voltage HEV.

A soft program is performed to correct memory cells moved below the erasing reference voltage HEV to form a narrow memory cell distribution as shown in FIG. 2C.

Referring to FIG. 2C, the memory cells 220 erased below the erase reference voltage HEV may be over erased. Therefore, a soft program is performed and corrected by the narrow distribution memory cell 230 using the verification voltage Pv.

As described above, a method of erasing the memory cells 230 having a narrow distribution is made by the following soft program operation.

3 is a block diagram illustrating a soft program operation flow according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a soft program operation according to an embodiment of the present invention first performs a soft program on all the memory blocks 301 and performs verification by a column scan method.

If the verification result for the soft program for the entire memory block 301 is passed, then the memory block 301 is divided into first and second groups 302 and 303. In an embodiment of the present invention, the first group 302 and the second group 303 are divided into half of all word lines (WL0 to WL15 and WL16 to WL31). If the soft program passes, even if one memory cell passes by the verify voltage, it is determined that the entire column including the corresponding memory cell has passed.

After verifying the first and second groups 302 and 303, the soft program is performed again for the group that has not been passed. In this case, the verification method uses the column method, but the pass voltage is provided to the word lines of the unselected group so as to be unaffected.

That is, the first group 302 is first verified, and if not passed, the first group 302 is soft programmed until the pass is verified. If the verification result for the first group 302 passes, the verification is also performed for the second group 303 first, and if not, a soft program is performed.

In a manner different from that described above, verification is performed on the first group 302 and the second group 303 in order, and a group that has not been passed is indicated using a flag, and then the first and second groups 302, After the verification of 303), a method of selectively executing the soft program for the flagged group may be used.

After the soft program for the first and second groups 302 and 303 is finished, the first and second groups 302 and 303 are divided into the third and fourth groups 304 and 305 and the fifth and sixth groups 306 and 306, respectively. 307). According to an embodiment of the present invention, the third group 304 includes first to seventh word lines WL0 to WL7, and the fourth group 305 includes eighth to fifteen word lines WL8 to WL15. The fifth group 306 includes sixteenth to twenty-third word lines WL16 to WL23, and the sixth group 307 includes twenty-fourth to thirty-first word lines WL24 to WL31.

As described above, the third to sixth groups 304 to 307 are also verified for each group so that the non-passed group performs the soft program until the pass.

Alternatively, the verification of the third to sixth groups 304 to 307 may be performed to flag only the unpassed groups, and then a method of executing a soft program for the flagged groups may be applied. The group may be divided arbitrarily, and in the exemplary embodiment of the present invention, the group is expressed by dividing the group by dividing the word lines by 1/2 for convenience.

The soft program and the verification are performed as follows, so that an unselected area is not programmed and does not affect the verification result.

4A is a circuit diagram illustrating a voltage application during soft programming according to an exemplary embodiment of the present invention.

Referring to FIG. 4A, a flash memory device according to an embodiment of the present invention is connected to a memory cell array 410 including memory cells and connected to the memory cell array 410 to operate for a program, an erase, a read operation, or the like. And a controller 430 for controlling the peripheral circuit unit 420 and the peripheral circuit unit 420.

The memory cell array 410 includes a plurality of cell strings in which a plurality of memory cells are connected in series between a drain select transistor (DST) and a source select transistor (SST), and each cell The string is connected to the bit line.

The gates of the drain select transistors of the cell strings are commonly connected to a drain select line DSL, and the gates of the source select transistors are commonly connected to a source select line SSL.

In addition, gates of the memory cells are connected to word lines WL <0> to WL <31> in the horizontal direction, respectively. According to an exemplary embodiment of the present invention, as shown in FIG. 3, the memory cell array 410 includes first to sixteenth word lines WL <0> to WL <15> as a first group 302. The seventeenth to thirty first word lines WL <16> WL <31> are divided into a second group 303.

The peripheral circuit unit 420 stores data in the memory cell array 410 or reads data stored in the memory cell array 410 according to an operation command. The peripheral circuit unit 420 includes a page buffer circuit, an X decoder, a Y decoder, and the like.

The controller 430 provides a control signal for controlling the operation of the peripheral circuit unit 420, and includes a storage unit 431 for storing flag information according to a program or erase state of the memory cell array 410.

According to the exemplary embodiment of the present invention as described above, a case in which the soft program is executed in the first group 302 when divided into the first group 302 and the second group 303 is provided. The program voltage Vpgm is applied to the selected word lines WL0 to WL15, and the pass voltage Vpass is applied to the word lines WL16 to WL31 which are not selected.

Therefore, the word lines WL16 to WL31 that are not selected are prevented because the program is prevented. When the verification is performed after the program, the voltage is applied as follows.

4B is a circuit diagram illustrating a voltage application for verification after the soft program of FIG. 4A.

Referring to FIG. 4B, the word lines WL0 to WL15 selected for the soft program apply 0V, and the read voltage Vread is applied to the unselected word lines WL16 to WL31 to not affect the verification result. Do not

An erase cell having a narrow cell distribution is generated by the soft program according to the exemplary embodiment described above. The soft program method is divided into sub-groups, and the verification results are mostly passed by the soft program toward the second half, and the number of times the program voltage is applied is reduced. This narrows the overall cell threshold voltage distribution.

The soft program method mentioned above has largely been described in two ways. Each of these methods will be described according to an embodiment as follows.

5A and 5B are operational flowcharts of a soft program method according to a first embodiment of the present invention. FIG. 5B is a flowchart illustrating the operation following FIG. 5A. In the following operation description, the soft program is performed as shown in FIG. 4A, and the verification is performed as shown in FIG. 4B.

First, referring to FIG. 5A, in the soft program method according to the first embodiment of the present invention, after erasing is performed on all memory blocks (S501), the first soft program and verification are performed on all memory blocks (S501). S503, S505). The first soft program executes until it passes through the entire memory block.

When the first soft program and the verification of the entire memory block are completed, the memory block is divided into first and second groups (S507), and the verification is performed on the first group (S509 and S511). . If the first group does not pass the verification as a result of confirming the pass in step S511, the second soft program is repeated until the pass (S513, S511). If the verification result passes for the first group, the second group is verified (S515). The first and second groups are divided as shown in FIG.

Also for the second group, the verification is repeated with the second soft program until the verification result passes (S517 and S519). When the verification passes for the first and second groups are performed, the first group is divided into third and fourth groups, and the second group is divided into fifth and sixth groups (S521).

The soft program for the third to sixth groups is shown in FIG. 5B. Referring to FIG. 5B, first, a verification is performed on the third group (S523).

When the verification pass for the third group is made in step S523 (S525), the fourth group is verified (S531). However, if the third group has not passed, verification is performed by executing the third soft program (S527). The step S527 is repeated until the verification pass for the third group (S529, S527).

When the verification result for the third group passes, the verification for the fourth group is performed (S531). When the verification result for the fourth group passes (S533), the verification for the fifth group is performed (S533). S539), when the verification pass for the fifth group is performed, verification for the sixth group is performed (S547).

In addition, similarly to the third group, if the verification result does not pass for each of the fourth to sixth groups, the third program is executed to pass the verification result.

The first embodiment of the present invention according to FIGS. 5A and 5B divides the memory block into first and second groups so that the second soft program is executed until each group becomes the verification pass, and the first to second operations are performed. The third to sixth groups in which the groups are divided also execute the third soft program until they each have a verification pass. At this time, each group first performs verification to determine whether it passes or not, and executes a soft program only when it does not pass.

6A and 6B are flowcharts illustrating a soft program method according to a second embodiment of the present invention. FIG. 6B is a flowchart illustrating the operation following FIG. 6A. In the following operation description, the soft program is performed as shown in FIG. 4A, and the verification is performed as shown in FIG. 4B.

Referring to FIG. 6A, in the soft program method according to the second embodiment of the present invention, after erasing is performed on all memory blocks (S601), first soft programming and verification are performed on all memory blocks (S603, S605). The first soft program executes until it passes through the entire memory block.

If the soft program verification for the entire memory block passes, the memory block is divided into first and second groups (S607). The first and second groups are divided as shown in FIG. 3 above.

The first group is verified (S609), and when the verification result passes (S611), the second group is verified next (S613). However, if the verification result of the first group does not pass, this is indicated by using flag information of the first group (S613). At this time, the flag display may be stored in the storage means 431 of the controller 430 or by using means for storing separate flag information.

When the verification of the first group is completed, the second group is verified (S615). If the verification result is not passed (S617), a flag is displayed (S619).

When the verification of the first and second groups is completed, check whether there is a flagged group (S621), and if there is a flagged group, perform verification with the second soft program so that the verification result is a pass for the group. (S623, S625). At this time, the control unit 430 resets the flag of the group that has become the verification path through the second soft program.

If both the first and second groups pass the verification result, each group is divided into third and fourth groups and fifth and sixth groups (S627). In this case, the third to sixth groups may be divided as shown in FIG. 3. That is, the third group includes first to eighth word lines WL <0> to WL <7>, and the fourth group includes ninth to sixteenth word lines WL <9> to WL <16>. And a fifth group includes seventeenth to twenty-fourth wordlines WL <17> to WL <24>, and a sixth group includes twenty-fifth to thirtieth wordlines WL <25> to WL <31>. ).

The soft program for the third to sixth groups is shown in Figure 6b. Referring to FIG. 6B, first, verification is performed on the third group (S629), and if not passed (S631), a flag is displayed (S633).

After the third group, the fourth group, the fifth group, and the sixth group are verified to flag the group that has not passed (S635 to S651). After verifying all the third to sixth groups, it is checked whether there is a flagged group among the four groups (S653), and it is checked whether there is a flagged group (S653).

As a result of checking in step S653, if there is a flagged group, only that group executes and verifies the third soft program (S655, S657). The group passed by executing the third soft program releases the flag display. If all of the third to sixth groups pass, the soft program process ends. 5A, 5B, 6A, and 6B illustrate a case in which only a soft program up to a process of dividing a memory block into first and second groups and dividing into a third to sixth groups is performed. It is also possible to divide groups.

As in the first embodiment, each group is verified, and if it is not passed, a method of performing a process of verifying the next group after the pass is performed through a soft program is performed. Similarly, verification can be given to all groups first, flagged groups that have not been passed, and then only soft flagged groups can be programmed. The first and second embodiments are

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A is a circuit diagram illustrating a voltage application during preprogramming for erasing a nonvolatile memory device.

1B is a circuit diagram illustrating a voltage application for erasing a nonvolatile memory device.

1C is a circuit diagram illustrating a voltage application during soft program for erasing a nonvolatile memory device.

FIG. 1D is a circuit diagram illustrating a voltage application for the verify operation after the soft program of FIG. 1C.

FIG. 2A is a diagram illustrating a movement of a cell distribution according to a free program for an erase operation of a nonvolatile memory device.

FIG. 2B is a diagram illustrating the movement of cells according to the erase operation after the preprogram of FIG. 2A.

FIG. 2C is a diagram illustrating a movement of cell distribution according to the soft program operation after the erase operation of FIG. 2B.

3 is a block diagram illustrating a soft program operation flow according to an exemplary embodiment of the present invention.

4A is a circuit diagram illustrating a voltage application during soft programming according to an exemplary embodiment of the present invention.

FIG. 4B is a circuit diagram illustrating a voltage application for verification after the soft program of FIG. 4A.

5A and 5B are operational flowcharts of a soft program method according to a first embodiment of the present invention.

6A and 6B are flowcharts illustrating a soft program method according to a second embodiment of the present invention.

Claims (15)

A method of erasing a nonvolatile memory device including a memory cell array including one or more blocks including multi-level cells, the method comprising: Performing a program for all multi-level cells of the block selected for erasing to move the threshold voltage levels of all multi-level cells to the highest level; A hard erase verification step of performing an erase operation and a verification on the preprogrammed memory block; A first soft program and verify step of performing a soft program and verify on the memory block when the hard erase verify passes; Dividing the memory block into first and second groups when the verification result passes; Performing verification on the first group, and performing a soft program and verification if the path is not passed; And Performing a verification on the second group when the verification result for the first group passes, and performing a soft program and verification on the second group if the verification result does not pass Erasing method of a nonvolatile memory device comprising a. The method of claim 1, And the verification is performed in the same way as the verification for the soft program. The method of claim 1, The pre-program step, Applying a program voltage to all word lines of the selected block; Applying a power supply voltage to a drain select line of the selected block; Applying 0V to a source select line of the selected block; And And performing a program on the selected block. The method of claim 1, The erasing step, Applying 0V to the word line of the selected block; Floating the drain select line and the source select line of the selected block; And  Erasing by applying a high voltage to the substrate (or well). The method of claim 1, The soft program, Applying a program voltage to a word line selected for soft program in the selected block; Applying a pass voltage to an unselected word line except for the selected word line; And And applying a power supply voltage to a drain select line of the selected block, applying 0V to a source select line, and performing a program. The method of claim 1, Verification after the soft program, Applying 0V to the selected word line on which the soft program is performed in the selected block; Applying a pass voltage to an unselected word line other than the selected word line; and And applying a power supply voltage to the drain select line and the source select line of the selected block, and performing verification. The method of claim 1, Dividing the first and second groups into subgroups, respectively; And Performing verification for any one of the divided groups, and if not passed, performing a soft program and verification to perform the same process for the next group after passing. Erasing Method of Memory Device. A method of erasing a nonvolatile memory device including a memory cell array including one or more blocks including multi-level cells, the method comprising: Performing a program for all multi-level cells of the block selected for erasing to move the threshold voltage levels of all multi-level cells to the highest level; A hard erase and verify step of performing an erase and verify operation on the pre-programmed memory block; A first soft program and verify step of performing a soft program and verify on the memory block if the hard erase verify passes; Dividing the memory block into first and second groups when the verification result passes; Performing verification on the first and second groups and flagging a group that has not passed; And Performing a soft program and verification on a flagged group of the first and second groups Erasing method of a nonvolatile memory device comprising a. The method of claim 8, And the verification is performed in the same way as the verification for the soft program. The method of claim 8, The pre-program step, Applying a program voltage to all word lines of the selected block; Applying a power supply voltage to a drain select line of the selected block; Applying 0V to a source select line of the selected block; And And performing a program on the selected block. The method of claim 8, The erasing step, Applying 0V to the word line of the selected block; Floating a drain select line and a source select line of the selected block; And And erasing by applying a high voltage to a commercially available (or well) device. The method of claim 8, The soft program, Applying a program voltage to word lines of a flagged group of the selected memory block; Applying a pass voltage to a word line of an un flagged group of the selected memory block; And And applying a power supply voltage to the drain select line of the selected group, applying 0V to a source select line, and performing a program. The method of claim 8, Verification after the soft program, Applying 0V to a wordline of a flagged group of the selected memory block; Applying a pass voltage to a word line of an un flagged group of the selected memory block; And And applying a power supply voltage to the drain select line and the source select line of the selected block, and performing verification. The method of claim 8, Dividing the first and second groups into subgroups, respectively, by a verification result of the soft program for the flagged group; Performing verification on each of the divided groups in order, and flagging groups that are not passed; And Performing a soft program and verification on the flagged groups Erasing method of a nonvolatile memory device comprising a. The method of claim 14, And performing a soft program and verification on the flagged groups, wherein the passed group deletes a flag indication.

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