KR100891244B1 - Method of forming a semiconductor device - Google Patents

Abstract

The present invention relates to a method of forming a semiconductor device,

In order to solve the problem that when forming the insulating film spacer on the conductive wiring sidewalls, it is difficult to form a predetermined thickness due to the high level difference of the conductive wiring due to the high integration,

Forming conductive wirings having a barrier metal layer, a conductive wiring conductive layer, and a hard mask layer stacked structure on the semiconductor substrate, and forming a first insulating spacer on the sidewall of the conductive wiring; and then exposing the semiconductor substrate exposed between the conductive wirings. The process of epitaxially growing the metal layer and forming the second insulating layer spacer on the sidewall of the conductive wiring reduces parasitic capacitance induced between the bit line and the peripheral layer, and improves the characteristics and reliability of the device.

Description

A method for forming a semiconductor device

1 is a layout diagram of a semiconductor device designed up to a bit line forming process.

FIG. 2 is a cross-sectional view of a bit line according to the prior art along the cutting line ⓐ-ⓐ of FIG.

3A to 3H are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

11,31: Lower insulating layer 13,33: Landing plug contact hole

15,35: landing plug 17,37: barrier metal layer

19,39: Bit line conductive layer, W 21,41: Hard mask layer

23: first insulating film spacer 25: second insulating film spacer

43: first insulating film 45: second insulating film

47: storage electrode contact plug 49: etching barrier layer

51 oxide film for storage electrode 53 storage electrode region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device. In particular, a capacitor formed of a structure of a conductive layer, an insulating film, and a conductive layer is not formed in a predetermined portion, and an insulating film between conductive layers is provided to form a capacitor according to high integration of the semiconductor device. For example, the present invention relates to a method for reducing capacitance of a capacitor having an insulating film between the bit line and the bit line.

FIG. 1 is a layout diagram illustrating the formation of a general semiconductor device, and includes an active region 100, a word line region 200, a bit line contact region 300, a bit line region 400, a storage electrode contact region 500, and The storage electrode region 600 is designed.

FIG. 2 is a cross-sectional view illustrating a method of forming a semiconductor device according to the prior art, and is shown along the line ⓐ-ⓐ of FIG. 1.

First, an isolation layer (not shown) defining an active region is formed on the semiconductor substrate (not shown).

A gate oxide film (not shown), a gate electrode polysilicon film (not shown), a gate electrode metal layer (not shown), and a hard mask layer (not shown) are formed on the semiconductor substrate.

The stacked structure is etched by a photolithography process using a gate electrode mask to form a gate electrode (not shown).

An insulating layer spacer (not shown) is formed on sidewalls of the gate electrode, and a source / drain junction region (not shown) is formed by performing an ion implantation process of impurities on the semiconductor substrate.                         

The landing plug contact hole 13 exposing the semiconductor substrate of the active region is formed by a photolithography process using a landing plug contact mask (not shown) that forms the lower insulating layer 11 on the entire surface and exposes the active region. do.

A landing plug poly (not shown) filling the landing plug contact hole 13 is formed on the entire surface.

The landing plug poly is planarized and etched to expose the hard mask layer to form the landing plug 15.

An interlayer insulating layer (not shown) is formed over the entire surface, and a bit line contact hole (not shown) is formed to expose the landing plug 15 by a self-aligned etching process using a bit line contact mask (not shown).

A bit line contact plug (not shown) filling the bit line contact hole is formed and a bit line connected thereto is formed. In this case, the bit line is formed of a stacked structure of the barrier metal layer 17, the bit line conductive layer 19, and the hard mask layer 21, and the first insulating layer spacer 23, which is an oxide layer, and the second nitride layer, are formed on the sidewalls thereof. The insulating film spacer 25 is provided.

At this time, it is difficult to form a predetermined thickness due to the step of the high bit line during the process of the spacer (23, 25).

In a subsequent step, an interlayer insulating film (not shown) is formed to planarize the entire top surface.

In the photolithography process using a storage electrode contact mask, an interlayer insulating film between the bit lines is self-aligned to form a storage electrode contact hole exposing the landing plug poly. At this time, the second insulating layer spacer 25 is etched to become thinner than the thickness at the time of formation.

A storage electrode contact plug for filling the storage electrode contact hole is formed, and a capacitor connected thereto is formed.

As described above, a method of forming a semiconductor device according to the prior art,

The insulating layer spacer formed on the sidewalls of the bit lines is etched in a subsequent contact process to form a thin layer so that the distance between the storage electrode contact plugs formed between the bit lines is closer than the predetermined distance and the capacitance is increased, thereby improving the characteristics and reliability of the device. There is a problem of deterioration.

In order to solve this problem, when the insulating film spacers on the sidewalls of the bit lines are formed to be thicker, there is a problem in that a subsequent contact process is difficult and the contact resistance increases accordingly.

The present invention provides a semiconductor device for maintaining the thickness of the second insulating film spacers by reducing the height of the second insulating film spacers during the process of forming the second insulating film spacers on the sidewalls of the bit line to reduce the etching process time. The purpose is to provide a formation method.

In order to achieve the above object, a method of forming a semiconductor device according to the present invention,
Forming a conductive wiring of a barrier metal layer, a conductive wiring conductive layer, and a hard mask layer stacked structure on a semiconductor substrate;
Forming a first insulating film spacer on sidewalls of the conductive wirings;
Epitaxially growing the semiconductor substrate exposed between the conductive wirings by the thickness of the barrier metal layer;

Forming a second insulating film spacer on the sidewall of the conductive wiring;

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The barrier metal layer is formed to a thickness of 10 to 500 Å,

The conductive wiring conductive layer is formed of tungsten having a thickness of 100 to 1000 GPa or 10 to 100 GPa,

The hard mask layer is formed to a thickness of 400 ~ 3000 Å,

The first insulating film spacer is formed of a nitride film 10 to 50 Å thickness,

The second insulating film spacer is formed of an oxide-based or nitride-based insulating film having a thickness of 10 to 50 kHz,

The epitaxial growth process is a first feature of using at least one of SiH 4, SiHCl 3, SiH 2 Cl 2, SiH 3 Cl or SiCl 4 as a source gas.

In addition, the method of forming a semiconductor device according to the present invention to achieve the above object,

Forming a bit line having a barrier metal layer, a conductive wiring conductive layer, and a hard mask layer stacked structure on a lower insulating layer having a landing plug;

Forming a first insulating film spacer on sidewalls of the bit lines;

Epitaxially growing a landing plug exposed between the bit lines by the thickness of the barrier metal layer;

A second feature is a step of forming a second insulating film spacer on the sidewall of the bit line.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3A to 3H are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention, and are shown along the cutting line ⓐ-ⓐ of FIG. 1.

Referring to FIG. 3A, an isolation layer (not shown) defining an active region is formed on the semiconductor substrate (not shown).

In addition, a lower insulating layer 31 having a gate electrode, a landing plug contact hole 13, and a landing plug 33 filling the same is formed on the semiconductor substrate.

Bit lines are formed over the entire surface. In this case, the bit line is formed in a stacked structure of the barrier metal layer 37, the bit line conductive layer 39, and the hard mask layer 41.

The barrier metal layer 37 is formed to a thickness of 10 to 500 kPa, the conductive layer 39 for the bit line is formed of tungsten having a thickness of 100 to 1000 kPa, and the hard mask layer 41 is 400 to 3000 kPa thick. It is formed of a nitride film.

In addition, the thickness of the conductive layer for bit lines formed of the tungsten may be reduced to a thickness of 10 to 100 GPa to reduce the surface area.

A nitride film, which is the first insulating film 43, is deposited on the entire surface with a thickness of 10 to 50 GPa.

Referring to FIG. 3B, the first insulating layer 43 is anisotropically etched to form a first insulating layer 43 spacer on the sidewall of the bit line, and expose the landing plug 35 between the spacers of the first insulating layer 43. .

Referring to FIG. 3C, the exposed landing plug 35 is epitaxially grown, but only by the height of the barrier metal layer 37. At this time, the epitaxial growth method is carried out using at least one of SiH4, SiHCl3, SiH2Cl2, SiH3Cl or SiCl4 as the source gas.

Referring to FIG. 3D, a second insulating layer 45 is deposited on the entire surface at a predetermined thickness. In this case, the second insulating layer 45 is formed of an oxide film or a nitride film.

Referring to FIG. 3E, the second insulating layer 45 is anisotropically etched to form a second insulating layer 45 spacer on the sidewalls of the first insulating layer 43 of the bit line sidewalls.

Referring to FIG. 3F, a storage electrode contact plug 47 connected to the landing plug 35 exposed between the spacers of the second insulating layer 45 is formed.

In this case, the storage electrode contact plug 47 forms a second insulating layer 45 spacer on the sidewall of the bit line and an interlayer insulating layer (not shown) to planarize the entire surface, and then the storage electrode contact mask ( (Not shown) to etch the interlayer insulating layer to expose the landing plug 35 and to deposit a conductive layer for a storage electrode contact plug connected to the landing plug 35, and then The planarization etching process is performed until the hard mask layer 41 is exposed.

In addition, the storage electrode contact plug 47 may planarize an interlayer insulating layer formed after the second insulating layer 45 spacer forming process, and the hard electrode layer 41 may be exposed to expose the storage electrode contact mask (not shown). After forming a storage electrode contact hole by performing a self-aligned contact process by a photolithography process using a photolithography process, a conductive layer for a storage electrode contact plug filling the same is formed on the entire surface, and the hard mask layer 41 is exposed. It may be formed by a planarization etching process.

Referring to FIG. 3G, a nitride film, which is an etch barrier layer 49, is formed on the entire surface.

Referring to FIG. 3H, an oxide layer 51 for a storage electrode is deposited on the etch barrier layer 49. At this time, the storage electrode oxide film 51 is formed to a thickness of 15000 ~ 20000 Å.

The storage electrode region 53 exposing the storage electrode contact plug 47 is formed by etching the storage electrode oxide layer 51 and the etching barrier layer 49 by a photolithography process using a storage electrode mask (not shown). do. In this case, the storage electrode region 53 refers to a region where the storage electrode is to be formed.

In a subsequent process, a capacitor (not shown) connected to the storage electrode contact plug 47 is formed.

According to another embodiment of the present invention, when the first and second insulating film spacers are formed on the sidewalls after the word line forming process, the first insulating film spacers are formed, the exposed semiconductor substrate is epitaxially grown, and the second insulating film spacer is subsequently processed. To form.

As described above, in the method of forming a semiconductor device according to the present invention, the first insulating film spacer is formed on the sidewalls of the conductive wiring, the conductive layer between the conductive wirings is epitaxially grown to a predetermined thickness, and then the second insulating film spacer is formed. The thickness of the insulating layer spacers between the conductive wirings is increased by reducing the depth during the etching process for forming the second insulating layer spacers, thereby reducing the parasitic capacitance and thereby improving the characteristics and reliability of the device.

Claims (8)

Forming a conductive wiring of a barrier metal layer, a conductive wiring conductive layer, and a hard mask layer stacked structure on a semiconductor substrate; Forming a first insulating film spacer on sidewalls of the conductive wirings; Epitaxially growing the semiconductor substrate exposed between the conductive wirings by the thickness of the barrier metal layer; And forming a second insulating film spacer on the sidewall of the conductive wiring. The method of claim 1, The barrier metal layer is a method of forming a semiconductor device, characterized in that formed to a thickness of 10 to 500 kHz. The method of claim 1, The conductive wiring conductive layer is formed of tungsten having a thickness of 10 to 1000 GPa. The method of claim 1, The hard mask layer is a method of forming a semiconductor device, characterized in that formed to a thickness of 400 ~ 3000 Å. The method of claim 1, And the first insulating film spacer is formed of a nitride film having a thickness of 10 to 50 kHz. The method of claim 1, And the second insulating film spacer is formed of an oxide-based or nitride-based insulating film having a thickness of 10 to 50 GPa. The method of claim 1, The epitaxial growth process is performed using at least one of SiH4, SiHCl3, SiH2Cl2, SiH3Cl or SiCl4 as the source gas. Forming a bit line having a barrier metal layer, a conductive wiring conductive layer, and a hard mask layer stacked structure on a lower insulating layer having a landing plug; Forming a first insulating film spacer on sidewalls of the bit lines; Epitaxially growing a landing plug exposed between the bit lines by the thickness of the barrier metal layer; And forming a second insulating film spacer on the sidewalls of the bit line.

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