KR100879436B1 - Voltage regulators, their error amplifiers, and their control loop stabilization methods - Google Patents

Abstract

The control loop of the voltage regulator can be stabilized using a minimum silicon area. The current limit signal generated by the current regulator control loop of the voltage regulator is distributed to minimize the zero provided to the compensation set with respect to the voltage control loop to stabilize both loops. The compensation set may include a resistor (zero) and a capacitor (pole) connected in series between the output and input terminals of the amplifier. The distribution of the current limiting signal may include applying a first portion of the current limiting signal to the first side of the resistor and applying a second portion of the current limiting signal to the second side of the resistor. The ratio of the first portion to the second portion can be based on the gain of the amplifier, thereby minimizing the effect of resistance.

Voltage, regulator, error, amplifier, compensation

Description

Voltage regulator, its error amplifier, and control loop stabilization method {ZERO CANCELLATION IN MULTILOOP REGULATOR CONTROL SCHEME}

1A shows a simple DC voltage regulator that includes a voltage control loop.

1B shows a voltage regulator comprising a voltage control loop and a current limiting loop.

1C shows the board plot of the poles and the corresponding phase shift.

1D shows a zero plot of the board and the corresponding phase shift.

1E shows a board plot with multiple poles and zeros and corresponding phase shifts.

FIG. 2 shows an embodiment of a voltage regulator that includes a latometric branch compensation circuit, which may provide a single compensation solution for both the voltage control loop and the current limit loop.

3 illustrates one embodiment of an error amplifier that includes the implementation of a rationometric branch compensation circuit.

Drawing elements having the same number may be specified in a similar configuration.

The present invention relates to a DC voltage regulator and in particular to an error amplifier of a DC voltage regulator. The error amplifier according to the invention has the advantage of including a single compensation solution for both the voltage control loop and the current limit control loop.

Typical DC voltage regulators employ a voltage control loop that stabilizes the output voltage for various conditions. 1A is a diagram illustrating a conventional DC voltage regulator 100 (hereinafter referred to as "regulator"). In the regulator 100, the error amplifier 102 applies its output to the output driver 103. Output driver 103 typically includes hundreds or thousands of transistors. The voltage VOUT in turn drives the load 110 having both the resistive component 105 and the capacitive component 106. In a typical embodiment, the load 110 is disposed outside of the integrated circuit implementing the regulator 100.

In the regulator 100, the voltage control loop includes resistors 108 and 109 connected in series between VOUT and the node providing the voltage supply VSS. The node 111 disposed between the resistors 108 and 109 provides a feedback voltage to the negative input terminal of the error amplifier 102. In this arrangement, the error amplifier 102 can measure (ie sample) the output voltage VOUT using a resistive divider, thereby making it easy to equalize the voltage input to the error amplifier 102. This voltage control loop is provided for the normal operating conditions of the regulator 100.

Standard regulators can also include a control loop for overcurrent conditions, which can destroy the regulator as well as the IC in which the regulator is formed. For example, FIG. 1B illustrates one embodiment of a current limiting circuit 104 that may be added to the regulator 100 to form a calibrated regulator 100 '. The current limiting circuit 104 may include two PNP transistors 121 and 122 connected in series between the resistor 120 and the amplifier 123. The two PNP transistors 121 and 122 receive the output of the power supply 103 at its base. The resistor 120 is connected between the emitter of the PNP transistor 121 and the source voltage VCC. The amplifier 123 receives a first input from the source voltage VCC, receives a second input from the emitter of the PNP transistor 121, and receives a third input from the collector of the PNP transistor 122.

Amplifier 123 provides its output through a feedback loop to the input of power supply 103. The node provides the output voltage VOUT when the PNP transistor 121 is energized between the collector of the PNP transistor 121 and the emitter of the PNP transistor 122. In this arrangement, the compensation circuit 104 can sense the ISENSE current at the output of the power supply 103. If a current limit condition exists, the amplifier 123 supplies a current proportional to the excess current (ie, the amount of current exceeding the normal maximum current). This current limits the drive of the power supply 103 to prevent local overheating on the IC.

If the output voltage VOUT is too high relative to the input voltage power supply VIN (for example, VIN-VOUT < 150 mV), the PNP transistor 121 starts to saturate and the PNP transistor 122 is turned on. When the PNP transistor 121 begins to saturate, excess carriers are injected into the substrate. Such excess carriers on the substrate cause undesirable substantial instability in many components of the regulator 100.

In one embodiment, the current limiting circuit 104 may detect and respond to both conditions. In particular, in either case (or when both conditions are potentially present), the amplifier 123 has its current limit and / or its input to generate an amount of current suitable for the PNP transistor 121 to begin to saturate. Can be used. Amplifier 123 has two inputs: one is a voltage high sensitivity differential input for ISENSE (and therefore amplifier 123 can function as a gm amplifier) and one is a current high sensitivity single-ended input for PNP transistor 122. (Hence, amplifier 123 may also function as a current amplifier).

Unfortunately, both the voltage control loop and the current limit control loop in regulator 100 'are sources of regulator destabilization. In particular, each control loop provides negative feedback to the regulator 100 '. Unfortunately. The configuration in this control loop causes unwanted positive feedback, causing oscillation in the output voltage VOUT, making the regulator 100 'unstable. This vibration can prevent effective voltage compensation, remove current limiting conditions, or cause substantial damage to other ICs driven by regulator 100 '.

Therefore, there is an increasing need for a method and system that provides a stabilized control loop of the regulator.

The purpose of the voltage regulator according to the present invention to solve the above problem is to provide a stable output voltage (VOUT). The control loop in the voltage regulator can cause unwanted vibrations in the output voltage VOUT. According to one aspect of the invention, the use of poles and zeros can advantageously be used to stabilize the voltage regulator in a silicon-effective manner.

According to one aspect of the invention, the control loop of the voltage regulator can be stabilized using the minimum silicon region. In particular, the current limiting signal generated by the current limiting control loop of the voltage regulator can be distributed to minimize the zero provided to the compensation set associated with the voltage control loop to stabilize both loops. The compensation set may include a resistor (zero) and a capacitor (pole) connected in series between the input and output terminals of the amplifier. The distribution of the current limiting signal may include applying a first portion of the current limiting signal to the first side of the resistor and applying a second portion of the current limiting signal to the second side of the resistor. The ratio of the first and second portions can be based on the gain of the amplifier, thereby minimizing the effect of resistance. This amplifier can be the second stage of the multistage error amplifier.

For example, the error amplifier may include a first amplifier and a second amplifier. In one embodiment, the first amplifier may comprise an automatic amplifier and the second amplifier may comprise a current amplifier. The first amplifier may have a first input terminal for receiving a reference voltage and a second input terminal for receiving a signal in a voltage control loop. The second amplifier may receive the output of the first amplifier. The compensation set may include a resistor and a capacitor connected in series between the output of the second amplifier and the input of the second amplifier.

Remarkably, the error amplifier may further include a ratiometric branch compensation circuit that receives the current limit signal and applies current to both sides of the resistor in the compensation set. The ratio of the applied current is substantially equal to the gain of the second amplifier. In one embodiment, the rationometric branch compensation circuit may include first and second transistors. Each transistor has a terminal (eg, ground) connected to a voltage power supply and a control terminal for receiving a current limit signal. However, each transistor has another terminal connected to the other side of the resistor. In one embodiment, the first and second transistors may be implemented as NMOS transistors having a ground voltage power supply. This error amplifier can be included in other reference voltage regulators.

As described in more detail below, the ratiometric branch compensation circuit has the advantage of stabilizing both the voltage control loop and the current limit control loop while minimizing the silicon area. In particular, by minimizing (or eliminating) the effect of resistance in the compensation set, the loop can assign a single compensation capacitor.

Overview: poles and zeros

In general, for a stable loop, the feedback signal can be of opposite polarity to the source signal (eg, in a voltage regulator, the reference voltage becomes the source signal). For this reason, the feedback signal is typically characterized by negative feedback. This negative feedback enhances stable output against any changes introduced by the source signal. Conversely, positive feedback has the same polarity as the source signal, so that any fluctuations in the source signal are sharp and the control loop is unstable.

The feedback signal may experience fluctuations in the gain and phase that pass through the control loop. The phase shift, referred to as the change in all phases, occurs within the control loop. The ideal negative feedback is 180 ° out of phase with the source signal, ie it starts at -180 °. Logically, if negative feedback experiences a 180 ° phase shift, that negative feedback becomes positive feedback.

The phase shift of any control loop can be calculated using a Bode plot that shows the gain (dB) of the loop as a function of frequency (Hz). The amount of phase shift that occurs at unity gain (0 dB) determines the stability of the control loop. A "pole" can be defined as the point on the gain curve when the slope changes by -20dB. 1C shows a board plot 130 that includes a pole and a corresponding calculated phase shift plot 132. As shown in the phase shift plot 132, the pole changes the phase shift almost -90 ° within 1x10 or more and 1x10 or less of the pole frequency (the actual equation is that phase shift = -arctan (f / fp). ), The frequency f is generated by the pole frequency placed at frequency fp). Conversely, "zero" can be defined as the point on the gain curve when the curve changes by +20 dB. 1D shows a board plot 140 with poles 141 and corresponding calculated phase shift plots 412. As shown in the phase shift plot 142, the zero point changes the phase shift almost + 90 ° within 1x10 or more and 1x10 or less of the pole frequency (the actual equation is phase shift = arctan (f / fp) ).

In a typical control loop, there may be both poles and zeros, where each pole reduces the slope in the board plot by -20dB / decade and each zero increases the slope by + 20dB / decade. FIG. 1E shows a board plot 150 with two poles and two zeros, that is, poles 151 and 153 and zeros 152 and 154 and corresponding phase shift plots 155. In this embodiment, the DC gain is 40 dB at the pole 151 at 1 kHz, the zero point 152 at 10 kHz, the pole 153 at 100 kHz, and the zero point 154 at 1 MHz. As zero points 152 and 154 change the slope to 0 dB / decade, poles 151 and 153 produce a slope of -20 dB / decade.

To determine if the control loop is stable, a phase shift at 0 dB (also in this case can be called unity-gain crossover frequency occurring at 1 MHz) can be determined. In the phase shift plot 155, the poles 151 and 153 as well as the zero point 152 contribute to the -90 °, 90 ° and -90 ° phase shifts, respectively. In particular, the final pole contributes nearly 60-80 ° (compared to -90 ° from the previous three poles). Therefore, the final phase shift is from -10 ° to -30 °. With this phase shift, the loop can be stabilized.

Control loop stability

Remarkably, each configuration of the voltage control loop and the current limiting loop can contribute to the pole or zero. In addition, parasitic poles may exist in the circuit (parasitic zero may also exist. A parasitic zero may act as a Right Half Plane Zero (hereinafter referred to as RHPZ) with the same amplitude effect as zero, but with a phase). Seems like a pole, causing a shift, even though the gain stage typically has pole pairs and RHPZ, the degradation effect on the phase margin of the control loop from gain and parasitic zero is usually minimized due to its high frequency, so transfer function analysis is both controlled. It is important to reinforce the stability of the loop, that is, provide negative feedback, and the introduction and location of additional configurations that provide such stability are described.

2 shows a simplified voltage regulator 200 that can provide a stable control loop with a minimum silicon region. In this embodiment, the error amplifier 210 may include a differential amplifier 201 that receives signals from the reference voltage 101 and the voltage control loop. The output of differential layer amplifier 201 is applied to a current amplifier which in turn provides its output to drive device 103.

Very large compensation capacitors (not shown) can be used to control the gain and phase characteristics of the control loop. This large compensation capacitor can also be a pole, but with this configuration the phase shift can lead to cumulative negative feedback in addition to other poles and parasitic poles in the ballast. However, using large compensation capacitors substantially slows down the ballast and occupies significant silicon area, both of which are economically unacceptable.

On the other hand, smaller compensation capacitors can be used, for example, one for each control loop. However, any compensation capacitor occupies a significant silicon area, which is a relatively expensive configuration that is integrated into the system. Therefore, it is desirable for the voltage control loop and the current limiting control loop to share one compensation capacitor.

The most disturbing sharing of compensation elements in the ballast is the presence of a standard compensation loop for the voltage control loop. As shown in FIG. 2, this compensation loop includes a resistor 205 and a compensation capacitor 204 connected in series between the nodes 209 and 203. Capacitor 204 and resistor 205 may be adjusted to provide adequate performance during transient conditions while providing sufficient gain and phase shift to enhance the stability of the voltage control loop.

The goal of a high performance regulator is to drive the output driver solidly. Therefore, the error amplifier in the regulator is built with significant gains. However, because of this high gain need and some processing conditions, the amplifier of the current limiting circuit cannot provide the current limit correction necessary for the error amplifier in the arrangement shown in FIG. 1B, that is, the output correction of the error amplifier.

Therefore, it is desirable to provide current limit correction to the internal stage of the error amplifier that is substantially lower in gain than the output (current is lower), thereby enhancing the performance of the current limiting circuit 104. It simply provides the output of the current limiting circuit 104 to make the function of moving to the same zero point as a voltage control loop only at the node 211 in the error amplifier 210. That is, unwanted positive feedback.

On the other hand, simply providing a signal over line 124 only at node 212 creates large loop instability. In particular, when a current pulse is added to the circuit with poles and zeros, the initial stage (zero-based, eg resistance) is generated according to the inclined waveform (pole-based, eg capacitor). This step and the inclined waveform occur when a pulse is applied only to node 211. However, if a pulse is applied to node 212, the pulse is immediately sent to node 203 and amplifier 202 via capacitor 204, which is required for the inversion phase. In this case, the initial response begins a step in the opposite direction before the slope begins. The reversal of this short interval input is superior to that of the long interval input. Therefore, zero is always generated no matter which pulse is added to either node 212 or node 211. Ie, left half zero or right half zero. Remarkably, both types of zeros are bad for current limiting loops.

Therefore, in accordance with one aspect of the present invention, a rationometric branch compensation circuit 206 is used to distribute the signal from the current limiting circuit 104 and provides signals at both nodes 211 and 212 distributed. To provide this distribution, the rationometric branch compensation circuit 206 includes two buffers 207 and 208. Remarkably and in more detail with reference to FIG. 3, buffers 207 and 208 apply a definite current to each of nodes 212 and 211 based on the gain of current amplifier 202 and thereby resist (ie, R _zero ). The influence of can be eliminated. This cancellation helps all loop stabilization using a single compensation capacitor (ie, pole), thereby minimizing silicon area. This cancellation also has the advantage of controlling loop stabilization without considering loop instability in current limit conditions.

Error Amplifier: Example

3 illustrates one embodiment of an error amplifier 300 that includes a ratiometric branch compensation circuit. In this embodiment, the differential amplifier 201 may include PNP transistors 310, 302, 312, 313 as well as resistors 320, 321, 322. PNP transistor 301 has a collector and its base connected to a current source IBBN whose emitter is connected to a voltage power supply VCC. The PNP transistor 302 has an emitter connected to the voltage power supply VCC and its collector connected to the emitters of the PNP transistors 312 and 313. The bases of the PNP transistors 312 and 313 each have a negative input signal INn (ie, a signal of a voltage control loop) and a reference voltage REF. The collectors of PNP transistors 312 and 313 are connected to voltage source GND (ground) through resistors 320 and 321, respectively.

Differential amplifier 201 may include NPN transistors 314, 315, 318 as well as resistor 322, which actually provides a fully differential output to current amplifier 202. In particular, collectors of PNP transistors 312 and 313 are connected to NPN transistors 318 and 315, respectively, to provide differential signals. NPN transistor 314 has its emitter coupled to voltage wjsdnjsGND via resistor 322. The base of the NPN transistors 314, 315, 318 is usually connected to the collector of the NPN transistor 314. In this arrangement, the NPN transistor 314 connected to the diode may be biased in the NPN transistors 315 and 318. The values of resistors 320, 321 and 322 can be set, for example, to 10 kΩ such that currents applied from PNP transistors 312 and 313 pass the same through resistors 320 and 321 like resistor 322, thereby causing differential amplifier 201. And the current amplifier 202 can be balanced. In this way, changes in the input signal can be accurately reflected in the NPN transistors 315 and 318.

In this embodiment, the rational branch compensation circuit 206 may include NMOS transistors that implement buffers 206 and 207 (described with reference to FIG. 3 as NMOS transistors 206 and 207). NMOS transistors 206 and 207 have a source connected to a voltage power supply GND and a gate connected to receive a signal from a current limiting circuit CLimit. NMOS transistor 323 has a source coupled to voltage supply GND, a gate coupled to receive a signal from current limiting circuit CLimit, and a drain coupled to the gate. NMOS transistor 323 may be characterized as part of the formation of amplifier 330. In this diode connected arrangement, the NMOS transistors 323 can actually be set to biases provided to the NMOS transistors 206 and 207 and thereby determine the current they produce. More particularly, the size of the NMOS transistor 323 determines the gain of the current limiting loop.

Amplifier 330 receives the differential current applied by current amplifier 202 and generates a voltage to function as a transimpedance amplifier. In this embodiment, amplifier 330 includes PNP transistors 303, 304, 305, 308 and 309 as well as resistors 306 and 307. The collectors of the PNP transistors 304, 305 are connected to the other terminal of the resistor 306, the collector of the NPN transistor 315, and the base of the PNP transistor 308. The collector of the PNP transistor 305 is connected to the other terminal of the resistor 307, the collector of the NPN transistor 318 and the base of the PNP transistor 309. Emitters of the PNP transistors 308 and 309 are connected to a voltage power supply VCC. The collector of the PNP transistor 308 is connected to the gate and the drain of the NMOS transistor 326 as well as the gate of the NMOS transistor 327. The collector of the PNP transistor 309 is connected to the drain of the NMOS transistor 327. The sources of NMOS transistors 326 and 327 are connected to the voltage power supply GND.

Node 312 in this arrangement represents the output of amplifier 330. The magnitude of resistors 306 and 307 determine the current gain of amplifier 330. Amplifier 330 provides a regulated amount of current gain without additional DC bias.

The significantly determines the size ratio of the NMOS transistors (206,207) it is important to perform the erase the effect of the resistor (205, that is, R _zero). Resistor 205 is connected between the drains of NMOS transistors 206 and 207. Conversely, capacitor 204 is connected between the emitter of NPN transistor 318 and the drain of NMOS transistor 206. At short interval pulses the capacitor 204 is shortened. In addition, the effective resistance to the emitter of NPN transistor 318 is much lower than the resistance of resistor 205. In this case, applying a current pulse to nodes 212 and 211 will result in a triple the current pulse size at node 312. Applying a triple pulse to node 312 by itself to pulses 212 and 211, the net current at resistor 205 is zero. In other words, the effect of the amplified pulse is essentially eliminated. Therefore, the size of the resistor 205 is not important.

Based on the gain of the current amplifier 202, the size ratio of the NMOS transistors 206 and 207 may be selected so that an appropriate amount of current can be applied to the opposite side of the resistor 205. Thereby, the influence of Rzero is effectively canceled. For example, if the gain of the current amplifier 202 is 3, the NMOS transistor 205 has M = 1 and the NMOS transistor 207 has M = 3. Therefore, none of the applied current increases in the resistor 205, so the influence of Rzero is canceled. If the effect of Rzero is canceled, only the effect of capacitor 204 is manifested by the current limiting loop CLimit (ie, after sufficient time for capacitor 204 to begin charging).

In one embodiment, resistor 205 may be smaller, such as 100-300 kΩ or 10-40 kΩ. According to one aspect of the present invention, the effect of Rzero can be minimized to enhance negative feedback as long as the rationometric branch compensation circuit 206 is closed at a selected ratio to the gain provided by the current amplifier 202.

A PNP transistor 310 having an emitter connected to the voltage power supply VCC and a collector connected to the drain of the NMOS transistor 311 receives a current signal IBBN at its base. The NMOS transistor 311 connected to the voltage power supply GND is connected to the collector of the PNP transistor and the drain of the NMOS transistor 207. The collector of the PNP transistor 310 and the drain of the NMOS transistor provide the output voltage OUT of the error amplifier.

Additional configuration may be included to enhance the balanced output signal at node 312. For example, PNP transistors 304 and 308 and resistor 306 are symmetrical to PNP transistors 305 and 309 and resistor 307. In addition, NMOS transistors 326 and 327 may form a voltage balanced mirror in addition to node 312. Transistors 326 and 327 perform MOSFET technology as the same output device 311. Since no imbalance in the signal at node 312 is desirable (ie, by triggering a control loop to correct the input offset), the components of the error amplifier 300 can be characterized as symmetrically as possible.

The invention is not limited by the depicted description.

For example, although the regulator 300 includes a MOSFET and a polarization transistor, other types of embodiments may be included. MOSFET transistors can also be used for polarization transistors. For example, an NPN transistor can be used in place of the NOMS transistor of FIG.

In other embodiments, differential amplifiers and current amplifiers may be used instead of operational amplifiers. Therefore, in general, the error amplifier can be simply characterized to include the first and second amplifiers. Also, in other embodiments the rationometric branch compensation circuit can be characterized by a voltage applied to two nodes instead of current.

Accordingly, the scope of the invention is defined by the following claims and their equivalents.

According to the present invention as described above can provide a voltage regulator for applying a stable output voltage (VOUT), it can bring a stabilization to the control loop in the voltage regulator. Thus, according to the present invention, poles and zeros can be used to stabilize the voltage regulator in a silicon-effective manner.

Claims (18)

For error amplifiers: A first amplifier having a first input terminal for receiving a reference voltage and a second input terminal for receiving a signal from a voltage control loop; A second amplifier receiving the output of the first amplifier; A compensation set comprising a resistor and a capacitor connected in series between the output of the second amplifier and the input of the second amplifier and providing stability of the voltage control loop; And And a rational branch compensation circuit that receives a signal in a current limiting circuit and applies current to both sides of the resistor of the compensation set. The method of claim 1, Wherein said first amplifier comprises a differential amplifier and said second amplifier comprises a current amplifier. The method of claim 1, And wherein the ratio of the applied currents is equal to the gain of the second amplifier. The method of claim 1, The ratiometric branch compensation circuit is: A first transistor comprising a first terminal connected to the first side of the resistor, a second terminal connected to a voltage power supply, and a control terminal receiving the signal from the current limiting circuit; And And a second transistor comprising a first terminal connected to the second side of the resistor, a second terminal connected to the voltage power supply, and a control terminal receiving the signal from the current limiting circuit. The method of claim 4, wherein Wherein said first and second transistors comprise NMOS transistors and said voltage power supply is ground. In the control loop stabilization method of the voltage regulator, Receiving a current limit signal from a current limit control loop of the voltage regulator; And Stabilizing the voltage control loop and the current limit control loop by minimizing the effect of zero provided on a compensation set that distributes the current limit signal to provide stability of the voltage control loop. How to stabilize the control loop of a voltage regulator. The method of claim 6, The compensation set includes a resistor that generates the zero point, Distributing the current limiting signal may include: Applying a first portion of the current limiting signal to the first side of the resistor; And Applying a second portion of the current limiting signal to a second side of the resistor, The control loop stabilization method of the voltage regulator, characterized in that to minimize the effect of the resistance. The method of claim 6, The set of rewards includes a zero, Distributing the current limiting signal may include: Applying the distributed current limit signal to minimize the effect of the zero point. In the voltage regulator, An error amplifier including a rational branch compensation circuit; A drive coupled to receive the output of the error amplifier; A current limiting circuit coupled to receive the output of the drive and generating a current limiting signal for a current limiting control loop; A voltage control loop coupled to receive the output of the current limiting circuit and applying an input signal to the error amplifier; And A compensation set comprising a zero and a pole and providing stability of the voltage control loop, The rational branch compensation circuit minimizes the effect of the zero point in the compensation set by distributing the current limit signal, This stabilizes the voltage control loop and the current limiting control loop. The method of claim 9, And said rationometric branch compensation circuitry comprises two buffers receiving said current limiting signal and applying an output to the other side of the resistor generating said zero. In the error amplifier, A differential amplifier having a first input terminal for receiving a reference voltage and a second input terminal for receiving a signal from a voltage control loop; A current amplifier receiving the output of the differential amplifier; A compensation set comprising a resistor and a capacitor connected in series between the output of the current amplifier and the input of the current amplifier, the compensation set providing stability of the voltage control loop; And And a schematic branch compensation circuit that receives a signal from a current limiting circuit and applies current to both sides of the resistor in the compensation set. The method of claim 11, The ratiometric branch compensation circuit is: A first NMOS transistor having a source connected to a first voltage power source and a drain connected to a first junction positioned between the resistor of the resistor and the capacitor; And A second NMOS transistor having a source connected to a first voltage power supply and a drain connected to a second junction of the resistor, And the gates of the first and second NMOS transistors receive current limiting circuit outputs. The method of claim 12, And a third NMOS transistor having a source connected to said first voltage power supply, a drain and a gate receiving said current limiting circuit output. The method of claim 11, The differential amplifier is: A first PNP transistor having a base connected to the current power supply and a collector and an emitter connected to the second voltage power supply; A second PNP transistor having an emitter connected to a second voltage power supply and a base connected to the base of the first PNP transistor; A third PNP transistor having an emitter connected to the collector of the second PNP transistor and a base for receiving a reference voltage; A fourth PNP transistor having an emitter connected to said collector of said second PNP transistor and a base for receiving a voltage control loop signal; A second resistor coupled between the collector of the third PNP transistor and the first voltage power supply; And And a third resistor coupled between the collector of the fourth PNP transistor and the first voltage power supply. The method of claim 14, The current amplifier is: A first NPN transistor having a base, a collector, and an emitter; A second NPN transistor having an emitter, a base, and a collector connected to the collector of the fourth PNP transistor; An emitter connected to the collector of the third PNP transistor and a base connected to the collector of the first NPN transistor and a base connected to the base of the first and second NPN transistors, the first resistor of the first resistor A junction is a first junction of the capacitor, a second junction of the capacitor is connected to the emitter of the third NPN transistor, and the collector of the first and third NPN transistors is a third NPN transistor which can be connected to an amplifying circuit. ; And And a fourth resistor coupled between the first voltage power supply and the emitter of the first NPN transistor. The method of claim 15, The amplification circuit is: A fifth PNP transistor having an emitter connected to the second voltage power source, a base connected to the base of the second PNP transistor, and a collector connected to the collector of the first NPN transistor; A sixth PNP transistor having an emitter connected to a second voltage power supply and a collector connected to the collector of the second NPN transistor; A seventh PNP transistor having an emitter connected to the second voltage power supply, a collector connected to the collector of the third NPN transistor, and a base connected to the base of the sixth PNP transistor; An eighth PNP transistor having an emitter connected to the second voltage power supply, a base connected to the collector of the sixth NPN transistor, and a collector coupled to a first voltage power supply; A ninth PNP transistor having an emitter connected to a second voltage power supply, a base connected to the collector of the seventh NPN transistor, and a collector coupled to the first voltage power supply; A fifth resistor having a first junction connected to said gate of sixth and seventh PNP transistors and a second junction connected to said collector of said sixth PNP transistor; And And a sixth resistor having a first junction connected to said gate of said sixth and seventh PNP transistors and a second junction connected to said collector of said seventh PNP transistor. The method of claim 16, A fifth NMOS transistor having a source connected to a first voltage power supply, and a gate and a drain connected to a collector of the eighth PNP transistor; And And an sixth NMOS transistor having a source coupled to the first voltage power source, a gate coupled to the gate of the fifth MMOS transistor, and a drain coupled to the collector of the ninth PNP transistor. . The method of claim 17, A fourth NMOS transistor having a source connected to a first voltage power source, a gate connected to the second junction of the collector and the first resistor of the ninth PNP transistor, and a drain connected to the output terminal of the error amplifier; And And a tenth PNP transistor having an emitter connected to a second voltage power source, a base connected to the base of the fifth PNP transistor, and a collector connected to the output terminal of the error amplifier.

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