KR100874644B1 - Data transmission device and method - Google Patents

Abstract

The present invention relates to a data transmission apparatus and method capable of minimizing electromagnetic interference (EMI) generated during data transmission.

The data transmission apparatus includes a clock generator for generating at least two clocks having the same frequency and having different phases; A data extractor for sampling input data according to at least one of the clocks; The clock generator includes a main clock generator for generating a main clock, a first clock generator for generating a first clock according to the main clock, and a second clock delayed by one clock from the first clock by receiving the first clock. It has a second clock generator for generating a clock, said first and second clock generators comprising a D flip-flop.

With this configuration, by sampling and latching digital data using multi-clock, it is possible to latch data having a high frequency at a low clock frequency. Accordingly, the electromagnetic interference (EMI) problem and the distortion of the signal due to the faster clock frequency in the high speed data signal are prevented.

Description

Data transmission apparatus and method {APPARATuS AND METHOD FOR TRANSMITTING DATA}             

1 is a block diagram showing a conventional timing controller.

2 is a waveform diagram showing a clock for latching conventional data.

3 is a waveform diagram illustrating a clock for latching a data frequency faster than the frequency of the data shown in FIG.

4 is a block diagram showing data latched to a source driver.

Fig. 5 is a waveform diagram showing a clock frequency for latching data separated into conventional odd and even data.

6 is a block diagram illustrating a timing controller according to the present invention.

FIG. 7 is a circuit diagram illustrating a multiclock generator for generating the multiclock shown in FIG. 6.

FIG. 8 is a waveform diagram illustrating a multi clock generated from the multi clock generator illustrated in FIG. 7.

9 is a waveform diagram illustrating latching data using the multi-clock of the present invention.

10 is a waveform diagram illustrating a timing margin.                 

Fig. 11 is a block diagram showing that latched data is supplied to a source driver driver.

12 is a waveform diagram illustrating a clock frequency for latching data separated into odd and even data according to the present invention.

<Explanation of symbols for main parts of drawing>

10,14,20,24: Timing Controller

12,16,32,36: Source Driver

40: multi clock generator

42: main clock generator

The present invention relates to a data transmission apparatus and method, and more particularly, to a data transmission apparatus and method capable of minimizing electromagnetic interference (EMI) generated during data transmission.

Recently, the amount of video data transmitted through a transmission medium has been increased in order to meet the user's desire for high quality video and is being transmitted at a high speed so that the user can use it at an appropriate time. As a result, the transmission frequency of the video data is increased and the number of lines for transmitting information is inevitably increased. In this case, as the video data having a high frequency is transmitted synchronously through the increased data transmission lines, electromagnetic interference (hereinafter, referred to as “EMI”) becomes severe.

1 is a block diagram showing a timing controller for transmitting conventional data.

Referring to FIG. 1, a conventional data transmission device receives various clock signals DCLK, horizontal and vertical synchronization signals Hsync and Vsync, and digital data to generate various control signals by using an enable signal. And a source driver driver 12 for storing digital data by the control signal supplied from the timing controller 10 and transmitting the digital data to an image display unit (not shown).

The timing controller 10 controls the driving timing of the gate driving driver (not shown) and the source driving driver 12 in response to the clock signal DCLK inputted from the outside and the horizontal and vertical synchronization signals Hsync and Vsync. do. In other words, the timing controller 10 generates a gate start pulse GSP and a gate shift clock GSC signal in response to the clock signal DCLK and the horizontal and vertical synchronization signals Hsync and Vsync to operate the gate driving driver. And a gate output enable signal (GOE) to the gate driving driver. In addition, the timing controller 10 is a digital input to the enable section of the source start pulse (SSP) indicating that the video data section in response to the input clock signal (DCLK) and the horizontal and vertical synchronization signals (Hsync, Vsync) The data Data is transmitted to the source driver 12. In this case, the timing controller 10 supplies the source sampling clock SSC, the source output enable signal SOE signal, the polarity control signal MPOL, and the digital data R, G, and B to the source driving driver 12. Done.

The timing controller 10 samples the digital data in the rising edge section or the falling edge section of the source sampling clock SSC frequency and latches the digital data in the source driving driver 12.

The source driver 12 latches the digital data sampled according to the source sampling clock SSC supplied from the timing controller 10 into a shift register (not shown), and then digital-analog converts the image through a buffer. It serves to supply to a display unit (not shown).

Referring to FIG. 2, the digital data Data is sampled in the rising edge section of the source sampling clock SSC and latched in a shift register (not shown) of the source driving driver 12. Since the latch of the digital data is latched in the rising edge section of the frequency of the single source sampling clock SSC, the source sampling clock SSC should also be faster as the frequency of the digital data is faster. In other words, when the frequency of the digital data is doubled as shown in FIG. 3, the source sampling clock SSC must also be increased by twice the clock frequency of FIG. 2. Therefore, when the frequency of the digital data is increased, the frequency of the source sampling clock SSC must be increased by that much.

As described above, as the latching interval of the source sampling clock SSC becomes narrower, the timing margin for latching the correct digital data Data is reduced. When the timing margin is reduced in this way, the sampling time of the data is shifted and the wrong digital data is latched, which may cause distortion of the data signal.

4 illustrates a process of sampling odd data ODD data and even data EVEN DATA separated by the timing controller 14 and latching them in the source driving driver 16 according to the source sampling clock SSC.

4 and 5, the digital data is red (Re, Ro), green (Ge, Go) divided into odd data (ODD DATA) and even data (EVEN DATA) through the timing controller 14. ) And blue (Be, Bo) data. Accordingly, the frequency of the source sampling clock SSC for sampling the odd data ODD DATA and the even data EVEN DATA is halved and output.

The odd data ODD DATA and the even data EVEN DATA are sampled in the rising edge section of the source sampling clock SSC and latched in the shift register (not shown) of the source driving driver 16. Accordingly, the frequency of the source sampling clock SSC is halved by dividing the digital data Data into odd data and even data by sampling and latching the digital data.

However, the faster the data transmission frequency, the faster the frequency of the source sampling clock (SSC) must be. Accordingly, as the latching interval of the source sampling clock SSC is narrowed, the timing margin for latching the correct digital data Data is reduced. When the timing margin is reduced in this way, the sampling time of the data is shifted and the wrong digital data is latched, which may cause distortion of the data signal. In particular, in the case of a liquid crystal display device, as the resolution increases, that is, as the number of pixels increases, the amount of video data to be transmitted within a unit time increases, which inevitably increases the data transmission frequency. For example, when the liquid crystal display is in the XGA mode, the timing controller 14 drives both the input and output clock signals DCLK and CLOCK at 65 MHz and synchronously samples the digital data at the same frequency. Done.

As such, as the transmission frequency of video data increases, EMI on the data bus becomes more severe.

Accordingly, it is an object of the present invention to provide a data transmission apparatus and method capable of minimizing electromagnetic interference (EMI) generated during data transmission.

In order to achieve the above object, a data transmission apparatus according to the present invention comprises a clock generator for generating at least two or more clocks having the same frequency and different phases; A data extractor for sampling input data according to at least one of the clocks; The clock generator includes a main clock generator for generating a main clock, a first clock generator for generating a first clock according to the main clock, and a second clock delayed by one clock than the first clock by receiving the first clock. And a second clock generator for generating a clock, wherein the first and second clock generators are configured as D flip-flops.

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The number of clocks generated from the clock generator may vary according to the frequency of the input data.

The data extractor samples the input data in any one of a rising edge section and a falling edge section of the clock.

A data transmission method according to the present invention comprises the steps of: generating at least two or more clocks having the same frequency and having different phases; Sampling input data according to at least one of the clocks; The generating of the clocks may include generating a main clock, generating a first clock using a D flip-flop according to the main clock, and receiving the first clock and using the D flip-flop. Generating a second clock delayed by one clock than one clock.

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The number of clocks generated in the clock generation step may vary according to the frequency of the input data.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 12.

Referring to FIG. 6, the data transmission apparatus according to the present invention receives a clock signal DCLK, horizontal and vertical synchronization signals Hsync, Vsync, and digital data to provide various control signals by enabling the signal. And a source driver driver 32 for storing the digital data by the control signal supplied from the timing controller 20 and transmitting the digital data to an image display unit (not shown).

The timing controller 20 controls the driving timing of the gate driving driver (not shown) and the source driving driver in response to the clock signal DCLK inputted from the outside and the horizontal and vertical synchronization signals Hsync and Vsync. In other words, the timing controller 20 responds to the clock signal DCLK and the horizontal and vertical synchronizing signals Hsync and Vsync input to operate the gate driver, and the gate start pulse GSP and the gate shift clock GSC. Signal and a gate output enable (GOE) signal to the gate driving drivers.

In addition, the timing controller 20 receives digital data input to an enable section of the source start pulse SSP indicating the video data section in response to the clock signal DCLK and the horizontal and vertical synchronization signals Hsync and Vsync. (Data) is transmitted to the source driver 32. In this case, the timing controller 20 supplies the first to nth source sampling clocks SSC1 to SSCn, the source output enable signal SOE signal, the polarity control signal MPOL, and the digital data Data. Will be sent).                     

The first to nth source sampling clocks SSC1 to SSCn serve to latch digital data at every rising edge section of the clock. To this end, the first to nth source sampling clocks SSC1 to SSCn are delayed by one clock by the multi-clock generator 40 as shown in FIG. 7 and are supplied to the source driving driver 32.

Referring to FIG. 7, the multi-clock generator 40 may include the main clock generator 42 generating the main clock MCLK and the first to nth source sampling clocks SSC1 to SSCn according to the main clock MCLK. N D flip-flops DFF1 to DFFn for generation.

The main clock generator 42 generates a main clock MCLK to supply the n D flip-flops DFF1 to DFFn, respectively.

The main clock MCLK is supplied from the main clock generator 42 to the inverting input terminals of the n D flip-flops DFF1 to DFFn.

The first D flip-flop DFF1 among the n D flip-flops DFF1 to DFFn is provided with an inverter IVE between the output terminal Q and the data input terminal D1. The inverter IVE is provided to output the initial state of the first source sampling clock SSC1 to the rising edge state.

Each of the second to nth D flip-flops DFF2 to DFFn is supplied with the output signals of the main clock MCLK and the D flip-flops DFF1 to DFFn-1. That is, the first source sampling clock SSC1, which is the output signal of the first D flip-flop DFF1, is supplied to the input terminal of the second D flip-flop DFF2, and the output signal of the second source sampling clock SSC2 is The input terminal of the third D flip-flop DFF3 is supplied.                     

When the multi-clock generator 40 first assumes that the output terminal Q of the first D flip-flop DFF1 is in the low state, the output signal SSC in the low state is inverted through the inverter IVE to generate data. The input terminal D1 goes high. At this time, the first source sampling clock SSC1 in the high state is output through the output terminal Q in the high input signal in the first rising edge section of the main clock MCLK. The first source sampling clock SSC1 in the high state is inverted through the inverter IVE to become a low state in the data input terminal D1 so that the input signal in the low state is applied in the second rising edge section of the main clock MCLK. The first source sampling clock SSC1 in a low state is output through the output terminal Q.

The first source sampling clock SSC1 generated by the first D flip-flop DFF1 is supplied to the data input terminal D2 of the second D flip-flop DFF2. At this time, since the first source sampling clock SSC1 in the high state is delayed and input to the input terminal D2 of the second D flip-flop DFF2, when the main clock MCLK is in the first rising edge section, it is in a low state. The main clock MCLK outputs the second source sampling clock SSC2 in a low state until the second rising edge section.

Thereafter, the second source sampling clock SSC2 has the main clock MCLK changed to a high state in the second rising edge section. Accordingly, the second source sampling clock SSC2 is output by one clock delay from the first source sampling clock SSC1.

As a result, the multi-clock generator 40 generates the first to nth source sampling clocks SSC1 and SSCn which are sequentially delayed by one clock as shown in FIG. 8 using the D flip-flops DFF1 to DFFn-1. Done.                     

As such, the timing controller 20 including the multi-clock generator 40 may use the digital data (either the rising edge latching method or the falling edge latching method of the first to nth source sampling clocks SSC1 to SSCn). Data) is sampled and supplied to the source driver 32.

The source driving driver 32 latches the digital data Data sampled by the first to nth source sampling clocks SSC1 to SSCn supplied from the timing controller 20 to a shift register (not shown). It converts the analog and supplies it to the image display unit through the buffer.

9 is a waveform diagram illustrating latching digital data by simultaneously driving two multi-clocks according to the present invention.

Referring to FIG. 9, the digital data Data is sampled at the rising edge sections of the first and second source sampling clocks SSC1 and SSC2 and latched in a shift register (not shown) of the source driving driver 32.

In detail, the odd-numbered data D1, D3, D5, ..., Dn-1 of the digital data Data are sampled and latched in the rising edge section of the first source sampling clock SSC1. Further, even-numbered data D2, D4, ..., Dn of the digital data Data are sampled and latched in the rising edge section of the second source sampling clock SSC2. At this time, the frequencies of the first and second source sampling clocks SSC1 and SSC2 have a frequency that is about twice as slow as the frequency of the digital data Data.

As such, the digital data Data is sampled and latched in the rising edge sections of the first and second source sampling clocks SSC1 and SSC2. In this case, two source sampling clocks SSCs are simultaneously driven to increase timing margins, so that even if the frequency of the digital data becomes faster, the source sampling clocks SSC may be sampled and latched.

The timing margin indicates a time margin for the clock signal CLK to accurately sample the data, as shown in FIG. 10. The timing margin is a period in which the clock signal CLK is in a high state and a low state in a low state. The wider it is, the more stable time it can sample and latch. Accordingly, the timing margin is improved by simultaneously driving the first and second source sampling clocks SSC1 and SSC2, which are frequencies lower than the frequency of data, as in the present invention.

Referring to FIGS. 11 and 12, the digital data is red (Re, Ro), green (Ge, Go) divided into odd data (ODD DATA) and even data (EVEN DATA) through the timing controller 24. ) And blue (Be, Bo) data. The odd data ODD DATA and the even data EVEN DATA are sampled by the first and second source sampling clocks SSC1 and SSC2 and latched in the source driving driver 36.

Odd-numbered odd data D1, D5, D9, ..., and even data D2, D6, D10, ... are sampled in the rising edge section of the first source sampling clock SSC1 to be transmitted to the source driving driver 36. Latched. The even-numbered odd-numbered data D3, D7, D11, ..., and even-numbered data D4, D8, D12, ... are sampled in the rising edge section of the second source sampling clock SSC2, and the source driving driver 36 is sampled. Latched. At this time, since the frequencies of the first and second source sampling clocks SSC1 and SSC2 simultaneously drive the first and second source sampling clocks SSC1 and SSC2, odd data ODD data and even data EVEN DATA It has a frequency halved than the frequency of.

Accordingly, even if the frequency of the digital data becomes faster, the source sampling clocks SSC1 and SSC2 having a lower frequency than the frequency of the digital data are increased by driving two source sampling clocks SSC1 and SSC2 simultaneously to increase the timing margin. Digital data can be sampled and latched.

As shown in FIG. 10, the timing margin indicates a time margin for accurately sampling data by the clock signal CLK. The timing margin is high as the interval between the high state and the low state of the clock signal CLK increases. A stable time to sample and latch can be obtained. Accordingly, the timing margin is improved by simultaneously driving the multi-clock which is a frequency lower than the frequency of the data as in the present invention.

On the other hand, the timing controller 24 determines the number of outputs among the first to nth source sampling clocks SSC1 to SSCn according to the frequency of the digital data Data. Accordingly, the first to n th source sampling clocks SSC1 to SSCn output are sequentially delayed and output from the multi-clock generator 40. Therefore, even if the digital data becomes faster, the digital data may be sampled and latched at a lower frequency.

Accordingly, the high frequency digital data may be sampled and latched by a low frequency source sampling clock to solve the electromagnetic interference (EMI) problem due to the high clock frequency.

As described above, the data transmission apparatus and method according to the present invention can latch the data having a high frequency at a low clock frequency by sampling and latching the digital data using a multi clock. Accordingly, the electromagnetic interference (EMI) problem and the distortion of the signal due to the faster clock frequency in the high speed data signal are prevented.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

A clock generator for generating at least two clocks having the same frequency and having different phases; A data extractor for sampling input data according to at least one of the clocks; The clock generator includes a main clock generator for generating a main clock, a first clock generator for generating a first clock according to the main clock, and a second clock delayed by one clock than the first clock by receiving the first clock. And a second clock generator for generating a clock, wherein said first and second clock generators comprise a D flip-flop. delete delete The method of claim 1, The number of clocks generated from the clock generator may vary depending on the frequency of the input data. The method of claim 1, And the data extractor samples the input data in any one of a rising edge section and a falling edge section of the clock. Generating at least two clocks having the same frequency and having different phases; Sampling input data according to at least one of the clocks; The generating of the clocks may include generating a main clock, generating a first clock using a D flip-flop according to the main clock, and receiving the first clock and using the D flip-flop. Generating a second clock delayed by one clock than one clock. delete The method of claim 6, The number of clocks generated in the clock generation step may vary depending on the frequency of the input data. The method of claim 6, And the input data is sampled in any one of a rising edge section and a falling edge section of the clock.

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