KR100861273B1 - Line on Glass Liquid Crystal Display - Google Patents

Abstract

The present invention relates to a line on glass type liquid crystal display device capable of preventing a luminance difference between horizontal line blocks.

The line-on-glass type liquid crystal display device according to the present invention comprises a display unit in which signal signal lines for data display are formed and pixel cells are arranged in a matrix form, and connected to the signal signal lines for display. 1 A plurality of integrated circuits for supplying a drive signal, a supply line formed on a non-display area on the outer side of the display unit and supplying a second drive signal for display signal wirings, and a display signal wiring And a switching element for switching the current path between the display signal wires and the supply line.

Description

Line on glass type liquid crystal display device {LIQUID CRYSTAL DISPALY APPARATUS OF LINE ON GLASS TYPE}             

1 is a plan view schematically showing the configuration of a conventional line on glass type liquid crystal display device.

FIG. 2 is a detailed view of the gate drive IC shown in FIG. 1; FIG.

3 is a view showing in detail the level shifter shown in FIG.

FIG. 4 is a view for explaining separation between horizontal line blocks due to line resistance of the line-on-glass signal line group shown in FIG. 1; FIG.

5 is a plan view schematically illustrating a configuration of a line on glass type liquid crystal display device according to a first exemplary embodiment of the present invention.

FIG. 6 is a detailed view of a gate drive IC and a gate low voltage line shown in FIG. 5; FIG.

FIG. 7 is a view schematically illustrating a configuration of a line on glass type liquid crystal display device according to a second exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>                 

1, 51: liquid crystal panel 2, 52: lower substrate

4, 54: upper substrate 8, 58: data TCP

10, 60: data drive IC 12, 62: data PCB

14, 14A to 14D, 64: gate TCP

16, 66: Gate Drive IC

18, 68: data line 20, 70: gate line

21, 71: image display unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a line on glass type liquid crystal display device capable of preventing a luminance difference between horizontal line blocks.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area where the gate lines and the data lines cross each other. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to one of the data lines via source and drain terminals of a thin film transistor, which is a switching element. The gate terminal of the thin film transistor is connected to any one of the gate lines through which the pixel voltage signal is applied to the pixel electrodes of one line.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for controlling the gate driver and the data driver, and a power supply for supplying various driving voltages used in the liquid crystal display device. It has a supply part. The timing controller controls the driving timing of the gate driver and the data driver and supplies the pixel data signal to the data driver. The power supply unit generates driving voltages such as a common voltage VCOM, a gate high voltage VGH, and a gate low voltage VGL required for driving the liquid crystal display using the input power. The gate driver sequentially supplies the scanning signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever a scanning signal is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Among them, a data driver and a gate driver directly connected to the liquid crystal panel are integrated into a plurality of integrated circuits (ICs). Each of the integrated data drive IC and the gate drive IC is mounted on a tape carrier package (TCP) and connected to a liquid crystal panel by a tape automated bonding (TAB) method or mounted on a liquid crystal panel by a chip on glass (COG) method.

Here, the drive ICs connected to the liquid crystal panel in a TAB manner through TCP are interconnected with the control signals and DC voltages input from the outside through signal lines mounted on a printed circuit board (PCB) connected to the TCP. . In detail, the data drive ICs are connected in series through signal lines mounted on the data PCB, and are commonly supplied with control signals from the timing controller, pixel data signals, and driving voltages from the power supply unit. The gate drive ICs are connected in series through signal lines mounted on the gate PCB, and are commonly supplied with control signals from the timing controller and driving voltages from the power supply.

The drive ICs mounted on the liquid crystal panel in the COG method are interconnected in a line on glass (hereinafter referred to as "LOG") method in which signal lines are mounted on the liquid crystal panel, that is, the lower glass, and the timing controller and the power supply unit. Control signals and driving voltages are supplied.

Recently, even when the drive ICs are connected to the liquid crystal panel by the TAB method, the liquid crystal display device can be further thinned by adopting the LOG method and removing the PCB. In particular, the gate PCB is removed by forming a relatively small number of signal lines connected to the gate drive ICs on the liquid crystal panel using the LOG method. In other words, the TAB type gate drive ICs are connected in series through signal lines mounted on the lower glass of the liquid crystal panel, and are commonly supplied with control signals and driving voltage signals (hereinafter referred to as gate driving signals). do.

In practice, the liquid crystal display device in which the gate PCB is removed by using the LOG type signal lines has a plurality of data TCPs connected between the liquid crystal panel 1 and the liquid crystal panel 1 and the data PCB 12 as shown in FIG. 8, a plurality of gate TCPs 14 connected to the other side of the liquid crystal panel 1, data drive ICs 10 mounted on each of the data TCPs 8, and gate TCPs ( 14) and gate drive ICs 16 mounted on each.

The liquid crystal panel 1 is injected between the lower substrate 2 on which the thin film transistor array is formed, the upper substrate 4 on which the color filter array is formed, and the lower substrate 2 and the upper substrate 4 together with various signal lines. Configured liquid crystal. The liquid crystal panel 1 is provided with an image display area 21 composed of liquid crystal cells provided at each intersection of the gate lines 20 and the data lines 18 to display an image. Data pads extended from the data line 18 and gate pads extended from the gate line 20 are positioned in the outer region of the lower substrate 2 positioned at the outer portion of the image display area 21. In addition, in the outer region of the lower substrate 2, a LOG type signal line group 26 for transmitting gate driving signals supplied to the gate drive IC 16 is positioned.

A data drive IC 10 is mounted on the data TCP 8, and input pads 24 and output pads 25 electrically connected to the data drive IC 10 are formed. The input pads 24 of the data TCP 8 are electrically connected to the output pads of the data PCB 12 via an anisotopic conductive film (hereinafter referred to as "ACF"), and the data TCP 8 Output pads 25 are electrically connected to the data pads on the lower substrate 2 via the ACF. In particular, the first data TCP 8 is further formed with a gate drive signal transmission group 22 electrically connected to the LOG signal line group 26 on the lower substrate 2. The gate driving signal transmission group 22 supplies the gate driving signals supplied from the timing controller and the power supply unit to the LOG type signal line group 26 via the data PCB 12.

The data drive ICs 10 convert the pixel data signal, which is a digital signal, into a pixel voltage signal, which is an analog signal, and supply the same to the data lines 18 on the liquid crystal panel.

A gate drive IC 16 is mounted on the gate TCP 14, and a gate drive signal transmission line group 28 and output pads 30 electrically connected to the gate drive IC 16 are formed. The gate drive signal transmission line group 28 is electrically connected to the LOG signal line group 26 on the lower substrate 2 via the ACF, and the output pads 30 are connected to the lower substrate 2 via the ACF. It is electrically connected to the gate pads.

The gate drive ICs 16 sequentially supply the scanning signal, that is, the gate high voltage signal VGH, to the gate lines 20 in response to the input control signals. In addition, the gate drive ICs 16 supply the gate low voltage signal VGL to the gate lines in a period other than the period in which the gate high voltage signal VGH is supplied. In detail, the gate drive ICs 16 sequentially scan pulses in response to a gate start pulse GSP and a gate shift clock GSC supplied from a timing controller (not shown) as shown in FIG. 2. A shift register 40 for generating SP and a level shifter 42 for shifting the voltage of the scan pulse SP to a level suitable for driving the thin film transistor.

The shift register 40 is supplied with the gate start pulse GSP from the timing controller and performs a shift operation in response to the gate shift clock GSC to transfer the scan pulse SP to the level shifter 42 and the next stage shift register 40. ) Will be supplied sequentially.

As shown in FIG. 3, when the high logic scan pulse SP is supplied from the shift register 40, the level shifter 42 turns on the first transistor GT1 so that the gate high voltage VGH becomes the gate line. GL). When the low logic scan pulse SP is supplied from the shift register 40, the second transistor GT2 is turned on to supply the gate low voltage VGL to the gate line GL.

The LOG signal line group 26 typically includes a power supply unit such as a gate high voltage signal VGH, a gate low voltage signal VGL, a common voltage signal VCOM, a ground voltage signal GND, and a power supply voltage signal VCC. It consists of DC voltage signals supplied from the gate lines, gate start pulses GSP, gate shift clock signals GSC, and gate enable signals GOE, respectively. do.

The LOG signal line group 26 of the conventional liquid crystal display device is formed side by side in a fine pattern in a very narrow space, such as a pad portion located in the outer region of the image display portion 21. The LOG signal line group 26 is formed of a gate metal layer similarly to the gate lines 20. As the gate metal, a metal having a relatively large resistivity value (0.046), such as AlNd, is usually used. As the LOG signal line group 26 is formed as a fine pattern within a limited region and is composed of a gate metal having a relatively large resistivity value, a line having a relatively high line compared with signal lines formed of copper foil on a conventional gate PCB is formed. It includes the resistance component (X). In addition, an ACF (not shown) for connecting the LOG signal line group 26 and the gate driving signal transmission line group 28 on the lower substrate 2 includes a predetermined connection resistance component Y. In addition, the gate driving signal transmission line group 28 formed on the gate TCP 14 or the chip on film (COF) includes a predetermined line resistance component (Z). These resistive components differ by X + 2Y + 2Z between adjacent ICs. Here, since the gate driving signal transmission line group 28 on TCP or COF is formed of copper foil, the line resistance Z value can be ignored, so that the resistance difference Rt between the adjacent ICs is X + 2Y.

In addition, as the resistance components are proportional to the line length, the resistance value increases with distance from the data PCB 12 so that the gate driving signal is attenuated. As a result, the gate drive signals are distorted by the resistance thereof, thereby degrading the quality of the image displayed on the image display section 21.

In particular, the distortion of the gate low voltage VGL among the gate driving signals greatly affects the image quality of the image display unit 21. This causes the gate low voltage VGL to maintain the pixel voltage charged in the liquid crystal cell in the gate high voltage VGH period until the next pixel voltage is charged. If the gate low voltage VGL is distorted, the charged pixel voltage This is because it is variable.

In detail, the LOG type gate low voltage transmission line VGLL for supplying the gate low voltage VGL may include the first data TCP 8 and the first to fourth gate TCPs 14A to 14D, as shown in FIG. 4. The first to fourth LOG type gate low voltage transmission lines VGLL1 to VGLL4 are connected to each other. The first to fourth LOG type gate low voltage transmission lines VGLL1 to VGLL4 have line resistance values a, b, c, and d that are proportional to their line lengths, and have first to fourth gate TCPs 14A to 14D. Connected in series via).

The gate low voltage VGL supplied to each gate drive IC 16 varies according to the line resistances a, b, c, and d of the LOG gate low voltage transfer lines VGLL1 to VGLL4.

Specifically, the gate drive IC 16 mounted on the first gate TCP 14A has a first gate low voltage which is dropped in proportion to the first line resistance value a of the first LOG gate low voltage transmission line VGLL1. VGL1 is supplied. The first gate low voltage VGL1 is supplied to the gate lines of the first horizontal line block A through the first gate drive IC 16.

A second line resistance value of the first LOG gate low voltage transfer line VGLL1 and the second LOG gate low voltage transfer line VGLL2 connected in series to the gate drive IC 16 mounted on the second gate TCP 14B ( The second gate low voltage VGL2 which is dropped in proportion to a + b) is supplied. The second gate low voltage VGL2 is supplied to the gate lines of the second horizontal line block B through the second gate drive IC 16.

The third line resistance value a of the first LOG gate low voltage transmission line to the third LOG gate low voltage transmission line VGLL1 to VGLL3 connected in series to the gate drive IC 16 mounted on the third gate TCP 14C. The third gate low voltage VGL3, which is dropped in proportion to + b + c, is supplied. The third gate low voltage VGL3 is supplied to the gate lines of the third horizontal line block C through the third gate drive IC 16.

The fourth line resistance value a of the first LOG gate low voltage transmission line to the fourth LOG gate low voltage transmission line VGLL1 to VGLL4 connected in series to the gate drive IC 16 mounted on the fourth gate TCP 14D. The fourth gate low voltage VGL4 which is dropped in proportion to + b + c + d is supplied. The fourth gate low voltage VGL4 is supplied to the gate lines of the fourth horizontal line block D through the fourth gate drive IC 16.

As such, a difference occurs in the gate low voltages VGL1 to VGL4 supplied to the gate lines for each gate drive IC 16. That is, the line resistance values a, b, c, and d of the LOG type gate low voltage transmission line VGLL are added as they progress from the first gate drive IC 16 to the fourth gate drive IC 16. The first to fourth gate low voltages VGL1 to VGL4 supplied to the line blocks A to D have the same relationship as VGL1> VGL2> VGL3> VGL4. As a result, a luminance difference occurs between the horizontal line blocks A to D connected to the different gate drive ICs 16. The luminance difference between the horizontal line blocks A to D is caused by the horizontal line 32 phenomenon, and the screen is divided so that the image quality is reduced.

Accordingly, it is an object of the present invention to provide a LOG type liquid crystal display device capable of preventing the luminance difference between horizontal line blocks.

In order to achieve the above object, the LOG liquid crystal display according to the first exemplary embodiment of the present invention has a display unit in which signal signal lines for data display are formed and pixel cells are arranged in a matrix form, and display signal lines. A plurality of integrated circuits connected to supply first driving signals necessary for display signal wirings, and a second driving signal formed on a non-display area located at an outer side of the display unit and required for display signal wirings. And a switching element formed between the supply line for supplying and the display signal lines and the supply line to switch a current path between the display signal lines and the supply line.

The integrated circuit may be a gate drive integrated circuit, display signal lines may be a gate line, a first driving signal may be a gate high voltage signal, and a second driving signal may be a gate low voltage signal.

The gate drive integrated circuit may include a second switching device connected between the gate line and the gate high voltage line, and a resistor connected between the gate line and the base voltage.

A scan pulse is supplied to the gate terminal of the switching device, a gate high voltage is supplied to the drain terminal, and a gate line is connected to the source terminal.

In order to achieve the above object, the LOG-type liquid crystal table market according to the second embodiment of the present invention has a display unit in which display signal wirings for data display are formed and pixel cells are arranged in a matrix form, and display signal wirings. A plurality of integrated circuits connected to supply first driving signals necessary for display signal wirings, and a second driving signal formed on a non-display area located at an outer side of the display unit and required for display signal wirings. And a resistance formed between the supply line for supplying and the display signal lines and the supply line.

The integrated circuit may be a gate drive integrated circuit, display signal lines may be a gate line, a first driving signal may be a gate high voltage signal, and a second driving signal may be a gate low voltage signal.

The gate drive integrated circuit may include a switching device connected between the gate line and the gate high voltage line.

A scan pulse is supplied to the gate terminal of the switching device, a gate high voltage is supplied to the drain terminal, and a gate line is connected to the source terminal.

The supply line may be formed on a non-display area opposite to an area in which the gate drive integrated circuit is mounted on the display unit.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 5 to 7.                     

FIG. 5 is a diagram schematically illustrating a configuration of a LOG type liquid crystal display device according to a first embodiment of the present invention. The liquid crystal display shown in FIG. 5 is connected to a liquid crystal panel 51, a plurality of data TCPs 58 connected between the liquid crystal panel 51 and the data PCB 62, and one side of the liquid crystal panel 51. A plurality of gate TCPs 64, data drive ICs 60 mounted on each of the data TCPs 58, and gate drive ICs 66 mounted on each of the gate TCPs 64, respectively. do. In addition, a gate low voltage line 90 for applying the gate low voltage VGL is further provided to the gate lines 70 at the right end of the liquid crystal panel 51.

The liquid crystal panel 51 is injected between the lower substrate 52 on which the thin film transistor array is formed, the upper substrate 54 on which the color filter array is formed, and the lower substrate 52 and the upper substrate 54 together with various signal lines. Containing liquid crystals. The liquid crystal panel 51 displays an image in the image display area 71 by liquid crystal cells formed at each intersection of the gate lines 70 and the data lines 68. Data pads extended from the data line 68 and gate pads extended from the gate line 70 are positioned in the outer region of the lower substrate 52 positioned at the outer portion of the image display area 71. In addition, in the outer region of the lower substrate 52, a LOG type signal line group 92 for transmitting the gate driving signals supplied to the gate drive IC 66 is positioned.

A data drive IC 60 is mounted on the data TCP 58, and the data TCP 58 outputs the lower pads 52 and the output pads of the data PCB 62 through input / output pads connected to the data drive IC 60. ) Data pads. In particular, the first data TCP 58 further includes a gate drive signal transmission line group connected to the LOG type signal line group on the lower substrate 52. The gate drive signal transmission line group supplies the gate drive signals supplied from the timing controller and the power supply unit to the LOG type signal line group 92 via the data PCB 62.

The data drive ICs 60 convert the pixel data signal, which is a digital signal, into a pixel voltage signal, which is an analog signal, and supply the same to the data lines 68 on the liquid crystal panel 51.

A gate drive IC 66 is mounted on the gate TCP 64, and the gate TCP 64 is connected to the gate pads of the lower substrate 52 through output pads connected to the gate drive IC 66. The gate TCP 64 further includes a gate drive signal transmission line group connected between the LOG signal line group 76 of the lower substrate 52 and the gate drive IC 66.

The gate drive ICs 66 sequentially supply the scanning signal, that is, the gate high voltage signal VGH, to the gate lines in response to the input control signals. In addition, the gate drive ICs 66 supply the gate low voltage signal VGL to the gate lines 70 in a period other than the period in which the gate high voltage signal VGH is supplied.

The LOG signal line group 92 typically includes DC voltage signals supplied from a power supply such as a gate high voltage signal VGH, a common voltage signal VCOM, a ground voltage signal GND, and a power supply voltage signal VCC. The signal lines are configured to supply the gate control signals supplied from the timing controller, such as the gate start pulse GSP, the gate shift clock signal GSC, and the gate output enable signal GOE. The LOG signal line group 92 is formed of the gate metal in the same manner as the gate lines 70. The LOG signal line group 92 includes a predetermined line resistance component (X). In addition, an ACF (not shown) for connecting the signal lines on the lower substrate 52 and the input / output pad includes a predetermined connection resistance component (Y). In addition, the lines formed on the TCP or the chip on film (COF) include a predetermined line resistance component (Z). As the resistance components are proportional to the line length, the resistance values increase as the distance from the data PCB 62 increases, thereby decreasing the gate driving signal.

In order to prevent distortion of the gate low voltage VGL among the gate driving signals supplied to the gate drive IC 66 by the resistor, the gate low voltage line 90 is disposed on the right outer region of the image display unit 71. Form separately.

FIG. 6 is a detailed view illustrating a gate drive IC connected to a gate low voltage line of the liquid crystal display illustrated in FIG. 5.

Referring to FIG. 6, first to mth PMOS transistors T1 to Tm are formed between the gate low voltage lines 90 and the gate drive ICs 66, respectively.

The gate drive IC 66 is a shift register (not shown) that sequentially generates scan pulses SP in response to a gate start pulse GSP and a gate shift clock GSC supplied from a timing controller (not shown). And a level shifter 94 for shifting the voltage of the scan pulse SP to a level suitable for driving the thin film transistor.

The shift register is supplied with the gate start pulse GSP from the timing controller and performs a shift operation in response to the gate shift clock GSC to sequentially supply the scan pulse SP to the level shifter 94 and the next shift register. do.

The level shifter 94 includes an NMOS transistor Q1 positioned between the gate high voltage line VGH and the gate line GL, and a resistor Rs positioned between the gate line GL and the base voltage GND. It is provided. Here, the gate terminal of the NMOS transistor Q1 is connected with the scan pulse SP, the drain terminal is connected with the gate high voltage VGH, and the source terminal is connected with the gate line GL. In addition, the resistor Rs is formed to be several degrees or more to prevent the gate high voltage VGH from flowing to the base voltage GND when the NMOS transistor is turned on.

The first to mth PMOS transistors T1 to Tm are formed to be connected to the first to mth gate lines GL1 to GLm, respectively. The gate terminal and the drain terminal of the first to mth PMOS transistors T1 to Tm are connected to the output terminal of the gate drive IC 66, and the source terminal is connected to the gate low voltage line 90.

When a high logic signal is input to the gate terminals of the first to mth PMOS transistors T1 to Tm, the first to mth PMOS transistors T1 to Tm are turned off. On the other hand, when a low logic signal is input to the gate terminal, the first to m th PMOS transistors T1 to Tm are turned on to apply the gate low voltage VGL to the first to m th gate lines GL1 to GLm. do.

The channel widths of the first to mth PMOS transistors may be changed for each of the first to mth gate lines GL1 to GLm to compensate for line resistances that increase as the distance from the data PCB increases.

The gate low voltage line 90 is connected to the source terminals of the first to m th PMOS transistors T1 to Tm, and is supplied with a gate low voltage VGL generated from a power supply unit (not shown). Here, the gate low voltage VGL is relatively higher than the base voltage GND. The gate low voltage line 90 is formed of the same gate metal layer as the gate line GL on the right outer side of the image display portion 71.

Looking at the operation of the liquid crystal display having such a configuration as follows.

First, when the high logic scan pulse SP is supplied from the shift register, the NMOS transistor Q1 of the level shifter 94 is turned on so that the gate high voltage VGH becomes the first to mth gate lines GL1 to GLm. Is supplied to either. Here, the high logic scan pulse SP is sequentially applied to the first to m th gate lines GL1 to GLm.

For example, assuming that the gate high voltage VGH is supplied to the first gate line GL1, the first PMOS transistor T1 connected to the first gate line GL1 is turned off and the gate low voltage VGL is turned off. ) Is not supplied to the first gate line GL1, so the thin film transistors connected to the first gate line GL1 are turned on by the gate high voltage VGH. Then, the gate high voltage VGH is sequentially applied to the second to m th gate lines GL2 to GLm, and the thin film transistors connected to the second to m th gate lines GL2 to GLm are sequentially turned on.

When the low logic scan pulse SP is supplied from the shift register, the NMOS transistor Q1 of the level shifter 94 is turned off so that the base voltage GND is supplied with the high logic scan pulse. Supply to the remaining gate lines except. For example, assuming that the ground voltage GND is supplied to the second gate line GL2, the second PMOS transistor T2 connected to the second gate line GL2 is turned on so that the gate low voltage VGL is turned on. The thin film transistor supplied to the second gate line GL2 and connected to the second gate line GL2 is turned off.

As described above, in the LOG type liquid crystal display according to the first exemplary embodiment of the present invention, the gate low voltage line 90 is formed in the right outer region of the image display unit 71 so that the resistance component applied to each gate line becomes the same. The luminance difference between blocks can be reduced. In addition, since the gate-low voltage line 90 is not required to be formed in the LOG signal line group, the number of input lines of the gate drive IC 66 can be reduced.

7 is a diagram illustrating a LOG type liquid crystal display device according to a second embodiment of the present invention.

Referring to FIG. 7, first to mth resistors R1 to Rm are formed between the gate low voltage lines 90 and the gate drive ICs 66, respectively.

The gate drive IC 66 is a shift register (not shown) that sequentially generates scan pulses SP in response to a gate start pulse GSP and a gate shift clock GSC supplied from a timing controller (not shown). And a level shifter 94 for shifting the voltage of the scan pulse SP to a level suitable for driving the thin film transistor. The level shifter 94 includes an NMOS transistor Q2 positioned between the gate high voltage line VGH and the gate line GL. Here, the gate terminal of the NMOS transistor Q2 is connected to the scan pulse SP, the drain terminal is connected to the gate high voltage VGH, and the source terminal is connected to the gate line GL.

The first to mth resistors R1 to Rm are formed to be connected to the first to mth gate lines GL1 to GLm, respectively. The first to mth resistors R1 to Rm may prevent variation in the gate high voltage VGH or the gate low voltage VGL supplied to the first to mth gate lines GL1 to GLm according to the scan pulse. To form.

The first to mth resistance values R1 to Rm may be sequentially reduced for each of the first to mth gate lines GL1 to GLm. Accordingly, line resistance components that increase with distance from the data PCB may be relatively compensated by this resistance value.

The gate low voltage line 90 is connected to the first to m th resistors R1 to Rm and is supplied with a gate low voltage VGL generated from a power supply unit (not shown). The gate low voltage line 90 is formed of the same gate metal layer as the gate line GL on the right outer side of the image display unit.

Looking at the operation of the liquid crystal display having such a configuration as follows.

First, when the high logic scan pulse SP is supplied from the shift register, the NMOS transistor Q2 of the level shifter 94 is turned on so that the gate high voltage VGH becomes the first to mth gate lines GL1 to GLm. Is supplied to either. Here, the high logic scan pulse SP is sequentially applied to the first to m th gate lines GL1 to GLm.

For example, assuming that the gate high voltage VGH is supplied to the first gate line GL1, the gate high voltage VGH is reduced to a predetermined voltage by the gate low voltage VGL and the first resistor R1. However, since the gate high voltage VGH is continuously supplied in the high logic scan pulse period, this can be compensated for. The thin film transistor connected to the first gate line GL1 to which the gate high voltage VGH is supplied is turned on.

Then, the high logic scan pulse SP is sequentially applied to the second to mth gate lines GL2 to GLm, and the thin film transistors connected to the second to mth gate lines GL2 to GLm are sequentially turned on. do.

When the low logic scan pulse SP is supplied from the shift register, the NMOS transistor Q2 of the level shifter 94 is turned off. Accordingly, the gate lines GL1 to GLm connected to the NMOS transistor Q2 include infinite resistance components. As a result, an infinite resistance component and a resistor R are connected in series to form a potential of 0 V in the gate lines GL. Accordingly, the gate line voltage GLGL having a relatively high potential is supplied to the gate line GL. The thin film transistor connected to the gate line GL is turned off.

As described above, in the LOG type liquid crystal display according to the second exemplary embodiment of the present invention, the gate low voltage line 90 is formed in the right outer region of the image display unit 71 so that the resistance component applied to each gate line GL is the same. Therefore, the luminance difference between the horizontal line blocks can be reduced. In addition, since the gate low voltage line 92 is not required to be formed in the LOG signal line group, the number of input lines of the gate drive IC 66 can be reduced.

As described above, in the LOG type liquid crystal display device according to the present invention, a gate low voltage line is formed in the right outer region of the image display portion. As a result, since the resistance component applied to each gate line becomes the same, the luminance difference between the horizontal line blocks can be reduced. In addition, since the gate-low voltage line of the LOG signal signal group does not need to be formed, the number of input lines of the gate drive IC can be reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

A display unit in which display signal lines for data display are formed and pixel cells are arranged in a matrix; A plurality of integrated circuits connected to the display signal lines for supplying a first driving signal required for the display signal lines; A supply line formed on a non-display area positioned at an outer side of the display unit and supplying a second driving signal required for the display signal wires; And a switching element formed between the display signal wires and the supply line to switch a current path between the display signal wires and the supply line. The method of claim 1, The integrated circuit is a gate drive integrated circuit, the display signal lines are a gate line, the first driving signal is a gate high voltage signal, and the second driving signal is a gate low voltage signal. Type liquid crystal display device. The method of claim 2, The gate drive integrated circuit A second switching element connected between the gate line and the gate high voltage line; And a resistance connected between said gate line and a ground voltage. The method of claim 2, A scan pulse is supplied to a gate terminal of the switching element, a gate high voltage is supplied to a drain terminal, and the gate line is connected to a source terminal. A display unit in which display signal lines for data display are formed and pixel cells are arranged in a matrix; A plurality of integrated circuits connected to the display signal lines for supplying a first driving signal required for the display signal lines; A supply line formed on a non-display area positioned at an outer side of the display unit and supplying a second driving signal required for the display signal wires; And a resistance formed between the display signal lines and the supply line. The method of claim 5, wherein The integrated circuit is a gate drive integrated circuit, the display signal lines are a gate line, the first driving signal is a gate high voltage signal, and the second driving signal is a gate low voltage signal. Type liquid crystal display device. The method of claim 6, The gate drive integrated circuit And a switching element connected between the gate line and the gate high voltage line. The method of claim 7, wherein A scan pulse is supplied to a gate terminal of the switching element, a gate high voltage is supplied to a drain terminal, and the gate line is connected to a source terminal. The method according to any one of claims 2 and 6, And the supply line is formed on a non-display area opposite to an area in which the gate drive integrated circuit is mounted with respect to the display unit.

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