KR100854903B1 - Programming method of flash memory device - Google Patents

Abstract

The present invention relates to a method of programming a flash memory device, and after performing a program on a selected page, the program verification is performed using different verification voltages according to the position of the page, thereby reducing the difference in threshold voltage distribution of all cells. As a result, margins with lead wires can be secured. A method of programming a flash memory device capable of improving the reliability of a NAND type flash memory device by securing a margin with a lead wire is provided.

Program Verification, Page, Verification Voltage, Threshold Voltage Distribution

Description

Method of programming a flash memory device

1 is a configuration diagram of a cell string for explaining the configuration of a general NAND flash memory device.

FIG. 2 is a graph illustrating threshold voltage variation of a NAND type flash memory cell after typical cycling and baking; FIG.

3 (a) and 3 (b) are diagrams for explaining the concept of an all "0" pattern and a check boat pattern of a NAND type flash memory device;

4 is a graph illustrating threshold voltage distributions of one block, even cells, and odd cells of a NAND type flash memory device.

FIG. 5 is a graph illustrating threshold voltage distributions of cells 62 and 63 of the NAND type flash memory device, even cells excluding 62, and odd cells excluding 63. FIG.

FIG. 6 is a diagram for explaining parasitic capacitance present in a NAND type flash memory device. FIG.

7 is a block diagram illustrating a cell string for explaining a method of programming a NAND-type flash memory device according to an exemplary embodiment.

The present invention relates to a method of programming a flash memory device, and in particular, by performing a program verification by varying a verification voltage according to a position of a program cell, a difference in threshold voltage distribution of all cells can be reduced, thereby securing a margin with a lead wire. The present invention relates to a flash memory device program method.

NAND-type flash memory devices are used in portable electronic systems such as notebooks, PDAs, and cellular phones, as well as in computer BIOS, printers, and USB drivers. The range of use is expanding.

The NAND-type flash memory device includes a plurality of cell blocks. One cell block includes a cell string 101 and 102 and a cell string connected in series with a plurality of cells for storing data, as shown in FIG. A drain select transistor 110 is formed between the 101 and 102 and even bit lines and the odd bit lines even BL and odd BL, and a source select transistor between the cell strings 101 and 102 and the common source line CSL. 120 is configured. The drain select transistor 110 is commonly connected to the drain select line DSL, and the source select transistor 120 is commonly connected to the source select line SSL. In addition, cells connected to the even bit line even BL are assigned even numbers 0, 2, 6, ..., 60, 62 from cells adjacent to the source select line SSL, and an odd bit line odod BL. Cells connected to are assigned odd numbers 1, 3, 5, ..., 61, 63 from cells adjacent to the source select line SSL. Meanwhile, a predetermined bias is applied to the cell gate through the word line WL for a predetermined operation of the cell, and a predetermined bias is applied to the drain through the even bit line or the odd bit line. The predetermined bias is applied to the source through the common source line CSL. In addition, cells with the same number connected to one word line, for example, gates connected to the last word line WL31 and cells 62 connected to different even bit lines even BL, operate simultaneously at the program or read operation. This unit is called a page. That is, a page refers to the number of cells that can be operated at one time. On the other hand, the cell of the NAND type flash memory device is formed with a gate in which a tunnel oxide film, a floating gate, a dielectric film, and a control gate are stacked in a predetermined region on a semiconductor substrate, and junctions are formed on both sides of the gate.

The NAND type flash memory device configured as described above is programmed and erased by injecting or withdrawing electrons into the floating gate. Both electrical programming and erasing of such NAND-type flash memory devices is made possible by FN tunneling. That is, the electrons are moved by the strong electric field through the thin tunnel oxide film, and the threshold voltage is changed to perform the program and erase functions, thereby deteriorating the tunnel oxide film.

The flow of electrons through the tunnel oxide film during the program or erase operation creates an electron trap in the tunnel oxide bulk, and traps any electrons or holes at the interface between the tunnel oxide film and the semiconductor substrate. Before the hole is trapped, it creates a neutral trap center that is in a neutral state. The electrons trapped in the tunnel oxide bulk reduce the FN current and change the threshold voltage because the flat band voltage rises. The reason why the flat band voltage rises is almost similar to the case where electrons are trapped in the tunnel oxide film, and the electrons are occupied in the floating gate, so it can be thought of as a programmed cell. If there is an electron, the energy wall that the electron has to cross is thickened.

On the other hand, the neutral trap center at the interface between the semiconductor substrate and the tunnel oxide film lowers the speed of electrons when current flows through the channel of the cell, thereby lowering the GM of the cell. However, when the cell state is actually determined by reading the state of the cell, the cell state is determined according to how much current flows in the cell. Thus, when the GM of the cell is lowered, the threshold voltage of the cell is increased.

The above has described the deterioration phenomenon of the tunnel oxide film due to cycling, and the opposite phenomenon occurs in the baking test after cycling. In the baking operation after cycling, electrons trapped in the tunnel oxide bulk are detrapted again, so that the neutral trap center is healed and disappears. As a result, when these two phenomena undergo cycling and baking, a threshold voltage drop occurs, which is the most important characteristic that determines the reliability of NAND-type flash memory devices.

These cycling and baking characteristics are slightly different depending on the program pattern, and representative characteristics thereof are shown in FIG. 2. Figure 2 shows the characteristics of the threshold voltage change of the NAND-type flash memory cell after cycling and baking in general, and shows the threshold voltage change after baking for 10,000 hours and baking for 24 hours at 250 ℃. In FIG. 2, "A" represents an all "0" pattern before baking, "B" represents a checkerboard pattern before baking, and "C" represents an all "0" pattern after baking. "D" represents the checkerboard pattern after baking. As shown in Fig. 2, the worst pattern in the baking characteristics is an all "0" pattern. The reason for this is that the state in which all the cells are programmed in one string is the most affected by GM because the state has the largest resistance. Here, the all "0" pattern is a pattern in which all cells are programmed as shown in FIG. 3 (a), and the check board pattern is a program cell and an erase cell are repeated as shown in FIG. 3 (b). This is a pattern in which a program cell and an erase cell are adjacent to each other.

4 shows threshold voltage distributions of one block A, even pages B, and odd pages C, and FIG. 5 shows pages 62C and 63D. Threshold voltage distributions of the even pages A except 62 and the odd pages B except 63 are shown. As can be seen from FIG. 4 and FIG. 5, the page-specific distribution of all zero patterns has a threshold voltage of about 0.1 to 0.2 V higher than the odd pages, and is adjacent to the drain select line DSL. Page 62 and page 63 have a lower threshold voltage of 0.2 to 0.3V than other pages. The reason for this result is as follows.

In the case of a NAND type flash memory device, various parasitic capacitances exist. Two of the most representative ones are illustrated in FIG. 6, which is an interference between capacitance CFGY due to an interference between adjacent floating gates in a word line direction and an adjacent floating gate in a bit line direction. This is due to the capacitance (CFGX). This parasitic capacitance causes a flash memory cell to have a threshold voltage that varies depending on a program or erase state of an adjacent cell. However, when looking at all "0" program operation, the program operation is performed in the order of page numbers. If page 0 program operation is executed first, page 0 distribution starts at 1V. However, after page 1 is programmed, the threshold voltage increases about 0.1 to 0.2V by the capacitance of CFGX in the case of page 0. If page 2 is programmed again, the threshold voltage is raised again by CFGY. As described above, in the case of even pages, a threshold voltage increase is caused by both CFGX and CFGY, and in the case of odd pages, only a threshold voltage increase is caused by CFGY, so the threshold voltage distribution of the even pages is higher. In addition, in the case of page 62, the threshold voltage increases due to the program operation of page 63. Therefore, the threshold voltage is lower than the other even pages. In the case of page 63, the threshold voltage rise because the program operation is performed last. There is no effect.

For the above reasons, pages 62 and 63 have the lowest threshold voltage and the margin with the lowest lead. Therefore, failures in most cycling and baking tests occur on pages 62 and 63.

An object of the present invention is to raise the program verify voltage of an odd page by the difference of the threshold voltage due to the bit line direction interference, and to verify the last page, the program verify pages 62 and 63 also have a threshold due to the interference effect in the word line direction. The present invention provides a method of programming a flash memory device capable of increasing the voltage as much as possible to secure a margin with a lead wire.

A program method of a flash memory device according to an exemplary embodiment may include dividing a plurality of pages in a memory block into two or more page groups; Setting different verify voltages for the respective page groups; And after performing a program on the selected page, performing program verification by using a verification voltage set according to a page group to which the page on which the program is executed belongs.
The page groups include a first page group including the last even page programmed last in the memory block, a second page group including the last odd page programmed last in the memory block, and the last even A third page group including other even pages other than the page; And dividing into fourth page groups including other odd pages except for the last odd page.
The first to fourth verification voltages set for the first to fourth page groups are respectively higher than the third verification voltage, the fourth verification voltage is higher than the fourth verification voltage, and the first verification voltage is higher than the fourth verification voltage. The second verification voltage is higher than the first verification voltage.

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Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

FIG. 7 is a block diagram illustrating a cell string for explaining a method of programming a NAND type flash memory device according to an exemplary embodiment.

Referring to FIG. 7, all even pages excluding page 62 (0, 2, 4, ..., 60) 100, all odd pages except page 63 (1, 3, 5, ..., 61) (200), and divided into four groups of page 62 (300) and page 63 (400).

Then, a program operation is performed on the selected page. To program the selected page, apply a program voltage of about 16V to 19V to the selected word line using the ISPP (Incremental Step Pulse Program) method, apply a pass voltage of about 10V to the unselected word line, and select the selected bit line. The ground voltage Vss is applied to the power supply voltage, and the power supply voltage Vcc is applied to the unselected bit lines. At this time, the power supply voltage Vcc is applied to the drain select line DSL, the ground voltage Vss is applied to the source select line SSL, and the power supply voltage Vcc is applied to the common source line CSL. The ground voltage Vss is applied to the bulk.

The program verification is performed. The program verification is performed by varying the program verification voltage for each group to which the page on which the program is executed belongs. First, for program verification of a page belonging to all even pages (0, 2, 4, ..., 60) 100 except for page 62, a verify voltage of about 1V is applied to the selected word line, and the unselected word A power supply voltage Vcc is applied to the line, a voltage of about 1 V is applied to the selected bit line, and a ground voltage Vss is applied to the unselected bit line. In this case, a power supply voltage Vcc is applied to the drain select line DSL and the source select line SSL, and a ground voltage Vss is applied to the common source line CSL and the P well. For the program verification of the page belonging to all the odd pages (1, 3, 5, ..., 61) 200 except for the 63rd page, the threshold voltage transition amount due to the bit line direction interference effect (0.1 to Apply a verification voltage of 1.1 to 1.2V as high as 0.2V) to the selected word line, apply a power supply voltage (Vcc) to the unselected word line, apply a voltage of about 1V to the selected bit line, The ground voltage Vss is applied to the bit line. In this case, a power supply voltage Vcc is applied to the drain select line DSL and the source select line SSL, and a ground voltage Vss is applied to the common source line CSL and the P well. In addition, for program verification of page 62, a verification voltage of 1.2 to 1.3 V, which is as high as the threshold voltage transition amount (0.2 to 0.3 V) due to the word line direction interference effect, is applied to the selected word line. A power supply voltage Vcc is applied to an unselected word line, a voltage of about 1 V is applied to a selected bit line, and a ground voltage Vss is applied to an unselected bit line. In this case, a power supply voltage Vcc is applied to the drain select line DSL and the source select line SSL, and a ground voltage Vss is applied to the common source line CSL and the P well. For the program verification of the page 400, the threshold voltage transition amount (0.1 to 0.2 V) due to the bit line direction interference effect and the threshold voltage transition amount (0.2 to 0.3) due to the word line direction interference effect are required. Apply a verification voltage of about 1.3 to 1.5V plus V) to the selected word line, apply a power supply voltage (Vcc) to the unselected word lines, and apply a voltage of about 1V to the selected bit lines. The ground voltage Vss is applied to the bit line. In this case, a power supply voltage Vcc is applied to the drain select line DSL and the source select line SSL, and a ground voltage Vss is applied to the common source line CSL and the P well.

After program verification, the program is executed again while increasing the program voltage for the unprogrammed pages.

As described above, by applying the program verify voltage differently according to the position of the page, the threshold voltages of all cells are matched in the all-zero pattern to eliminate margin differences between lead lines, thereby improving cell reliability.

As described above, according to the present invention, after the program is executed for the selected page, the program verification is performed using different verification voltages according to the position of the page, thereby reducing the difference in threshold voltage distribution of all cells, and thus margining with lead wires. Can be secured. By securing margins with lead wires, the reliability of NAND-type flash memory devices can be improved.

Claims (6)

Dividing the plurality of pages in the memory block into two or more page groups; Setting different verify voltages for the respective page groups; And And performing a program verification by using a verification voltage set according to a page group to which the program-programmed page belongs after executing a program on a selected page. The method of claim 1, The page groups, A first page group including the last even page programmed last in the memory block; A second page group including a last odd page last programmed in the memory block; A third page group including other even pages other than the last even page; And A fourth page group including other odd pages except for the last odd page Program method of a flash memory device, characterized in that divided by. The method of claim 2, The first to fourth verification voltages respectively set for the first to fourth page groups are: The fourth verification voltage is higher than the third verification voltage, The first verification voltage is higher than the fourth verification voltage, And the second verification voltage is higher than the first verification voltage. delete delete delete

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