KR100851999B1 - Io sense amplifier - Google Patents

Abstract

The input / output sense amplifier of the present invention includes an input comparator for receiving a pair of data signals and generating a voltage difference between the first and second nodes according to the difference; Up means for pulling up the second output node voltage according to the first output node voltage and pulling up the first output node voltage according to the second output node voltage, A pull-down unit receiving the first and second node voltages and pulling down the third node voltage according to the second output node voltage and pulling down the fourth node voltage according to the first output node voltage; And a connection unit connecting the pull-up unit and the pull-down unit as the pre-charging signal is enabled.

Description

IO Sense Amplifier

1 is a circuit diagram of an input / output sense amplifier according to the related art,

2 is a circuit diagram showing an embodiment of an input / output sense amplifier according to the present invention,

3 is a circuit diagram showing another embodiment of the input / output sense amplifier according to the present invention.

Description of the Related Art [0002]

100: input comparator 110: first transmission element

120: second transmission element 210: pull-

220: pull down part 230: connection part

300: precharging unit 310: first precharging element

320: second precharging element 330: equalizing section

400: sensing unit 500: sub-precharging unit

The present invention relates to a semiconductor integrated circuit, and more particularly, to an input / output sense amplifier.

Generally, in a DRAM or other memory or logic configuration, an operation of amplifying an output micro-potential signal is often used. In a semiconductor memory device such as a DRAM or an ESRAM, the potential of a data signal output from the memory cell is very small The micro-potential signal is amplified firstly through a bit line sense amplifier and secondarily through a data bus line sense amplifier, and is discriminated as logic low and logic high data.

However, in a general semiconductor chip including a semiconductor memory currently in use, research is underway in the direction of lowering the operating voltage due to power consumption and reliability problems, so that the potential of the data signal output from the memory cell becomes weaker due to the lowered operating voltage Not only the potential difference between the two signals applied to the input terminals of the respective sense amplifiers becomes finer but also the activation time of each data line is reduced due to the ongoing speedup trend and the sensing operation of the data signal having the reduced potential difference becomes more difficult In fact.

1 is a circuit diagram of an input / output sense amplifier according to the related art.

The input / output sense amplifier according to the related art includes an input comparator 100 for receiving a pair of data signals DATA_IN and DATA_INB and sensing a difference therebetween, A precharging unit 300 for fixing the voltages of the output nodes N3 and N4 at a high level according to a precharging signal Pcharge and a precharging unit 300 for precharging the output nodes N3 and N4 according to the precharging signal Pcharge. An input comparator 100 and a sub-precharging unit 500 for providing a current path to the sensing unit 400.

The operation principle of the input / output sense amplifier shown in FIG. 1 is as follows.

As the precharge signal Pcharge is enabled, the seventh transistor M7 is turned on. Therefore, the current path of the input signal comparator 100 and the sensing unit 400 is provided, and the input / output sense amplifier performs sensing and amplifying operations. The gate-source voltage Vgs1 of the first transistor M1 is higher than that of the second transistor M2 when the voltage level of the data signal DATA_IN is relatively higher than the voltage of the inverted data signal DATA_INB. A large amount of current flows through the first transistor M1 and the voltage of the first node N1 is lower than the voltage of the second node N2. As a result, the gate-source voltage Vgs5 of the fifth transistor M5 is increased compared to the sixth transistor M6, the voltage of the third node N3 is decreased, and the voltage of the fourth node N4 is increased .

The gate-source voltage Vgs4 of the fourth transistor M4 is increased as compared with the third transistor M3 due to the variation of the voltages of the third and fourth nodes N3 and N4, The driving power of the transistor M4 is increased and the voltage of the fourth node N4 becomes higher and the voltage of the third node N3 becomes lower. When the voltage level of the data signal DATA_IN is higher than that of the inverted data signal DATA_INB, the fourth node N4, which is the output node of the input / output sense amplifier, is at a high level. The voltage becomes a low level.

When the precharge signal Pcharge is disabled, the seventh transistor M7 is turned off. Accordingly, the first to sixth transistors M1 to M6 are in a floating state, and the eighth to tenth transistors M8 to M10 are turned on and the third and fourth nodes N3 and N4 To a high level.

The input / output sense amplifier according to the related art has a precharging signal enabled, and when the seventh transistor M7 is turned on, the first and second transistors M1 and M6 are turned on by the drain-source voltage applied to the seventh transistor M7, And M2, the sensitivity of the sense amplifier to the input data signal is deteriorated, and the sensing operation is slowed down. Even if the first and second transistors are mismatched, malfunction may occur. Also, the drain-source voltage difference of the seventh transistor M7 affects the third through sixth transistors M6 performing the sensing and amplifying operations.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an input / output sense amplifier that performs a fast and stable sensing operation even at a low supply voltage.

According to an aspect of the present invention, there is provided an input / output sense amplifier including an input comparator receiving a pair of data signals and generating a voltage difference between the first and second nodes according to the difference; Up means for pulling up the second output node voltage according to the first output node voltage and for pulling up the first output node voltage according to the second output node voltage; A pull down unit for receiving the first and second node voltages and pulling down the third node voltage according to the second output node voltage and pulling down the fourth node voltage according to the first output node voltage; And a connection unit connecting the pull-up unit and the pull-down unit as the pre-charging signal is enabled.

According to another embodiment of the present invention, there is provided an input / output sense amplifier including: an input comparator receiving a pair of data signals and generating a voltage difference between the first and second nodes according to the difference; A sensing unit performing sensing and amplifying operations according to third and fourth node potentials; And a connection unit connecting the first and second nodes of the input and output unit with the third and fourth nodes of the sensing unit as the precharging signal is enabled.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of an input / output sense amplifier according to the present invention.

The input / output sense amplifier according to the present invention includes an input comparator 100, a pull-up unit 210, a pull-down unit 220, a connection unit 230, and a precharging unit 300.

The input comparator 100 receives a pair of data signals DATA_IN and DATA_INB and generates a voltage difference between the first and second nodes N1 and N2 according to the difference. As shown in the figure, the input comparing unit 100 may include first and second transmitting elements 110 and 120. The first and second transmission elements 110 and 120 are implemented as an NMOS transistor.

The pull-up unit 210 receives the supply power and pulls up the voltage of the second output node N4 according to the voltage of the first output node N3. The pull-up unit 210 pulls up the voltage of the second output node N4, (N3) voltage is pulled up. The pull-up unit 210 includes first and second PMOS transistors M3 and M4 that are configured to receive a power supply voltage VDD and to cross the output nodes N3 and N4 with respective gates and drains .

As shown in the figure, the pull-down unit 220 receives the voltages of the first and second nodes N1 and N2 and pulls down the voltage of the third node N5 according to the voltage of the second output node N4, And pulls down the voltage at the fourth node N6 according to the voltage of the first output node N3. The pull-down unit 220 includes first and second NMOS transistors M5 and M6 which are formed by connecting the first and second nodes N1 and N2 to their respective sources and crossing the respective gates and drains, respectively .

The connection unit 230 couples the pull-up unit 220 to the pull-up unit 210 in response to the precharge signal Pcharge being enabled. The connection unit 230 includes transmission elements 231 and 232 that connect the pull-up unit 210 and the pull-down unit 220 in response to the precharge signal Pcharge being enabled.

The connection unit 230 according to the present invention reduces the load due to the drain-source voltage difference in the sub-precharging unit 500, which is a precharging component of the prior art. Accordingly, the local sense amplifier according to the present invention can further sense the fine voltage difference between the data signals DATA_IN and DATA_INB to perform sensing and amplifying operations.

The precharging unit 300 includes first and second precharging elements 310 and 320 and an equalizing unit 330. The first and second precharging elements 310 and 320 are composed of ninth and tenth transistors M9 and M10 respectively and the equalizing part 330 is composed of an eleventh transistor M11.

The precharging unit 300 receives the precharging signal Pcharge at its gate and receives the ninth and tenth transistors M9 and M9 connected to the power supply VDD and the drains of the output nodes N3 and N4, And an eleventh transistor M11 that receives the precharging signal Pcharge at its gate and has drains and sources connected to the two output nodes N3 and N4, respectively.

The operation principle of the input / output sense amplifier shown in FIG. 2 is as follows.

When the precharge signal Pcharge is disabled, the ninth to eleventh transistors M9 to M11 are turned on, and the voltages of the output nodes N3 and N4 are fixed to a high level. In addition, since the seventh and eighth transistors M7 and M8 are turned off, the pull-up unit 210 and the pull-down unit 220 do not operate, and the third to sixth transistors M3 to M6 perform an amplifying operation Do not perform.

When the precharge signal Pcharge is enabled, the ninth to eleventh transistors M9 to M11 are turned off. The input comparator 100 receives the pair of data signals DATA_IN and DATA_INB and operates according to the data signals. The seventh and eighth transistors M7 and M8 are turned on and the third and fourth transistors The pull-up unit 220 and the pull-down unit 220 are connected to each other by connecting the pull-up unit 220 composed of the first and second transistors M3 and M4 and the fifth and sixth transistors M5 and M6, And the sensing and amplifying operation is performed as a cross-coupled latch circuit.

For example, when the data signal DATA_IN is higher in voltage level than its inverted signal DATA_INB, the gate-source voltage Vgs1 of the first transistor M1 is larger than the inverted signal DATA_INB of the first transistor M1, A larger current is supplied than the second transistor M2. As a result, the voltage of the first node N1 becomes lower than the voltage of the second node N2. As a result, the gate-source voltage Vgs5 of the fifth transistor M5 increases compared to the sixth transistor M6, and the fifth transistor M5 supplies a larger current than the sixth transistor M6 And the voltage of the third node N3 becomes lower than the voltage of the fourth node N4. The gate-source voltage Vgs4 of the fourth transistor M4 receiving the third node N3 voltage as the gate voltage increases and the current supply of the fourth transistor M4 increases. As a result, A positive feedback occurs in which the voltage of the node N4 becomes higher and the voltage of the third node N3 becomes lower. Therefore, the output signal of the input / output sense amplifier becomes a signal obtained by further amplifying the voltage difference between the pair of data signals (DATA_IN and DATA_INB).

In the case of the input / output sense amplifier according to the related art, it is difficult to sensitively detect the voltage difference of the data signals (DATA_IN and DATA_INB) from the drain-source voltage required for the transistor for precharging. However, in the case of the input / The voltage difference required for precharging is omitted by placing the connection portion 230, which is a configuration for precharging, at a position higher than that of the transmission element constituting the input comparator 100. [ Therefore, the input / output sense amplifier according to the present invention can reserve the gate-source voltage (Vgs) of the transistor constituting the input comparator 100 by the voltage difference required for precharging, Even if the data signals DATA_IN and DATA_INB are input, sensing and amplification are quick and easy.

3 is a circuit diagram showing another embodiment of the input / output sense amplifier according to the present invention.

3, the input / output sense amplifier shown in FIG. 3 includes a precharging unit 300, a sensing unit 400, a connection unit 230, and an input comparing unit 100.

The input comparator 100 receives a pair of data signals DATA_IN and DATA_INB and generates a voltage difference between the first and second nodes N1 and N2 according to the difference. The configuration of the input comparator 100 is the same as that of the input comparator 100 shown in FIG.

The sensing unit 400 performs sensing and amplifying operations according to potentials of the fifth and sixth nodes N5 and N6. That is, when the connection unit 230 receives the voltage difference between the first node N1 and the second node N2 as the precharge signal Pcharge is enabled, The sensing and amplifying operations are performed by the voltage difference between the nodes N5 and N6.

The connection unit 230 is connected to the first and second nodes N1 and N2 of the input and output unit 100 and the fifth and sixth nodes N1 and N2 of the sensing unit 400 as the precharge signal Pcharge is enabled. (N5, N6).

The input / output sense amplifier shown in FIG. 3 has a configuration in which the connection portion 230 shown in FIG. 2 is disposed between the pull-up portion 210 and the pull-down portion 220, The connection unit 230 is disposed between the pull-down unit 220 and the input comparing unit 100.

2 and 3, the input comparing unit 100 and the connecting unit 230 are implemented as an NMOS transistor, the precharging unit 300 is implemented as a PMOS transistor, and a sensing and amplifying operation is performed The input comparing unit 100 and the connecting unit 230 may be implemented as a PMOS transistor and the precharging unit 300 may be implemented as an NMOS transistor, It is needless to say that the same principle applies to a method of implementing a cross-coupled latch circuit for performing amplification operation, that is, a circuit constituted by replacing the NMOS transistor and the PMOS transistor.

The present invention can be applied to any field to which a DRAM input / output sense amplifier and a sense amplifier are applied. For example, it can be used as a high-speed input / output receiver sense amplifier.

Thus, those skilled in the art will appreciate that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof.

It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

The input / output sense amplifier according to the present invention has the effect of improving the performance of the input / output sense amplifier by rapidly sensing and amplifying low-level data signals even in the low supply power source.

Claims (17)

An input comparator receiving a pair of data signals and generating a voltage difference between the first and second nodes according to the difference; Up means for pulling up the second output node voltage according to the first output node voltage and for pulling up the first output node voltage according to the second output node voltage; A pull down unit for receiving the first and second node voltages and pulling down the third node voltage according to the second output node voltage and pulling down the fourth node voltage according to the first output node voltage; And And a connection unit connecting the pull-up unit and the pull-down unit as the pre-charging signal is enabled. The method according to claim 1, And a precharging unit for connecting or disconnecting the first and second output node voltages to / from the power supply according to the precharging signal. The method according to claim 1, The input / And a first and a second transmission element receiving the pair of data signals and being driven according to the pair of data signals, respectively. The method of claim 3, The first and second transmission elements are each composed of an NMOS transistor having first and second nodes and drains connected to each other, each source connected to a ground line, and the pair of data signals being input to respective gates The input / output sense amplifier. The method according to claim 1, The pull- And a first pull-up element connected to the first power supply and a second pull-up element connected to the first power supply node and the second power supply node, respectively. The method according to claim 1, The pull- Wherein the first and second pull-down elements are configured by connecting the first and second nodes to respective sources and crossing the third and fourth nodes with respective gates and drains. The method of claim 5, wherein Wherein the first and second pull-up elements are constituted by PMOS transistors. The method of claim 6, wherein Wherein the first and second pull down elements are comprised of an NMOS transistor. The method according to claim 1, The connecting portion A first transfer element for receiving the precharged signal at a gate and for connecting the first node and the third node to a drain and a source, respectively; And And a second transfer element for receiving the precharging signal at the gate and for connecting the second node and the fourth node to a drain and a source, respectively. 10. The method of claim 9, Wherein the first and second transmission elements are comprised of an NMOS transistor. An input comparator receiving a pair of data signals and generating a voltage difference between the first and second nodes according to the difference; A sensing unit performing sensing and amplifying operations according to third and fourth node potentials; And And a connection unit for connecting the first and second nodes of the input and output unit with the third and fourth nodes of the sensing unit as the precharging signal is enabled. 12. The method of claim 11, And a precharging unit for connecting or disconnecting the output voltage of the sensing unit with the power supply according to the precharging signal. 12. The method of claim 11, The input / And a first and a second transmission element receiving the pair of data signals and being driven according to the pair of data signals, respectively. 14. The method of claim 13, The first and second transmission elements are each composed of an NMOS transistor having first and second nodes and drains connected to each other, each source connected to a ground line, and the pair of data signals being input to respective gates The input / output sense amplifier. 12. The method of claim 11, The sensing unit includes: And a cross-coupled latch circuit performing sensing and amplifying operations according to the third and fourth node potentials. 12. The method of claim 11, The connecting portion A first transfer element for receiving the precharged signal at a gate and for connecting the first node and the third node to a drain and a source, respectively; And And a second transfer element for receiving the precharging signal at the gate and for connecting the second node and the fourth node to a drain and a source, respectively. 17. The method of claim 16, Wherein the first and second transmission elements are comprised of an NMOS transistor.

Images