KR100850210B1 - Reduced size and level shifter can be driven by low level input voltage - Google Patents

Abstract

A level shifter capable of driving at a low level voltage is disclosed. The level shifter according to the present invention includes a bias portion and a voltage converting portion. The bias section operates in response to the bias voltage. The voltage conversion component is connected in series with a bias unit, and receives a low level input voltage and converts the voltage level of the input voltage to output a high level output voltage. The bias voltage is adjusted so that the current in the bias section has the same value as the current in the voltage converter section. The level shifter according to the present invention can output a voltage of a high voltage level by using a low level input voltage by adjusting a bias voltage value, and has an advantage of reducing its magnitude.

Description

Level shifter which can drive at low input voltage and having reduced size}

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a view showing a conventional level shifter.

2 is a view showing a level shifter according to the present invention.

3A is a view for explaining the size of transistors included in a conventional level shifter.

3B is a view for explaining the size of transistors included in the level shifter according to the present invention.

4 is a view for showing the low voltage driving performance of the level shifter according to the present invention.

** Description of the symbols for the main parts of the drawings **

200: level shifter

210: bias unit

230: voltage shift unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shifter provided in an LCD source drive, and more particularly to a level shifter capable of driving at low voltage.

1 is a diagram illustrating a conventional level shifter 100.

High voltage is required to drive a source driver of a liquid crystal display (LCD) device. Therefore, a voltage required for driving the source driver is obtained by using a level shifter capable of inputting a low voltage signal and outputting a high voltage signal.

The conventional level shifter 100 includes a first P-type MOS transistor P1, a second P-type MOS transistor P2, a third P-type MOS transistor P3, a fourth P-type MOS transistor P1, and a first An N-type MOS transistor N1 and a second N-type MOS transistor N1 are provided.

Hereinafter, a case in which voltages of 3 V and 0 V are respectively applied to the input voltage S_data and the inverting input voltage S_datab will be described. In addition, a high power supply voltage VDD2 and a low power supply voltage VSS2 are connected to a voltage source of 15V and 0V (graund), respectively.

An input voltage S_data of 3 V is input to the gate terminal of the first N-type MOS transistor N1. As a result, the first N-type MOS transistor N1 is turned on and the first P-type MOS transistor P1 is turned off.

A 0 V inverting input voltage S_datab is input to the gate terminal of the second N-type MOS transistor N2. As a result, the second N-type MOS transistor N2 is turned off, and the second P-type MOS transistor P2 is turned on.

Since the first N-type MOS transistor N1 is turned on, a low power supply voltage VSS2 is applied to the drain terminal of the first N-type MOS transistor N1. Accordingly, since the low power supply voltage VSS2 is input to the gate terminal of the fourth P-type MOS transistor N4, the fourth P-type MOS transistor N4 is turned on.

Since the second P-type MOS transistor P2 and the fourth P-type MOS transistor P4 are turned on and the second N-type MOS transistor N2 is turned off, the power supply voltage VDD2 is high as the output voltage S_out. A voltage signal of 15V is outputted.

Since the first N-type MOS transistor N1 is turned on, the low power supply voltage VSS2 is applied to the drain terminal of the first N-type MOS transistor N1, so that the low power supply voltage VSS2 is the inverted output voltage S_outb. A voltage signal of 0 V is output.

However, when the level shifter 100 is driven at a low voltage (1.6V and 0V input as the input voltage and the inverted input voltage, respectively), the level shifter does not operate properly. It demonstrates below.

When the input voltage S_data 1.8V is input to the gate of the first N-type MOS transistor N1, the current driving capability of the transistor is reduced as compared with the input of 3V. On the other hand, the drain terminal of the fourth P-type MOS transistor P4 still receives the high power supply voltage VDD2. Therefore, the current driving capability of the third P-type MOS transistor P3 is not changed.

That is, the current flowing through the third P-type MOS transistor P3 becomes larger than the current flowing through the first N-type MOS transistor N1. As a result, the level shifter 100 does not operate normally due to a difference in current driving capability. I can't. In other words, the currents must be matched to the same value.

Here, the time point at which the first N-type MOS transistor N1 and the first P-type MOS transistor P1 are turned on together and the current flows is at the start of the operation of the level shifter, and is a time point at which the operating states of the transistors transition.

In order to prevent this, the length L (Length) of the first P-type transistor P1 and the second P-type MOS transistor P2 is adjusted to be larger so that the first P-type or second P-type MOS transistors P1 and P2 are adjusted. Reduce the amount of current flowing through

[Equation 1]

Referring to Equation 1, increasing the length L can reduce the current I flowing through the transistor. Therefore, in order for the existing level shifter 100 to operate normally by using an input voltage having a low voltage level, the length L of the first P-type transistors and the second P-type MOS transistors P1 and P2 is three times to four times. It should be doubled.

However, the length L of the transistor is a direct layer that determines the transistor size. Thus, increasing the length L increases the overall size of the transistor and the overall size of the source driver accordingly.

As described above, the conventional level shifter cannot be driven at low power, and in order to enable low power driving, the overall size of the chip is increased by increasing the size of the MOS transistor. This does not meet the tendency of miniaturization of chips or semiconductor devices.

An object of the present invention is to provide a level shifter that can be driven at a low input voltage.

Another technical object of the present invention is to provide a level shifter having a reduced size.

A level shifter according to an embodiment of the present invention for achieving the above technical problem includes a bias unit and a voltage converter.

The bias section operates in response to the bias voltage.

The voltage converter is connected in series with the bias unit, and receives a low level input voltage to convert the voltage level of the input voltage to output a high level output voltage.

The bias voltage is adjusted so that the current in the bias portion has the same value as the current in the voltage converting portion.

Preferably, the bias portion is connected at one end to the high power supply voltage, the voltage conversion portion is connected at one end to the other end of the bias portion, and the other end is connected to the low power supply voltage.

Preferably, the bias unit may include a first bias transistor having one end connected to a high power supply voltage and receiving a bias voltage through a gate, and a second bias transistor connected at one end to a high power supply voltage and receiving a bias voltage through a gate. Equipped.

Preferably, the voltage converter includes a first P-type MOS transistor having one end connected to the other end of the first bias transistor, a second P-type MOS transistor having one end connected to the other end of the second bias transistor, and one end of the first P-type MOS transistor A first N-type MOS transistor connected to the other end of the MOS transistor and a gate of the first P-type MOS transistor, the other end connected to a low power supply voltage, and receiving an input voltage through the gate, and one end of the second P-type MOS transistor And a second N-type MOS transistor connected to the other end of the transistor and the gate of the second P-type MOS transistor, the other end connected to a low power supply voltage, and receiving an inversion signal of the input voltage to the gate.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a view showing a level shifter according to the present invention.

2, the level shifter 200 according to the present invention includes a first bias transistor Pb1, a second bias transistor Pb2, a first P-type MOS transistor P1, and a second P-type MOS transistor P2. ), A first N-type MOS transistor N1, and a second N-type MOS transistor N2.

The source, drain, and gate of the first bias transistor Pb1 are connected to the high power supply voltage VDD2, the source of the first P-type MOS transistor P1, and the bias voltage S_BIAS, respectively.

The source, drain, and gate of the second bias transistor Pb2 are connected to the high power supply voltage VDD2, the second P-type MOS transistor P2, and the bias voltage S_BIAS, respectively.

The gate and the drain of the first P-type MOS transistor P1 are connected to the drain of the second P-type MOS transistor P2 and the drain of the first N-type MOS transistor N1, respectively. The gate and the drain of the second N-type MOS transistor P2 are connected to the drain of the first P-type MOS transistor and the drain of the second N-type MOS transistor N2, respectively.

The gate and the source of the first N-type MOS transistor N1 are connected to the input voltage S_data and the low power supply voltage VSS2, respectively. The gate and the source of the second N-type MOS transistor N2 are connected to the inverting input voltage S_datab and the low power supply voltage VSS2, respectively.

In the level shifter 200 according to the present invention, the value of the bias voltage S_BIAS is a current of the first N-type MOS transistor in consideration of the input voltage S_data value input to the first N-type MOS transistor N1. Determine the value.

That is, the current value flowing through the first N-type MOS transistor N1 is determined by Equation 1 above. Accordingly, the current value (first current value i1) of the first N-type MOS transistor N1 is predicted, and the value of the first bias voltage S_BIAS is determined so that the same current flows as the first current value i1. will be.

[수학식 2]

[Equation 2]

Referring to Equation 2, Wp and Lp represent the width and the length of the first bias transistor Pb1, respectively. The bias voltage S_BIAS becomes the gate voltage of the first bias transistor Pb1. Vgs becomes Vg-Vs, and Vs is the source voltage, so a low supply voltage (VSS) is applied. Vt is self-evident as a threshold voltage. According to Equation 2, the bias voltage S_BIAS, that is, the gate voltage value of the first bias transistor Pb1 is determined and input.

As described above, the bias voltage value is flexibly changed in consideration of the current value flowing in the first N-type MOS transistor N1, so that the level shift 200 may not operate due to a difference in current driving capability. It won't let you.

When a voltage of 3V is input as the input voltage S_data and 15V is input as the high power supply voltage VDD2, the bias voltage S_BIAS has a value of approximately VDD2-2V. In the above description, the approximate expression is slightly changed depending on the process variables shown in Equation 1 or Equation 2 and the change of the threshold voltage value Vth according to the driving conditions. Because there may be variations, it is impossible to specify exactly. Accordingly, the bias voltage S_BIAS may be determined in consideration of threshold voltages and other process variables in an environment in which a level shifter is used.

In addition, in order to prevent this in the related art, by taking the length L of the first and second P-type MOS transistors P1 and P2 large, it is possible to prevent the problem of increasing the overall size. This will be described below.

3A is a view for explaining the size of transistors included in a conventional level shifter.

Referring to FIG. 3A, the conventional level shifter 100 illustrated in FIG. 1 is based on a current ratio matching in which a current value varies in the first P-type MOS transistor P1 and the first N-type MOS transistor N1. In order to prevent malfunction, the length Lp of the first and second P-type MOS transistors P1 and P2 is made four times larger than the length Lp of the third and fourth P-type MOS transistors P3 and P4. Produced.

Therefore, as the length 4Lp of the first and second P-type MOS transistors P1 and P2 increases, the entire area of the level shifter increases.

3B is a view for explaining the size of transistors included in the level shifter according to the present invention.

Referring to FIG. 3B, as described above with reference to FIG. 2, by flexibly inputting the values of the bias voltage S_BIAS, transition operations of the transistors without increasing the lengths of the first and second bias transistors Pb1 and Pb2 are performed. At this point of time, malfunction due to the current non-matching phenomenon can be prevented.

Therefore, since the lengths of the first and second bias transistors Pb1 and Pb2 do not increase, the total area of the level shifter also does not increase.

4 is a view for showing the low voltage driving performance of the level shifter according to the present invention.

4 is a simulation result showing whether the level shifter malfunctions as the input voltage S_data decreases.

NN, FF, and SS indicate that process experimental conditions are variable. The temperature at each different process experimental condition is also varied as shown.

As shown in the related art, a level shifter (L / S) does not operate normally due to a current mismatch in some input voltage regions 401 of 1.7V and 1.6V, indicating an operation failure.

In contrast, the L / S according to the present invention can perform normal operation over the entire input voltage region 410.

As described above, the level shifter according to the present invention can prevent the malfunction due to the current non-matching phenomenon without increasing the area.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, these terms are only used for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the level shifter according to the present invention can output a voltage of a high voltage level by using a low level input voltage by adjusting a bias voltage value, and has an advantage of reducing its magnitude.

Claims (8)

In the level shifter, A bias unit connected at one end to a direction in which a high power supply voltage is applied and operating in response to a bias voltage; And A voltage converter configured to be connected in series with the other end of the bias part and to convert a voltage level of the input voltage to output a high level output voltage by receiving a low level input voltage; The bias voltage is And the current flowing through the bias unit is adjusted to have the same value as the current flowing through the voltage converting unit. The method of claim 1, wherein the voltage converter A level shifter, one end of which is connected to the other end of the bias unit, and the other end of which is connected to a low power supply voltage. The method of claim 2, wherein the bias portion A first bias transistor having one end connected to the high power supply voltage and receiving the bias voltage through a gate; And And a second bias transistor having one end connected to the high power supply voltage and receiving the bias voltage through a gate. The method of claim 3, wherein the voltage conversion unit A first P-type MOS transistor having one end connected to the other end of the first bias transistor; A second P-type MOS transistor having one end connected to the other end of the second bias transistor; A first N-type MOS, one end of which is connected to the other end of the first P-type MOS transistor and the gate of the first P-type MOS transistor, and the other end of which is connected to the low power supply voltage, and receives the input voltage through a gate. transistor; And A second end of which is connected to the other end of the second P-type MOS transistor and the gate of the second P-type MOS transistor, the other end of which is connected to the low power supply voltage, and a gate to which an inversion signal of the input voltage is applied to the gate A level shifter comprising an N-type MOS transistor. The method of claim 4, wherein in the level shifter, The output voltage is output from one end of the first N-type MOS transistor, And the inverted signal of the output voltage is output from one end of the second N-type MOS transistor. The method of claim 3, wherein the first and second bias transistors A level shifter, characterized by a P-type MOS transistor. The method of claim 2, The input voltage is Has a value of 0V to 3.6V, Output voltage And a level shifter having the same value as the high power supply voltage. The method of claim 7, wherein the bias voltage is And a value smaller than the high power supply voltage value.

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