KR100849077B1 - Method of manufacturing system on chip device - Google Patents

Abstract

The present invention relates to a method for manufacturing a system-on-chip device capable of increasing a capacitor area in a system-on-chip device to which a capacitor of a flat panel type is applied. Providing a semiconductor substrate defined and provided with an isolation layer; Depositing an oxide film on an entire surface of the substrate provided with the device isolation film; Selectively wet etching the oxide film to form an oxide pattern that exposes the capacitor formation region and covers the transistor formation region; Growing a hemispherical particle silicon film on the exposed portion of the substrate; Forming a nitride film pattern so as to remain on the hemispherical particle silicon film; Sequentially forming a gate oxide film and a polycrystalline silicon film on the resultant product; Etching the polycrystalline silicon film to form a gate electrode in the transistor formation region and simultaneously forming a polycrystalline silicon pattern in the capacitor formation region; Forming an LED area on the substrate under both sides of the gate electrode; Forming an insulating sidewall on a side of the gate electrode and the electrode and the polycrystalline silicon pattern; and forming a source / drain on a substrate on both sides of the gate electrode including the insulating sidewall to form a transistor and a flat plate capacitor.

Description

Method for Manufacturing System-on-Chip Devices {METHOD OF MANUFACTURING SYSTEM ON CHIP DEVICE}

1A to 1G are cross-sectional views illustrating a method of manufacturing a system on chip device according to the related art.

2A to 2I are cross-sectional views illustrating a method of manufacturing a system on chip device according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100. Semiconductor substrate 101. Trench

102, 103, 103a. Pad Oxides 104, 105, 132. Silicon Nitride

120. Device isolation film 130. Hemispherical particle silicon film

134. Gate oxide film 136. Polycrystalline silicon film

136a. Gate electrode 136b. Polycrystalline silicon pattern

140. LED area 142. Insulated sidewall

144. Source / drain regions 160, 162. Ion implantation process

C. Transistor D. Capacitor

III. Capacitor Formation Area Ⅳ. Transistor Formation Area

150, 152, 154, 156. Photoresist pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a system on chip device employing a plate type capacitor, and more particularly, to manufacturing a system on chip device capable of increasing a capacitor area. It is about a method.

System on chip (SoC) is a device that implements memory and logic, such as DRAM (DRAM) on a single chip, the interest is increasing recently. In particular, these system-on-chip devices have the disadvantages of increased chip size, complex manufacturing processes, and high manufacturing costs associated with the implementation of memory and logic on a single chip, but nevertheless memory and logic on a single chip. Its use is increasing gradually because it has the advantage of enabling high speed and low power operation compared to existing chips.

The system on chip device may be implemented by a method of applying a logic process based on a DRAM process and a method of applying a DRAM process based on a logic process. However, all of the above methods adversely affect the performance of the logic because the thermal budget due to the capacitor process of the DRAM is considerably larger than that of the logic process, and is also adopted in the logic process of 0.25 μm or less. Titanium or cobalt-silicide is agglomerated due to the thermal budget, causing junction leakage and increased resistance of the gate electrode.

Accordingly, in order to solve the above problem, a system-on-chip device is manufactured in the same manner as a logic process by applying a flat plate capacitor, which has been conventionally applied at 1 M DRAM or less, to a DRAM capacitor.

1A to 1D are cross-sectional views illustrating a method of manufacturing a system on chip device according to the related art.

In the method of manufacturing a system-on-chip device according to the related art, as illustrated in FIG. 1A, a pad oxide film 12 and a silicon nitride film 14 are sequentially deposited on a semiconductor substrate 1, and then the silicon nitride film ( A photoresist is applied on the surface 14 and exposed and developed to form a first photoresist pattern 50 that exposes an isolation region (not shown) of the device. At this time, the capacitor formation region I and the transistor formation region II are defined in the semiconductor substrate 10. The pad oxide film 12 is formed to have a thickness of 50 to 150 kPa.

Next, as shown in FIG. 1B, the trench 11 is formed by etching the silicon nitride film, the pad oxide oxide film, and the substrate to a predetermined depth using the first photoresist film pattern 50 as a mask. In this case, reference numeral 13 denotes a pad oxide film remaining after the etching process, and reference numeral 15 denotes a remaining silicon nitride film.

Then, after removing the first photoresist pattern, as shown in FIG. 1C, an oxide film (not shown) is deposited on the entire surface of the resultant substrate by HDP (High Density Plasma). Chemical Mechnical Polishing) to form the device isolation film 20.                         

Thereafter, as shown in FIG. 1D, the remaining silicon nitride film and the pad oxide film are removed by a wet method using a hydrofluoric acid solution and a phosphoric acid solution to expose a substrate.

Subsequently, as shown in FIG. 1E, a gate oxide film 22 and a polycrystalline silicon film 24 are sequentially deposited on the exposed substrate, and then a capacitor formation region I is formed on the polycrystalline silicon film 24. And a second photoresist pattern 52 covering the gate formation region (not shown) of the transistor formation region II.

Next, as shown in FIG. 1F, a gate electrode 24a is formed in the transistor formation region II by etching the polycrystalline silicon film using the second photoresist film pattern 52 as a mask. In this case, the polycrystalline silicon layer 24 remains on the capacitor formation region I during the etching process of the gate electrode 24a to form a polycrystalline silicon pattern 24b. Thus, the remaining polycrystalline silicon pattern 24b and the gate oxide layer are manufactured. In the completed system-on-chip device, it functions as a dielectric film and an electrode film, respectively, to form a flat plate capacitor (see A of FIG. 1G).

Subsequently, the second photoresist layer pattern is removed, and the P ^- ion implantation process 60 for the lightly doped drain is performed using the gate electrode 24a and the polycrystalline silicon pattern 24b as a mask to form the gate electrode ( 24a) The LED areas 28 are formed on both lower substrates.

Thereafter, as shown in FIG. 1G, a silicon oxide film (not shown) and a silicon nitride film (not shown) are formed on the entire surface of the substrate including the gate electrode 24a and the polycrystalline silicon pattern 24b by a high temperature low pressure deposition (HLD) method. ) Is sequentially deposited to form an insulating layer having a stacked structure, and then the insulating sidewall is etched back to insulate the insulating sidewall remaining between the side of the gate electrode 24a and the polycrystalline silicon pattern 24b adjacent to the electrode. 30). Subsequently, the gate electrode 24a including the insulating sidewall 30 is used as a blanket mask, and a source / drain P ⁺ ion implantation process 62 is performed on the substrate to provide a substrate under the gate electrode including the insulating sidewall 30. By forming the source / drain regions 32, the transistors B and the plate capacitors A are formed in the transistor forming region II and the capacitor forming region I of the substrate 10, respectively.

Subsequently, although not shown in the drawings, a series of subsequent processes including a wiring process are performed to complete a system on chip device in which DRAM and logic are mixed.

However, in the conventional method of manufacturing a system-on-chip device, the capacitance of the capacitor is much lower than that of the stacking method, and the chip size must be increased to compensate for this, but the actual chip size is limited, so that the capacitor of the DRAM is used. There is a limit to capacity increase.

Accordingly, an object of the present invention is to provide a method for manufacturing a system on chip device capable of increasing the capacitor area of a DRAM without increasing the chip size.

In order to achieve the above object, a method for manufacturing a system on a chip device of the present invention comprises the steps of providing a semiconductor substrate having a transistor isolation region and a capacitor formation region, the device isolation film; Depositing an oxide film on an entire surface of the substrate provided with the device isolation film; Selectively wet etching the oxide film to form an oxide pattern that exposes the capacitor formation region and covers the transistor formation region; Growing a hemispherical particle silicon film on the exposed portion of the substrate; Forming a nitride film pattern so as to remain on the hemispherical particle silicon film; Sequentially forming a gate oxide film and a polycrystalline silicon film on the resultant product; Etching the polycrystalline silicon film to form a gate electrode in the transistor formation region and simultaneously forming a polycrystalline silicon pattern in the capacitor formation region; Forming an LED area on the substrate under both sides of the gate electrode; Forming insulating sidewalls on a gate electrode and side surfaces of the electrode and the polycrystalline silicon pattern; And forming a source / drain on the substrates on both sides of the gate electrode including the insulating sidewalls to form transistors and flat plate capacitors.

The oxide film is preferably formed to a thickness of 300 kPa or more. In addition, the wet etching process uses BOE and hydrofluoric acid as an etchant.

On the other hand, the nitride film pattern is preferably formed so as to remain on the hemispherical particle silicon film by wet etching the nitride film after depositing the nitride film on the entire substrate including the hemispherical particle silicon film. In this case, the wet etching process uses a phosphoric acid solution as an etching solution.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2I are cross-sectional views illustrating a method of manufacturing a system on chip device according to an exemplary embodiment of the present invention.

In the method for manufacturing a system-on-chip device according to an embodiment of the present invention, as shown in FIG. 2A, first, a pad oxide layer 102 serving as a buffer for stress relaxation on the semiconductor substrate 100 and suppressing oxidation The silicon nitride film 104 is deposited in sequence. In this case, the semiconductor substrate 100 has a capacitor formation region III and a transistor formation region IV defined therein. In addition, the pad oxide film 102 is formed to a thickness of 3000 kPa or more thicker than the conventional one, since the formation position of the hemispherical particle silicon film to be formed in the capacitor formation region III is to be limited in a subsequent step.

Subsequently, a photoresist layer is coated on the silicon nitride layer 104, and the photoresist layer is exposed and developed to form a first photoresist layer pattern 150 exposing an isolation region (not shown) of the device.

Next, as shown in FIG. 2B, the trench 101 is formed by etching the silicon nitride layer, the pad oxide layer, and the substrate to a predetermined depth using the first photoresist layer pattern 150 as a mask. In this case, reference numeral 103 denotes a pad oxide film remaining on the substrate after the etching process for forming the trench, and reference numeral 104 denotes a silicon nitride film remaining.

Thereafter, as shown in FIG. 2C, after the first photosensitive film pattern is removed, the device isolation film 120 for filling the trench 101 is formed by a known technique. Subsequently, the silicon oxide film is removed by a wet method using phosphoric acid and hydrofluoric acid to expose the pad oxide film 103.

Next, as illustrated in FIG. 2D, a second photoresist layer pattern 152 is formed on the entire surface of the substrate including the pad oxide layer 103 to expose the transistor formation region IV and expose the capacitor formation region III. Thereafter, the pad photoresist is etched using the second photoresist pattern 152 as a mask to expose the capacitor formation region III of the substrate. In this case, the pad oxide layer etching process is performed by a wet etching method to minimize damage to the surface of the substrate, and BOE and hydrofluoric acid are used as an etching solution. In addition, reference numeral 103a denotes a pad oxide film remaining on the substrate after the etching process.

Subsequently, after the second photoresist layer pattern is removed, a silicon film 130 having hemispherical particles is formed in the capacitor formation region III of the exposed substrate. In this case, the hemispherical particles of the silicon film 130 are not formed in the pad oxide film 103a of the transistor formation region IV and are formed only on the silicon Si, which is the capacitor formation region III of the exposed substrate.

Then, as shown in FIG. 2F, after the silicon nitride film 132 is deposited on the entire surface of the resultant substrate, the capacitor forming area III is covered on the silicon nitride film 132 and the transistor forming area IV is covered. A third photoresist pattern 154 is formed to be exposed.

Thereafter, the silicon nitride film is etched using the third photoresist pattern 154 as a mask to form a silicon nitride film pattern 133 remaining on the silicon film 130 as shown in FIG. 2G. In this case, the silicon nitride film etching process uses a wet etching method, a phosphoric acid solution as an etching solution.                     

Subsequently, the third photoresist pattern is removed, and the gate oxide film 134 and the polycrystalline silicon film 136 are sequentially formed on the entire surface of the substrate including the silicon nitride film pattern 133.

Subsequently, a fourth photoresist pattern 156 is formed on the polycrystalline silicon film 136 to cover the capacitor formation region III and the gate region (not shown) of the transistor formation region IV.

Next, as shown in FIG. 2H, a gate electrode 136a is formed in the transistor formation region IV by etching the fourth photoresist pattern as a mask and etching a polycrystalline silicon film. At this time, during the etching process of the gate electrode 136a, the polycrystalline silicon film remains on the capacitor formation region (III) of the substrate to form a polycrystalline silicon pattern 136b. The remaining polycrystalline silicon pattern 136b and the lower portion thereof The gate oxide film 134, the silicon nitride film pattern 133 and the silicon film 130 function as an electrode film and a dielectric film in the fabricated system on chip device, respectively, to form a flat plate capacitor (see D in FIG. 2I). . As can be seen from the above, in the present invention, the capacitor is formed by adopting an oxide-nitride-oxide (ONO) structure of the silicon nitride film pattern 133, the hemispherical particle silicon film 130, and the gate oxide film 134 as the dielectric film. Can increase the capacitance.

Subsequently, the LED region 140 is formed on the lower substrate on both sides of the gate electrode 136a by performing the P ^- ion implantation process 160 for the LEDs using the gate electrode 136a and the polycrystalline silicon pattern 136b as a mask. Form.

Thereafter, as illustrated in FIG. 2I, an insulating film (not shown) and a silicon nitride film (not shown) are sequentially deposited on the substrate including the gate electrode 136a and the polycrystalline silicon pattern 136b in a HLD manner to double stack the layers. After forming the insulating film of the structure, the insulating film is etched back to form an insulating insulating sidewall 142 for the gate electrode 136a and the side of the polycrystalline silicon pattern 136b adjacent to the electrode. Subsequently, a source / drain P ⁺ ion implantation process 162 is performed on the substrate using the gate electrode 136a including the insulating sidewall 142 as a mask, so that a source / drain region may be formed on the substrate under the insulating sidewall 142. By forming the 144, the transistor C and the plate capacitor D are formed in the substrate 100.

Subsequently, although not shown in the drawings, a series of subsequent processes including a wiring process are performed to complete the system on chip device.

According to the method of the present invention, by adopting the ONO structure of the hemispherical particle silicon film, the silicon nitride film pattern and the gate oxide film as the dielectric film, the capacitance of the capacitor is increased by four times or more than the conventional one using a single insulating film (SiO ₂ ). You can. Therefore, in the present invention, the capacitance of the capacitor can be increased without increasing the chip size.

As described above, in the present invention, by adopting the ONO structure of the silicon nitride film pattern, the hemispherical particle silicon film, and the gate oxide film as the dielectric film, the capacitance of the capacitor is four times higher than that of using a single insulating film (SiO ₂ ) as the dielectric film. It can increase the number of chips that can be produced per wafer more than four times, lowering production costs.

Therefore, the present invention can increase the capacitance of the capacitor without increasing the chip size, so that a system-on-chip device having a highly integrated DRAM can be easily implemented.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (6)

Providing a semiconductor substrate having a transistor formation region and a capacitor formation region defined therein, and including an isolation layer; Depositing an oxide film on an entire surface of the substrate provided with the device isolation film; Selectively wet etching the oxide film to form an oxide pattern that exposes the capacitor formation region and covers the transistor formation region; Growing a hemispherical particle silicon film on the exposed portion of the substrate; Forming a nitride film pattern to remain on the hemispherical particle silicon film; Sequentially forming a gate oxide film and a polycrystalline silicon film on the resultant product; Etching the polycrystalline silicon film to form a gate electrode in the transistor formation region and simultaneously forming a polycrystalline silicon pattern in the capacitor formation region; Forming an LED region on substrates below both sides of the gate electrode; Forming insulating sidewalls on the gate electrode and on the side of the gate electrode and the polycrystalline silicon pattern; And And forming a source / drain on the substrates on both sides of the gate electrode including the insulating sidewalls to form transistors and flat plate capacitors. delete The method of claim 1, wherein the wet etching process uses BOE and hydrofluoric acid as an etching solution. The method of claim 1, wherein the oxide film is formed to a thickness of 300 GPa or more. The system on chip device according to claim 1, wherein the nitride film pattern is formed by wet etching the nitride film so as to remain on the hemispherical particle silicon film after depositing a nitride film over the entire surface of the substrate including the hemispherical particle silicon film. Manufacturing method. The method of claim 5, wherein the wet etching process uses a phosphoric acid solution as an etching solution.

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