KR100848104B1 - Thin film transistor array substrate and its manufacturing method - Google Patents

Abstract

First, a conductive material is stacked and patterned on an upper portion of a substrate to form a horizontal gate wiring including a gate line, a gate electrode, and a gate pad on the substrate. Next, a gate insulating film is formed by laminating silicon nitride, and an amorphous silicon layer and an ohmic contact layer of doped amorphous silicon are laminated thereon, and then the semiconductor layer and the ohmic contact layer are patterned. Subsequently, the conductive material is stacked and patterned to form a data line including a data line, a source electrode, a drain electrode, and a data pad crossing the gate line. Subsequently, the resistive contact layer, which is not covered by the data wiring, is etched to expose the semiconductor layer. Then, the semiconductor layer exposed by laser irradiation is crystallized with polycrystalline silicon, and metal conduction and crystallization are performed through heat treatment to form an amorphous layer under the data wiring. Silicon is crystallized into polycrystalline silicon. Subsequently, silicon nitride or an organic material is stacked to form a protective film and patterned by dry etching to form contact holes that expose the drain electrode, the gate pad, and the data pad, respectively. Subsequently, the transparent conductive material or the reflective conductive material is stacked and patterned to form a pixel electrode, an auxiliary gate pad, and an auxiliary data pad electrically connected to the drain electrode, the gate pad, and the data pad, respectively.

Amorphous Silicon, Polycrystalline Silicon, Thin Film Transistor, MIC

Description

A thin film transistor array substrate and a method of manufacturing the same {A THIN FILM TRANSISTOR ARRAY SUBSTRATE INCLUDING THE WIRING, AND A METHOD FOR MANUFACTURING THE SUBSTRATE}

1 is a layout view of a thin film transistor array substrate for a liquid crystal display according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II ',

3A, 5A, 6A, and 7A are layout views of a thin film transistor substrate illustrating an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, in the order of the steps thereof;

3B is a cross-sectional view taken along the line IIIb-IIIb ′ in FIG. 3A;

4B is a cross-sectional view taken along the line IVb-IVb ′ in FIG. 4A and is a cross-sectional view showing the next step in FIG. 3B;

FIG. 5B is a cross-sectional view taken along the line Vb-Vb ′ in FIG. 5A and illustrating the next step of FIG. 4;

FIG. 6 is a cross-sectional view taken along the line Vb-Vb 'of FIG. 5A and illustrating the next step of FIG. 5B;                 

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ of FIG. 7A and illustrating the next step of FIG. 6;

8 is a layout view of a thin film transistor array substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

9 and 10 are cross-sectional views of the thin film transistor substrate illustrated in FIG. 8 taken along lines IX-IX 'and X-X',

11A is a layout view of a thin film transistor array substrate at a first stage of manufacture in accordance with a second embodiment of the present invention;

11B and 11C are cross-sectional views taken along the lines XIb-XIb 'and XIc-XIc' of FIG. 11A, respectively.

12A and 12B are cross-sectional views taken along the lines XIb-XIb 'and XIc-XIc' of FIG. 11A, respectively, and are cross-sectional views of the next steps of FIGS. 11B and 11C;

FIG. 13A is a layout view of a thin film transistor array substrate in FIGS. 12A and 12B next steps; FIG.

13B and 13C are cross-sectional views taken along the lines XIIIb-XIIIb 'and XIIIc-XIIIc' of FIG. 13A, respectively.

14A, 15A, 16A and 14B, 15B, 16B are cross-sectional views taken along the lines XIIIb-XIIIb 'and XIIIc-XIIIc' in FIG. 13A, respectively, illustrating the following steps in the order of the process. ,

17A and 17B are cross-sectional views taken along the lines XIIIb-XIIIb 'and XIIIc-XIIIc' in FIG. 13A, which illustrate the following steps in the order of a process, FIGS. 16A and 16B;

FIG. 18A is a layout view of a thin film transistor array substrate in the next step of FIGS. 17A and 17B;

18B and 18C are cross-sectional views taken along the lines XVIIIb-XVIIIb 'and XVIIIc-XVIIIc', respectively, in FIG. 18A.

The present invention relates to a thin film transistor array substrate and a method of manufacturing the same, and more particularly, to a thin film transistor array substrate using a polycrystalline silicon as a semiconductor layer and a method of manufacturing the same.

As one of the flat panel display devices which are widely used at present, a liquid crystal display device has two substrates on which a plurality of electrodes for generating an electric field are formed, a liquid crystal layer injected between the two substrates, and is attached to the outer surface of each substrate to emit light. 2. A display device including two polarizing plates for polarizing and controlling the amount of light transmitted by rearranging liquid crystal molecules of a liquid crystal layer by applying a voltage to an electrode. This is because the arrangement of molecules changes when a voltage is applied among various properties of the liquid crystal. In a liquid crystal display device using light transmission or reflection, the liquid crystal does not emit light and thus requires a light source on its own or externally.                         

In this case, a thin firm transistor array panel is used as a circuit board for driving each pixel independently in a liquid crystal display. The thin film transistor array substrate includes a scan signal wiring or a gate wiring for transmitting a scan signal and an image signal line or data wiring for transmitting an image signal, and a thin film transistor and a thin film transistor connected to the gate wiring and the data wiring. It includes a pixel electrode connected to and used to display an image.

In this case, the thin film transistor has a semiconductor layer made of amorphous silicon or polycrystalline silicon, and may be divided into a top gate method and a bottom gate method according to a relative position of the gate electrode and the semiconductor layer. In this case, in the case of the amorphous silicon thin film transistor substrate, a bottom gate method in which the gate electrode is positioned below the semiconductor layer is mainly used, and in the case of the polysilicon thin film transistor substrate, the gate electrode is the semiconductor around the gate insulating film. The top gate method located above the layer is mainly used, and both of them are formed at the interface between the semiconductor layer and the gate insulating film.

However, in the method of manufacturing a polycrystalline silicon thin film transistor capable of securing high electron mobility in a top gate method, the semiconductor layer is crystallized into a polycrystalline silicon layer and then a gate insulating film is laminated thereon, whereby the channel portion of the semiconductor layer is Occurs when exposed to the outside it is difficult to uniformly secure the characteristics of the thin film transistor.

On the other hand, among the manufacturing method of the liquid crystal display device, the substrate on which the thin film transistor is formed is generally manufactured through a photolithography process using a mask. At this time, it is preferable to reduce the number of masks in order to reduce the production cost.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a polycrystalline silicon thin film transistor array substrate capable of uniformly securing characteristics of a thin film transistor and a method of manufacturing the same.

In addition, another object of the present invention is to simplify the manufacturing method of the thin film transistor array substrate.

In order to solve this problem, in the present invention, the gate insulating film and the amorphous silicon layer are sequentially stacked, and the source and drain electrodes are formed of a metal for metal induced crystallization (MIC), and then a metal induction process through laser irradiation and annealing. Through the crystallization of the amorphous silicon layer into a polycrystalline silicon layer.

More specifically, in the thin film transistor array substrate and the method of manufacturing the same, a conductive material is stacked and patterned on the substrate to form a gate wiring including a gate line and a gate electrode. Subsequently, a gate insulating film covering the gate wiring is stacked, and then a resistive contact layer of the doped amorphous silicon and the semiconductor layer of the amorphous silicon layer is formed. A data layer including a data line, a source electrode, and a drain electrode is formed by stacking and patterning a conductive layer of a conductive material for metal induction crystallization on the gate insulating layer or the semiconductor layer, and then irradiating a laser to irradiate a semiconductor layer not covered by the data line. Crystallization is made of polycrystalline silicon, and a metal induction crystallization process is performed to crystallize the semiconductor layer and the ohmic contact layer under the data wirings with polycrystalline silicon.

In this case, the method may further include forming a pixel electrode connected to the data line, and may further include forming a passivation layer between the data line and the pixel electrode.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Now, a thin film transistor array substrate for a liquid crystal display according to an exemplary embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings.

First, a structure of a thin film transistor array substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II ′.

On the insulating substrate 110, a gate wiring made of a single film having a low resistance, such as silver or a silver alloy, aluminum or an aluminum alloy, or a multilayer film including the same is formed. The gate wire is connected to the gate line 121 and the gate line 121 extending in the horizontal direction and connected to the gate pad 125 and the gate line 121 which receive a gate signal from the outside and transfer the gate signal to the gate line. A gate electrode 123 of the thin film transistor. Here, when the gate wirings 121. 125. 123 are a multilayer film, the gate material 121. 125.

On the substrate 110, a gate insulating layer 140 made of silicon nitride (SiN _x ) covers the gate lines 121, 125, and 123.

A semiconductor layer 150 made of a polysilicon semiconductor is formed on the gate insulating layer 140 of the gate electrode 125, and n + hydrogenation in which silicide or n-type impurities are heavily doped is formed on the semiconductor layer 150. Resistive contact layers 163 and 165 made of a material such as amorphous silicon are formed, respectively.

The conductive contact layers 163 and 165 and the gate insulating layer 140 include a conductive film made of a metal for metal induced crystallization (MIC) such as chromium or aluminum or an aluminum alloy or molybdenum or molybdenum alloy or nickel or palladium. The data wiring is formed. The data line is formed in the vertical direction and crosses the gate line 121 to define a pixel, which is a branch of the data line 171 and the data line 171 and extends to the upper portion of the ohmic contact layer 163. ), Which is connected to one end of the data line 171 and is separated from the data pad 179 and the source electrode 173 for receiving an image signal from the outside, and is opposite to the source electrode 173 with respect to the gate electrode 123. The drain electrode 175 is formed on the ohmic contact layer 165. In addition, the data line may include an organic capacitor conductor pattern 177 overlapping the gate line 121 to improve the storage capacitance. In the case where the data lines 171, 173, 175, 177, and 179 are multilayer films, the conductive film of the metal for MIC is preferably in contact with the lower semiconductor layer 150 or the ohmic contact layers 163 and 165. This is to crystallize the lower semiconductor layer 150 or the ohmic contact layers 163 and 165 with polycrystalline silicon.

A passivation layer 180 made of silicon oxide, silicon nitride, or an organic material is formed on the data lines 171, 173, 175, 177, and 179 and the semiconductor layer 150 that is not covered.

In the passivation layer 180, contact holes 185, 187, and 189 are formed to expose the drain electrode 175, the conductive pattern 177 for the organic capacitor, and the data pad 179, respectively, and together with the gate insulating layer 140. A contact hole 182 is formed to expose the gate pad 125.

A pixel electrode 190 is formed on the passivation layer 180 and is electrically connected to the conductive pattern 177 for the storage capacitor and the drain electrode 175 through the contact holes 185 and 187. In addition, an auxiliary gate pad 92 and an auxiliary data pad 97 connected to the gate pad 125 and the data pad 179 are formed on the interlayer insulating layer 180 through the contact holes 182 and 189, respectively. . The pixel electrode 190, the auxiliary gates, and the data pads 92 and 97 are made of indium tin oxide (ITO) or indium zinc oxide (IZO), which are transparent conductive materials. However, in the case of a reflective liquid crystal display device, the pixel electrode 190 may be made of a conductive material having reflectivity, such as silver, a silver alloy, aluminum, or an aluminum alloy. In the semi-transmissive case, the pixel electrode may have a conductivity. It may be made of a reflective film of a material and a transparent electrode of a transparent conductive material. In the reflective or semi-transmissive type, the surface of the passivation layer 180 may have a concave-convex pattern in order to induce a concave-convex pattern to the pixel electrode to maximize the reflectance of the reflecting electrode.

Here, the conductive capacitor pattern 177 connected to the pixel electrode 190 overlaps the gate line 121 to form a storage capacitor, and when the storage capacitor is insufficient, the same layer as the gate lines 121, 125, and 123. It is also possible to add a storage capacitor wiring.

Next, a method of manufacturing the thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 and FIGS. 3A to 7B.

First, as shown in FIGS. 3A and 3B, a single film made of silver or a silver alloy or aluminum or an aluminum alloy having a low resistance on the insulating substrate 110 or a single film including such a chromium, molybdenum, molybdenum alloy, Stacking and patterning a multilayer film including a conductive material having excellent contact properties with other materials such as titanium or tantalum to form a horizontal gate wiring including the gate line 121, the gate electrode 123, and the gate pad 125. do.

Next, as shown in FIGS. 4A and 4B, a three-layer film of a gate insulating layer 140 made of silicon nitride, a semiconductor layer 150 made of amorphous silicon, and a doped amorphous silicon layer 160 is sequentially stacked, and a mask is formed. The semiconductor layer 150 and the ohmic contact layer 160 are formed on the gate insulating layer 140 facing the gate electrode 123 by patterning the semiconductor layer 150 and the doped amorphous silicon layer 160 by the photolithography process. Form. In this case, the semiconductor layer 150 may be formed along the data line 171 formed later.

In this case, when the doped amorphous silicon layer 160 is located in the p-type thin film transistor region, only the amorphous silicon layer 160 doped with the p-type impurity is left in the n-type thin film transistor region by a photolithography process using a photoresist pattern. When positioned at, the only amorphous silicon layer 160 into which n-type impurities are injected is left in a photolithography process using another photoresist film. The order of forming the n-type and p-type thin film transistor regions may be changed.

Next, as shown in FIGS. 5A to 5B, a metal for metal induced crystallization (MIC) such as chromium or aluminum or an aluminum alloy or molybdenum or molybdenum alloy or nickel or palladium may be formed on the substrate 110. After the stacked conductive films are stacked, a patterning process using a mask is performed, and a source electrode connected to the data line 171 and the data line 171 crossing the gate line 121 and extending to the upper portion of the gate electrode 123 ( 173 and the data line 171 are separated from the data pad 179 and the source electrode 173 connected to one end thereof, and the drain electrode 175 facing the source electrode 173 around the gate electrode 123. And a data wiring including a conductive capacitor conductor pattern 177 overlapping with the gate line 121.

Next, the doped amorphous silicon layer pattern 160, which is not covered by the data wires 171, 173, 175, 177, and 170, is etched and separated from both sides around the gate electrode 123, while the doped amorphous silicon on both sides is etched. The semiconductor layer pattern 150 between the layers 163 and 165 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 150, it is preferable to perform oxygen plasma.

Subsequently, as shown in FIG. 5B, the laser is irradiated from the upper portion of the substrate 110 to crystallize the amorphous silicon of the semiconductor layer 150 that is not covered by the data lines 171, 173, 175, 177, and 170 with polycrystalline silicon. .

Next, as shown in FIG. 6, an ohmic contact layer of the amorphous silicon layer in contact with the data lines 171, 173, 175, 177, and 170 is subjected to an annealing in a heat treatment process to perform a metal induction crystallization process. (163, 165) and the lower semiconductor layer 150 are crystallized from polycrystalline silicon.

Subsequently, as shown in FIGS. 7A and 7B, an insulating material such as silicon nitride, silicon oxide, or an organic material having a low dielectric constant is stacked to form the passivation layer 180. Subsequently, the gate pad 125, the drain electrode 175, the conductive capacitor pattern 177 and the data pad 179 are patterned by dry etching together with the gate insulating layer 140 in a photolithography process using a photoresist pattern. Contact holes 183, 185, 187, and 189 to reveal the contact holes.

Next, as shown in FIGS. 1 and 2, the ITO or IZO film is laminated and patterned using a mask to conduct the drain electrode 175 and the conductor pattern 175 for the storage capacitor through the contact holes 185 and 187. ) And an auxiliary gate pad 92 and an auxiliary data pad 97 respectively connected to the gate pad 125 and the data pad 179 through the pixel electrode 190 and the contact holes 182 and 189, respectively. do.

In the method of manufacturing a thin film transistor array substrate according to the first exemplary embodiment of the present invention, an interface between the gate insulating layer 140 and the semiconductor layer 150 is formed by stacking the gate insulating layer 140 and then sequentially stacking the semiconductor layer 150. Since the channel portion of the thin film transistor formed in the is not exposed to the external environment during the manufacturing process, it is possible to uniformly secure the channel portion characteristics of the thin film transistor. In addition, by forming a thin film transistor having a bottom gate structure made of polycrystalline silicon, the characteristics of the bottom gate thin film transistor can be improved.

As described above, although the embodiment of the present invention has been applied to the manufacturing method of forming the semiconductor layer and the data wiring by a photolithography process using different masks, the semiconductor layer and the data wiring are minimized in order to minimize the manufacturing cost. The same applies to the method of manufacturing a thin film transistor substrate for a liquid crystal display device, which is formed by a photolithography process using one photosensitive film pattern. This will be described in detail with reference to the drawings.

First, the unit pixel structure of the thin film transistor substrate for a liquid crystal display according to the second exemplary embodiment of the present invention will be described in detail with reference to FIGS. 8 to 10.

8 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 9 and 10 are along the IX-IX 'and XX' lines of the thin film transistor substrate shown in FIG. It is sectional drawing cut out.

First, a gate line 121 including a conductive film made of a low resistance conductive material, a gate pad 125, and a gate electrode 123 are formed on the insulating substrate 110. The gate wiring includes a storage electrode 131 that is parallel to the gate line 121 on the substrate 110 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. The storage electrode 131 overlaps with the conductive capacitor conductor 177 connected to the pixel electrode 190 to be described later to form a storage capacitor to improve charge retention of the pixel, and the pixel electrode 190 and the gate line to be described later. If the holding capacity generated by the overlap of 121 is sufficient, it may not be formed.

A gate insulating layer 140 made of silicon nitride (SiN _x ) is formed on the gate lines 121, 125, 123, and 28 to cover the gate lines 121, 125, 123, and 28.

Semiconductor patterns 152 and 157 made of polycrystalline silicon are formed on the gate insulating layer 140, and amorphous silicon doped at high concentration with n-type or p-type impurities such as phosphorus (P) on the semiconductor patterns 152 and 157. An ohmic contact layer pattern or an intermediate layer pattern 163, 165, 167 is formed.

On the ohmic contact layer patterns 163, 165, and 167, as in the first embodiment, a data line including a conductive film made of a conductive material for metal induction crystallization is formed. The data line is a thin film transistor which is a branch of the data line 171 formed in the vertical direction, the data pad 179 connected to one end of the data line 171 to receive an image signal from the outside, and the data line 171. And a data line portion of the source electrode 173 of the source electrode 173, and separated from the data line portions 171, 179, and 173 of the source electrode 173 with respect to the gate electrode 123 or the channel portion C of the thin film transistor. Also included is a conductive capacitor pattern 177 for the storage capacitor located on the drain electrode 175 and the storage electrode 131 of the thin film transistor positioned on the opposite side. When the storage electrode 131 is not formed, the conductor pattern 177 for the storage capacitor is also not formed.

The contact layer patterns 163, 165, and 167 lower the contact resistance between the semiconductor patterns 152 and 157 below and the data lines 171, 173, 175, 177, and 179 above the data layer. (171, 173, 175, 177, 179) is exactly the same form. That is, the data line part intermediate layer pattern 163 is the same as the data line parts 171, 179 and 173, the drain electrode intermediate layer pattern 163 is the same as the drain electrode 173, and the storage capacitor intermediate layer pattern 167 is It is the same as the conductor pattern 177 for holding capacitors.

The semiconductor patterns 15 and 157 have the same shape as the data wires 171, 173, 175, 177 and 179 and the ohmic contact layer patterns 163, 165 and 167 except for the channel portion C of the thin film transistor. Doing Specifically, the semiconductor capacitor pattern 157 for the storage capacitor, the conductor pattern 177 for the storage capacitor, and the contact layer pattern 167 for the storage capacitor have the same shape, but the semiconductor pattern 152 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 171, 179, and 173, in particular, the source electrode 173 and the drain electrode 175 are separated, and the data layer intermediate layer 163 and the contact layer pattern for the drain electrode. Although 165 is also separated, the semiconductor pattern 152 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

A passivation layer 180 made of silicon nitride, silicon oxide, or an organic material having a low dielectric constant is formed on the data lines 171, 173, 175, 177, and 179 and the semiconductor layer 152 not covered by the data lines.

The passivation layer 180 has contact holes 185, 189, and 187 exposing the drain electrode 175, the data pad 179, and the conductive pattern 177 for the storage capacitor, and the gate together with the gate insulating layer 140. It has a contact hole 182 that exposes the pad 125.

A pixel electrode 190 is formed on the passivation layer 180 to receive an image signal from the thin film transistor and generate an electric field together with the electrode of the upper plate. The pixel electrode 190 is made of a transparent conductive material such as ITO or IZO, and is physically and electrically connected to the drain electrode 175 through the contact hole 185 to receive an image signal. The pixel electrode 190 also overlaps the neighboring gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 190 is also connected to the storage capacitor conductor pattern 177 through the contact hole 187 to transmit an image signal to the conductor pattern 177. On the other hand, an auxiliary gate pad 92 and an auxiliary data pad 97 connected to the gate pad 125 and the data pad 179 through the contact holes 182 and 189, respectively, are formed. 179) and supplementing the adhesion between the external circuit device and protecting the pad, are not essential, and their application is optional.

Next, a method of manufacturing a thin film transistor array substrate for a liquid crystal display device having the structure of FIGS. 8 to 10 will be described with reference to FIGS. 8 to 10 and FIGS. 11A to 18C.

First, as shown in FIGS. 11A to 11C, as in the first embodiment, a conductive film including a conductive material of silver or silver alloy or aluminum or aluminum alloy is laminated and patterned by a photolithography process using a mask to form a gate line 121. ), A gate wiring including the gate pad 125, the gate electrode 123, and the storage electrode 131 is formed.

Next, as shown in FIGS. 12A and 12B, the gate insulating layer 140 made of silicon nitride, the semiconductor layer 150 of undoped amorphous silicon, and the intermediate layer 160 of doped amorphous silicon are formed by chemical vapor deposition. Continuous deposition is carried out at a thickness of 1,500 kPa to 5,000 kPa, 500 kPa to 2,000 kPa, and 1400 kPa to 600 kPa, respectively. Subsequently, the conductive layer 170 of the conductive material for metal induced crystallization is deposited to have a thickness of 1,500 kPa to 3,000 kPa by sputtering or the like, and then the photosensitive film 210 is applied thereon to a thickness of 1 μm to 2 μm.

Thereafter, the photoresist film 210 is irradiated with light through a mask and then developed to form photoresist patterns 212 and 214 as shown in FIGS. 13B and 13C. At this time, the channel portion C of the photosensitive film patterns 212 and 214, that is, the first portion 214 positioned between the source electrode 173 and the drain electrode 175, is the data wiring portion A, that is, the data. The thickness of the wirings 171, 173, 175, 177, and 179 is smaller than that of the second part 212 positioned at the portion where the wirings 171, 173, 175, 177, and 179 are to be formed. At this time, the ratio of the thickness of the photoresist film 214 remaining in the channel portion C and the thickness of the photoresist film 212 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable that the thickness of the first portion 214 be 1/2 or less of the thickness of the second portion 212, for example, 4,000 kPa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure machine used for exposure, and in the case of using a translucent film, the transmittance is different in order to control the transmittance when fabricating a mask. A thin film having a thickness or a thin film may be used.

When the photosensitive film is irradiated with light through such a mask, the polymers are completely decomposed in the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small in the part where the slit pattern or the translucent film is formed. In the part covered by the light shielding film, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin photoresist 214 may be exposed to light using a photoresist film made of a reflowable material, and then exposed and exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot completely transmit light. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, etching is performed on the photoresist pattern 214 and the underlying layers, that is, the conductor layer 170, the intermediate layer 160, and the semiconductor layer 150. In this case, the data line and the layers under the data line remain in the data wiring portion A, only the semiconductor layer should remain in the channel portion C, and the three layers 170, 160, 150 is removed to expose the gate insulating layer 140.

First, as shown in FIGS. 14A and 14B, the exposed conductor layer 170 of the other portion B is removed to expose the lower intermediate layer 160. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 170 may be etched and the photoresist patterns 212 and 214 may be hardly etched. However, in the case of dry etching, since it is difficult to find a condition in which only the conductor layer 170 is etched and the photoresist patterns 212 and 214 are not etched, the photoresist patterns 212 and 214 may be etched together. In this case, the thickness of the first portion 214 is thicker than that of the wet etching so that the first portion 214 is removed in this process so that the lower conductive layer 170 is not exposed.

In this way, as shown in Figs. 14A and 14B, only the conductor layer of the channel portion C and the data wiring portion B, that is, the conductor pattern 178 for the source / drain and the conductor pattern 177 for the storage capacitor, is present. All of the conductor layer 170 of the remaining portion B is removed, revealing the underlying intermediate layer 50. The remaining conductor patterns 178 and 177 are the same as the data wires 171, 177, 173, 175 and 179 except that the source and drain electrodes 173 and 175 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 212 and 214 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 15A and 15B, the exposed intermediate layer 160 of the other portion B and the semiconductor layer 150 thereunder are simultaneously removed together with the first portion 214 of the photosensitive film by a dry etching method. do. At this time, etching is performed under the condition that the photoresist patterns 212 and 214 and the intermediate layer 160 and the semiconductor layer 150 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched and the gate insulating layer 140 is not etched. In particular, it is preferable to etch under conditions in which the etch ratios of the photoresist patterns 212 and 214 and the semiconductor layer 150 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etch ratios of the photoresist patterns 212 and 214 and the semiconductor layer 150 are the same, the thickness of the first portion 214 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 150 and the intermediate layer 160.

This removes the first portion 214 of the channel portion C, revealing the source / drain conductor pattern 178, as shown in FIGS. 15A and 15B, and the intermediate layer 160 of the other portion B. The semiconductor layer 150 is removed to expose the gate insulating layer 140 under the semiconductor layer 150. On the other hand, since the second portion 212 of the data line portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 152 and 157 are completed. Reference numerals 168 and 167 denote intermediate layer patterns under the source / drain conductor patterns 178 and intermediate layer patterns under the storage capacitor conductor patterns 177, respectively.

Subsequently, ashing of the photoresist film remaining on the surface of the source / drain conductor pattern 178 of the channel part C is removed.

Next, as illustrated in FIGS. 16A and 16B, the source / drain conductor pattern 178 of the channel part C and the source / drain interlayer pattern 168 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 178 and the intermediate layer pattern 168. The etching may be performed by wet etching with respect to the source / drain conductor pattern 178. 168) may be performed by dry etching. In the case of the former, it is preferable to perform etching under the condition that the etching selectivity of the source / drain conductor pattern 178 and the interlayer pattern 168 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 152 remaining in FIG. Examples of the etching gas used to etch the intermediate layer pattern 168 and the semiconductor pattern 152 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} may leave the semiconductor pattern 152 with a uniform thickness. In this case, as shown in FIG. 16B, a portion of the semiconductor pattern 152 may be removed to reduce the thickness, and the second portion 212 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating layer 140 is not etched, and the photosensitive layer is not exposed so that the second portion 212 is etched so that the data lines 171, 173, 175, 177, and 179 below the substrate are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 173 and the drain electrode 175 are separated to complete the data lines 171, 173, 175, 177, and 179 and the contact layer patterns 163, 165, and 167 thereunder.

Finally, the photosensitive film second portion 212 remaining in the data wiring portion A is removed. However, the removal of the second portion 212 may be performed after removing the conductor pattern 178 for the channel portion C source / drain and before removing the intermediate layer pattern 168 thereunder.

As mentioned earlier, wet and dry etching can be alternately used, or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

Next, as shown in FIGS. 17A and 17B, the channel portion C of the semiconductor layer 152, which is exposed by performing a crystallization process using a laser as in the first embodiment, is crystallized with polycrystalline silicon, and then subjected to an annealing process. The ohmic contacts 163, 165, and 167 and the semiconductor layer 152 under the data lines 171, 173, 175, 177, and 179 are crystallized with polycrystalline silicon. In this case, the channel portion C of the semiconductor layer 152 is polycrystalline silicon formed through a laser process, and the lower portions of the data lines 171, 173, 175, 177, and 179 are polycrystalline silicon formed through metal induction crystallization.

In this way, the data wirings 171, 173, 175, 177, and 179 are formed, and the semiconductor layer 152 and the ohmic contact layers 163, 165, and 167 are crystallized, and then, as shown in FIGS. 18A to 18C, An insulating material or silicon nitride is deposited to form the passivation layer 180, and the passivation layer 180 is etched together with the gate insulation layer 140 using a mask to form the drain electrode 175, the gate pad 125, and the data pad ( 179 and contact holes 185, 182, 189 and 187 exposing the conductor pattern 177 for the storage capacitor, respectively.

Finally, as shown in FIGS. 13 to 15, 400 Å to 500 Å thick IZO or ITO is deposited and etched using a mask to be connected to the drain electrode 175 and the conductor pattern 177 for the storage capacitor. An auxiliary gate pad 92 connected to the pixel electrode 190, a gate pad 125, and an auxiliary data pad 97 connected to the data pad 179 are formed.

In the second embodiment of the present invention, the data wirings 171, 173, 175, 177, and 179, the contact layer patterns 163, 165, 167, and the semiconductor patterns 152 underneath the data wirings 171, 173, 175, 177, and 179, as well as the effects of the first embodiment. , 157 may be formed using one mask, and the source electrode 173 and the drain electrode 175 may be separated in this process to simplify the manufacturing process.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, in the present invention, a thin film transistor is formed by stacking a gate insulating film, then stacking and crystallizing an amorphous silicon layer to form a semiconductor layer so that the channel portion of the semiconductor layer is exposed to the external environment during the manufacturing process. The characteristics of can be secured uniformly.

Claims (6)

Stacking and patterning a conductive material on the substrate to form a gate wiring including a gate line and a gate electrode; Stacking a gate insulating film on the substrate; Forming a semiconductor layer of an amorphous silicon layer on the gate insulating film, Forming an ohmic contact layer of doped amorphous silicon on the semiconductor layer, Stacking and patterning a conductive material for metal induction crystallization on the gate insulating layer or the semiconductor layer to form a data line including a data line, a source electrode, and a drain electrode; Irradiating a laser to crystallize the semiconductor layer, which is not covered by the data line, with polycrystalline silicon Performing a metal induction crystallization process to crystallize the semiconductor layer and the ohmic contact layer under the data line with polycrystalline silicon; Method of manufacturing a thin film transistor array substrate comprising a. delete In claim 1, And forming a pixel electrode connected to the data line. In claim 3, And forming a passivation layer between the data line and the pixel electrode. A gate wiring formed on an insulating substrate and including a gate line and a gate electrode connected to the gate line; A gate insulating film covering the gate wiring, A semiconductor layer formed on the gate insulating layer and made of polycrystalline silicon; The portion in contact with the semiconductor layer is made of a metal for metal induction crystallization, a data line, a source electrode connected to the data line and adjacent to the gate electrode, and a drain electrode opposite to the source electrode with respect to the gate electrode. Data wiring, including A protective film covering the semiconductor layer, A pixel electrode formed on the passivation layer and electrically connected to the drain electrode through a contact hole of the passivation layer; The semiconductor layer positioned between the source electrode and the drain electrode is made of polycrystalline silicon by laser irradiation, and the semiconductor layer located below the source electrode and the drain electrode is made of polycrystalline silicon formed by metal induction and crystallization. . delete

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