KR100840329B1 - Liquid crystal display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (LCD), and a signal line for transmitting a gate on or off voltage is formed on a data flexible printed circuit (FPC) A plurality of gate FPC boards on which driving ICs are respectively mounted are attached. A plurality of gate lead lines and gate drive signal lines are formed on the FPC substrate, and a gate drive signal line connected to the signal lines is formed at the left upper end and the left end edge outside the display area of the liquid crystal panel assembly. A gate on or off voltage bypass line is formed on the left edge of the liquid crystal panel assembly. One end of the bypass line is connected to a signal line for transmitting a gate on or off voltage through a contact portion. And is connected to the gate drive signal wiring between the third gate drive IC and the fourth drive IC. Therefore, when a gate on or off voltage is sequentially applied to a plurality of gate driving ICs, a gate on or off voltage is simultaneously supplied to another gate driving IC to which a gate on or off voltage is finally applied using a separate wiring , The gate on or off voltage difference between the gate driving ICs is reduced, and the variation of the gate on or off voltage sequentially supplied to each gate line can be reduced.

Contact portion, gate on voltage, gate off voltage, gate driver, liquid crystal display, wiring resistance, voltage difference, COG

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

1 is a conceptual diagram of a liquid crystal display device according to an embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an embodiment of the present invention

3 is a layout diagram schematically illustrating a liquid crystal display device according to an embodiment of the present invention.

FIG. 4 is a layout diagram showing a thin film transistor panel for a liquid crystal display according to an exemplary embodiment of the present invention, in which a region where a gate line and a data line intersect each other, and a contact portion connected to a gate line and a data line, respectively.

5 is a cross-sectional view taken along line V-V 'in FIG.

FIG. 6 is an enlarged view of a gate drive wiring and a bypass line located in the upper left portion of FIG. 3 according to an embodiment of the present invention.

7 is a cross-sectional view taken along line VII-VII 'in FIG.

8 is an enlarged view of a gate driving wiring and a bypass line located at the upper left portion of FIG. 3 according to another embodiment of the present invention.

9 is a cross-sectional view taken along line IX-IX 'in Fig.

10 is a layout diagram schematically illustrating a liquid crystal display device according to another embodiment of the present invention.

11 is an enlarged view of a gate drive wiring and a bypass line located in the upper left portion of FIG. 10 according to another embodiment of the present invention.

The present invention relates to a liquid crystal display device.

A typical liquid crystal display (LCD) includes two display panels and a liquid crystal layer interposed therebetween having a dielectric anisotropy. A desired image is obtained by applying an electric field to the liquid crystal layer and adjusting the intensity of the electric field to adjust the transmittance of light passing through the liquid crystal layer. Such a liquid crystal display device is a representative example of a flat panel display (FPD) that is easy to carry, and a TFT-LCD using a thin film transistor (TFT) as a switching element is mainly used.

A plurality of gate lines and data lines are formed in the row and column directions on the display panel on which the thin film transistors are formed, and pixel electrodes connected to the gate lines and the data lines through the thin film transistors are formed. The thin film transistor controls a data signal transmitted through a data line according to a gate signal transmitted through a gate line, and transmits the data signal to the pixel electrode. A gate signal is generated by a plurality of gate driving ICs (integrated circuits) supplied with the gate-on voltage and the gate-off voltage generated by the driving voltage generating unit, by combining them under the control of the signal control unit. The data signal is obtained by converting a gradation signal from the signal control section into an analog voltage by a plurality of data driving ICs. The signal control unit and the driving voltage generating unit are usually provided on a printed circuit board (PCB) located outside the display panel, and the driving IC is a flexible printed circuit (FPC) substrate Respectively. In general, two PCBs are placed, one on the top and the other on the left side of the display panel. The left side is the gate PCB, and the one on the right side is the data PCB. A gate driving IC is placed between the gate PCB and the display panel, and a data driving IC is placed between the data PCB and the display panel, and each receives a signal from the corresponding PCB.

However, only the data PCB can be used without using the gate PCB, and the position of the gate-side FPC board and the gate driving IC above the gate PCB can be the same. At this time, in order to transfer the signals from the signal control unit and the driving voltage generating unit located on the data PCB to all the gate driving ICs, the data FPC board and the wiring are separately formed on the display panel. Wiring is also made on the gate FPC board so that signals can be transferred to the next gate drive IC.

In this way, the signal on the PCB, in particular the gate on or off voltage generated by the driving voltage generator, is transferred to the gate driver IC through the gate FPC board and the display panel, so that the entire signal path becomes longer, Or the OFF voltage is much lower than the original voltage. As a result, the gate on or off voltage applied to the gate line connected to the driving IC is also very low.

Further, since the length of the signal path of the gate on or off voltage reaching each gate driving IC is different and the gate on or off voltage supplied to the gate line is not constant, the turn on or turn off operation of the thin film transistor is unstable, Is different for each gate driving IC. As a result, a gate block phenomenon occurs in which the gradation difference occurs for each gate driving IC, resulting in poor image quality of the display device.

SUMMARY OF THE INVENTION It is an object of the present invention to stabilize the operation of a liquid crystal display device by reducing the gate ON or OFF voltage difference between a plurality of gate driving ICs and to improve image quality.

A liquid crystal display device according to an embodiment of the present invention includes:

A plurality of gate lines and a plurality of data lines formed in row and column directions,

A switching element connected to one of the gate lines and one of the data lines,

A gate drive voltage wiring for transferring a gate drive voltage for controlling the operation of the switching element, and a plurality of first signal lines located on one edge,

A second signal line electrically connected to the first signal line at least at one point,

And a liquid crystal panel assembly                     

/ RTI >

The gate driving voltage is transmitted through two paths of the first signal line and the second signal line.

It is preferable that the first signal lines are separated from each other. The liquid crystal display may further include a plurality of gate FPC substrates each including a second gate driving line and attached to the liquid crystal panel assembly, and the second gate driving line may be connected to two adjacent ones of the first signal lines. have. The liquid crystal display further includes a plurality of gate driving ICs mounted on the respective gate FPC boards for receiving the gate driving voltage through the second gate driving wiring and transmitting the gate driving voltage to the gate lines of the liquid crystal panel assembly can do.

The first signal lines are preferably connected to each other. The liquid crystal display device may further include a plurality of gate driving ICs mounted on the liquid crystal panel assembly and receiving the gate driving voltage through the gate driving voltage wiring line and transferring the gate driving voltage to the gate line.

The liquid crystal display according to an embodiment of the present invention includes a first gate driving line connected to the first first signal line and transmitting the gate driving voltage to the first first signal line, And a data FPC (flexible printed circuit) substrate.

The second signal line may be connected to the first signal line at at least two points.                     

One connection point of the first signal line and the second signal line is located in a first first signal line to which the gate driving voltage is applied first and the other is connected to a last one signal line to which the gate driving voltage is last applied, do.

In this case, a resistance connected to the first signal line may be further included, and a resistor connected to the second signal line may be further included. The number of the first signal lines is preferably four.

The first signal line may be formed in the same layer as the gate line, the second signal line may be formed in the same layer as the data line, and the first signal line and the second signal line may be formed in the same layer as the data line.

The liquid crystal display panel assembly may further include a pixel electrode connected to the switching element, and the first signal line and the second signal line may be connected to each other through a connection member made of the same layer as the pixel electrode.

It is preferable that a gate driving voltage having a different magnitude is applied to the first signal line and the second signal line, and in particular, a gate driving voltage applied to the second signal line is greater than a gate driving voltage applied to the first signal line .

In this case, the gate driving voltage may be a gate-on voltage for turning on the switching element, and may be a gate-off voltage for turning off the switching element.

It is also preferable that the second signal line crosses the gate line.

The embodiments of the present invention will now be described more fully with reference to the accompanying drawings, in which embodiments of the invention may be readily practiced by those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. It will be understood that when an element such as a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the element directly over another element, Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

FIG. 1 is a conceptual diagram of a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of a pixel of a liquid crystal display device according to an embodiment of the present invention.

1, a liquid crystal display device according to the present invention includes a liquid crystal panel assembly 300, a gate driver 400 and a data driver 500 connected thereto, A driving voltage generator 700 connected to the gate driving unit 400 and a gray voltage generator 800 connected to the data driving unit 500 and a signal controller for controlling the driving voltage generator 700 and the gray voltage generator 800, (600).

Liquid crystal panel assembly 300 includes a plurality of signal lines _{(G 1 -G n, D 1} -D m) and a plurality of pixels (pixel) connected thereto when viewed as an equivalent circuit, and each pixel has a signal line (G ₁ -G a switching element Q connected to the switching elements C _{1 to n} and D _{1 to} D _m and a liquid crystal capacitor C _lc and a storage capacitor C _st connected thereto. The signal lines G ₁ -G _n and D ₁ -D _m are connected to a plurality of scanning signal lines or gate lines G ₁ -G _n extending in the row direction to transmit a scanning signal or a gate signal, And a data signal line or a data line D ₁ -D _m extending in the column direction and transmitting an image signal or a data signal. The switching element Q is a three-terminal element, the control terminal thereof is connected to the gate lines G _{1 to} G _n , the input terminal thereof is connected to the data lines D _{1 to} D _m , C _lc and a storage capacitor C _st .

The liquid crystal capacitor C _lc is connected to an output terminal of the switching element Q to a common voltage V _com or a reference voltage. The other terminal of the holding capacitor C _st is connected to another voltage, for example a reference voltage. However, the other terminal of the storage capacitor C _st may be connected to the gate line immediately above (hereinafter referred to as "previous gate line"). The former is referred to as a separate wire type, and the latter is referred to as a previous gate type.

Meanwhile, the liquid crystal panel assembly 300 can be schematically shown in FIG. 2 as a structural view. For convenience, only one pixel is shown in FIG.

2, the liquid crystal panel assembly 300 includes a lower display panel 100 and an upper display panel 200 facing each other, and a liquid crystal layer 3 between the two. The lower panel 100 includes gate lines G _i-1 and G _i and a data line D _j and a switching element Q and a storage capacitor C _st . The liquid crystal capacitor C _lc has the pixel electrode 190 of the lower panel 100 and the reference electrode 270 of the upper panel 200 as two terminals and the liquid crystal layer 3 between the two electrodes 190 and 270 And functions as a dielectric.

The pixel electrode 190 is connected to the switching element Q and the reference electrode 270 is formed on the entire surface of the upper panel 200 and is connected to the common voltage V _com .

Here, the liquid crystal molecules change their arrangement according to the change of the electric field generated by the pixel electrode 190 and the reference electrode 270, and the polarization of the light passing through the liquid crystal layer 3 changes accordingly. Such a change in polarization is caused by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

The pixel electrode 190 is also provided with a separate wiring for receiving a reference voltage on the lower panel 100 and overlaps the pixel electrode 190 to form a storage capacitor C _st . In the case of the front-end gate method, the pixel electrode 190 overlaps the front _- end gate line G _i-1 via the insulator to form the two terminals of the storage capacitor C _st together with the front-end gate line G _i-1 .

FIG. 2 shows a MOS transistor as an example of the switching element Q. This MOS transistor is implemented as a thin film transistor in which an amorphous silicon or a polycrystalline silicon is used as a channel layer in an actual process .

2, the reference electrode 270 may be provided on the lower panel 100. In this case, the two electrodes 190 and 270 are all linearly formed.

In order to realize the color display, each pixel must be capable of displaying a color. In this case, a color filter 230 of red, green, or blue is provided in a region corresponding to the pixel electrode 190 It is possible. The color filter 230 may be formed on a corresponding region of the upper panel 200, as shown in FIG. 2, but may be formed on or below the pixel electrode 190 of the lower panel 100.

Again referring to Figure 1, the driving voltage generator 700 generates a gate-on voltage (V _on), and the gate-off voltage (V _off) turn turning off the switching device (Q), such as to turn on the switching element (Q) do.

The gradation voltage generator 800 generates a plurality of gray voltages related to the brightness of the liquid crystal display.

The gate driver 400 is also referred to as a scan driver and is connected to the gate lines G _{1 to} G _n of the liquid crystal panel assembly 300 to generate a gate on voltage V _on from the driving voltage generator 700, And a gate-off voltage (V _off ) is applied to the gate lines (G ₁ -G _n ).

The data driver 500 is also referred to as a source driver and is connected to the data lines D _{1 to} D _m of the liquid crystal panel assembly 300 to select the gradation voltage from the gradation voltage generator 800, Signal to the data lines D ₁ -D _m .

The signal controller 600 generates control signals for controlling operations of the gate driver 400, the data driver 500 and the driving voltage generator 700 and supplies the corresponding control signals to the gate driver 400, To the driving unit 500 and the driving voltage generator 700.

The gate driver 400 and the data driver 500 are generally comprised of a plurality of gate driver ICs (integrated circuits) 441-444 and a data driver IC 540, as shown in FIG. 3, each IC is separately provided outside the liquid crystal panel assembly 300, but it may be mounted on the liquid crystal panel assembly 300 ([COG (chip on glass)], the signal lines G ₁ -G _n , D ₁ -D _m , and the thin film transistor Q may be formed on the liquid crystal panel assembly 300 in the same process.

Hereinafter, the structure of a liquid crystal display device according to an embodiment of the present invention will be described in detail with reference to FIG.

3 is a layout diagram schematically illustrating a liquid crystal display device according to an embodiment of the present invention.

3, a signal controller 600 (not shown) for driving the liquid crystal display is provided above the liquid crystal panel assembly 300 having the gate lines G ₁ -G _n and the data lines D ₁ -D _m , A printed circuit board (PCB) 550 provided with circuit elements such as a driving voltage generating unit 700 and a gradation voltage generating unit 800 is located. The liquid crystal panel assembly 300 and the PCB 550 are electrically and physically connected to each other through a flexible printed circuit (FPC)

A data driving IC 540 is mounted on the data FPC substrate 510 and a plurality of data lead wires 520 and gate driving signal wires 521-523 are formed. The data lead line 520 is connected to the output terminal of the data driving IC 540 and is connected to the data lines D _{1 to} D _m through the contact portion C 2 and supplies data from the data driving IC 540 to the data lines D ₁ -D _m . Although only three gate driving signal lines 521 to 523 are illustrated in FIG. 5, the number is actually four or more. As will be described later, in the present embodiment, the signal line 521 is a signal line for transmitting a gate on or off voltage, the signal line 522 is for example a gate clock signal, and the signal line 523 is a vertical synchronization start signal . The signal lines 521-523 are electrically connected to the circuit elements of the PCB 550, and the data driving IC 540 is also the same.

Four gate FPC boards 411-414 are attached to the left side of the liquid crystal panel assembly 300 and gate drive ICs 441-444 are attached to the gate FPC boards 411-414 respectively. A plurality of gate lead lines 420 and gate drive signal lines 421, 422, 423a, and 423b are formed on the FPC boards 411-414. Some of the signal lines 421 and 422 of the gate drive signal lines 421 and 422 are connected to the input terminals of the gate drive ICs 441-444 except for some signal lines 423a and 423b, Has one end connected to the gate driving ICs 441-444. The signal line 423a positioned above the other signal lines 423a and 423b is connected to the input terminal of the gate driving ICs 441-444 and the signal line 423b located below the gate driving ICs 441-444 is connected to the gate driving ICs 441-444 Output terminal. Although only four gate driving signal lines 421, 422, 423a, and 423b are shown in FIG.

A plurality of pixel regions defined by the intersection of the horizontal gate lines G ₁ -G _n and the vertical data lines D ₁ -D _m provided in the liquid crystal panel assembly 300 as shown in FIG. 3 Thereby forming a display area D for displaying an image. A black matrix 220 is provided outside the display area D (shaded area) to block light leaking outside the display area D. The gate lines G ₁ -G _n and the data lines D ₁ -D _m remain substantially parallel to each other in the display area D, but when they are out of the display area D, So that the gap between them becomes narrower, and again, a substantially parallel state is obtained.

Gate driving signal wirings 321a-321d, 322a-322d, and 323a-323d are formed on the upper left and upper left edges of the liquid crystal display panel assembly 300 outside the display area D, respectively. The gate drive signal wirings 321a, 322a and 323a located at the upper left corner are electrically connected to the gate drive signal wirings 521, 522 and 523 of the data FPC board 510 via the contact C4, C3, and the gate drive signal wirings 421, 422, 423a of the uppermost gate FPC substrate 411, respectively. Another gate drive signal lines (321b-321d, 322b-322d , 323b-323d) is a gate line (G ₁ -G _n) gate FPC substrate adjacent through the contact portions (C5, C6) and positioned between the assembled parts ( 421, 421, 421, 421, 421, 421, 421, 421, 421, 421, 421,

A gate on or off voltage bypass line 321 is also formed on the left edge of the liquid crystal panel assembly 300. One end of the bypass line 321 is connected to the signal line 321a for transferring the gate on or off voltage through the contact C7 and the other end is connected to the third gate driving IC 423 through the contact C8. And the gate driving signal wiring 321d between the fourth gate driving IC 444 and the fourth gate driving IC 444. Bypass line 321 crosses the gate line (G ₁ -G _m) gate lines (G ₁ -G _m) due to the position on the inside of the contact portion (C1) of the gate lead wires 420. Although the bypass line 321 is formed separately in this embodiment, a gate line or a repair line for repairing a data line, which is disposed at the edge of the liquid crystal panel assembly 300 and can not perform normal signal transmission due to disconnection or the like, is used It is possible.

An FPC board (not shown), to which the data driving IC 540 is not attached, may be attached to the PCB 550 and the liquid crystal panel assembly 300 in addition to the data FPC board 510. In this case, 521-523 may be provided on the FPC board.

The gate lines G ₁ -G _n , the data lines D ₁ -D _m and the signal lines 521-523 of the liquid crystal panel assembly 300 at the contacts C1-C8 and the FPC boards 411-414 And the signal lines 321a-321d, 322a-322d, and 323a-323d are connected through the anisotropic conductive film. The specific connection structure will be described later in detail.

The display operation of such a liquid crystal display device will be described in more detail.

The signal controller 600 included in the PCB 550 receives RGB data signals R, G, and B from an external graphic controller (not shown) and a control input signal a vertical synchronizing signal V _sync and a horizontal synchronizing signal H _sync , a main clock CLK and a data enable signal DE, . The signal controller 600 generates a gate control signal and a data control signal based on the control input signal and appropriately processes the gray scale signals R, G, and B according to the operation conditions of the liquid crystal panel assembly 300, And outputs the gray level signals R ', G', and B 'processed with the data control signal to the data driver 500. The gray level signals R', G ', and B'

The gate control signal includes a vertical synchronization start signal (STV) for indicating the start of output of the gate-on pulse (high section of the gate signal), a gate clock signal (gate clock signal) for controlling the output timing of the gate- CPV) and a gate on enable signal (OE) that defines the width of the gate on pulse. In this case, the gate-on enable signal OE and the gate clock signal CPV are supplied to the driving voltage generator 700. The data control signal includes a horizontal synchronization start signal (STH) for instructing the start of the input of the gray-scale signal, a load signal (LOAD or TP) for applying the corresponding data voltage to the data line, And an inverted control signal RVS and a data clock signal HCLK.

On the other hand, the driving voltage generating unit 700 includes a signal controller 550, a common voltage (V _com is applied to the gate turn-on voltage (V _on), gate turn-off voltage (V _off) and the reference electrode 270 in response to the control signal from the And supplies the gate-on voltage V _on and the gate-off voltage V _off to the gate driver 400. The gradation voltage generator 800 generates a plurality of gradation voltages related to the brightness of the liquid crystal display and applies the gradation voltages to the data driver 500.

At this time, the gate control signal of the gate clock signal (CPV), gate-on enable signal (OE) etc. and the gate-on voltage (V _on) is each of the gate driving IC (441 via the signal line (522, 322a-322d, 422 ) And the vertical synchronization start signal STV is supplied to the first gate driving IC 441 through the signal lines 523, 323a, and 423a.

In this embodiment, the gate on or off voltage (V _on , V _off are supplied in parallel to the gate driving ICs 441-444 through the signal lines 521 and 321a-321d and 421 while the third and fourth driving ICs 443 and 444 ). The gate-on voltage (V _on) the signal line (521, 321a-321d, 421 ) and is supplied through the bypass line 321, a gate-off voltage (V _off) is another signal line, for example, the signal line (522, 322a-322d , 422, and vice versa.

The voltage at the contact C8 between the signal line 321a and the bypass line 321 becomes a value reduced by a value proportional to the wiring resistance of the bypass line 321 at the voltage of the contact C7. Since the length of the bypass line 321 is much smaller than the length of the signal lines 321a-321d and 421 between the two contact portions C7 and C8, the voltage drop is small and the contact portion C8 ) Is high. Therefore, the difference in size of the gate on or off voltages (V _on , V _off ) supplied to the gate driving ICs 441 - 444 is reduced.

A gate driver 400, a gate-on voltage (V _on), and then the gate lines (G ₁ -G _n), the gate lines (G ₁ -G _n) is applied to the gate according to the control signal from the signal controller 600, And turns on the switching elements Q of the connected row. At the same time, the data driver 500 generates a gradation voltage corresponding to the gradation signals R ', G' and B 'in the pixel row where the switching element Q is turned on according to the data control signal from the signal controller 600 And supplies the gradation voltage, which is an analog voltage from the unit 800, to the data lines D ₁ -D _m as data signals. The data signals supplied to the data lines D ₁ -D _m are applied to the corresponding pixels through the turned-on switching elements Q. In this manner, the applied data signals to all the pixel rows by applying a frame gate-on voltage (V _on) in turn for all of the gate lines (G ₁ -G _n) for a (frame). At this time, if the data signal is applied to the pixels of all the rows corresponding to one frame and then the reverse control signal RVS is supplied, the polarities of the data signals of all the rows corresponding to the next frame are changed.

This process is explained in more detail.

The first gate driving IC (441) receiving the vertical synchronization start signal (STV) is the first gate by selecting the gate-on voltage (V _on) of the two voltages (V _on, V _off) from the driving voltage generator 700 And outputs it to the line G ₁ . At this time, gate off voltage V _off is applied to the other gate lines G ₂ -G _n . The switching element Q of the first row connected to the first gate line G ₁ is conducted by the gate on voltage V _on and the data signal of the first row is turned on through the switching element Q of the first row, Is applied to the liquid crystal capacitor C _lc and the storage capacitor C _st of the pixel of the row. After the charging of the capacitors C _lc and C _st of the pixels of the first row is completed after a predetermined time has elapsed, the first gate driving IC 441 applies the gate-off voltage V _off to the first gate line G ₁ The connected switching element Q is turned off and the gate-on voltage V _on is applied to the second gate line G ₂ .

All gate lines gate-on voltage (V _on) for applying at least once a first gate driving IC (441) connected in this way, the second gate with the carry (carry) signal indicating that the scan is complete, via the signal line (423b, 323b) And supplies it to the driving IC 442.

The second gate driving IC 442 receiving the carry signal scans all the gate lines connected thereto in the same manner and supplies the carry signal to the next gate driving IC 413 through the signal lines 423b and 323c. When the scanning operation of the last gate driving IC 444 is completed in this manner, one frame is completed.

As described above, the liquid crystal display panel assembly 300 includes two display panels 100 and 200, and the lower display panel 100 having the dual thin film transistors is referred to as a "thin film transistor display panel ". The gate drive signal lines 321a-321d, 322a-322d, and 323a-323d and the bypass line 321 are provided in the thin film transistor display panel 100 in FIG. 3, 7 Will be described in detail with reference to FIG.

FIG. 4 is a layout diagram showing a thin film transistor panel for a liquid crystal display according to an embodiment of the present invention. In FIG. 4, a region where a gate line and a data line intersect each other and a contact portion C1 and C2 connected to a gate line and a data line, respectively And FIG. 5 is a cross-sectional view cut along the line VV 'in FIG. 6 is an enlarged view of the gate driving signal line 321a and the bypass line 321 located at the upper left portion of FIG. 3 according to an embodiment of the present invention. FIG. 7 is a cross-sectional view taken along line VII- Fig.

A gate wiring made of a metal such as aluminum (Al) or an aluminum alloy, molybdenum (Mo), molybdenum-tungsten alloy (MoW), chromium (Cr), tantalum (Ta) 121, 123, and 125, and gate drive signal lines 132, 137, and 138 are formed.                     

The gate wirings 121, 123 and 125 are connected to the ends of a plurality of gate lines 121 extending in the horizontal direction, a gate electrode 123 which is a part of the gate lines 121 and a gate line 123, And a gate pad 125 for transferring the gate signal to the gate line 121.

The gate driving signal lines 132, 137 and 138 include a driving signal line 132 and two pads 137 and 138 connected to both ends of the driving signal line 132. The two pads 137 and 138 are located near the upper left edge of the upper left portion of the substrate 110 and the upper left edge of the upper portion of the substrate 110 and the drive signal line 132 is connected between the pads 137 and 138. The pads 138 near the upper left edge of the pads 137 and 138 receive the gate on or off voltages V _on and V _off from the gate drive signal line 521 of the data FPC board 510, (132). The pad 137 located near the left edge of the upper left portion supplies the gate on or off voltage V _on and V _off of the driving signal line 132 to the gate driving signal wiring 421 of the gate FPC board 411.

The gate wirings 121, 123, and 125 and the gate drive signal wirings 132, 137, and 138 may be formed as a single layer, but may be formed as two or more layers. At this time, it is preferable that one layer is made of a material having a small resistance and the other layer is made of a material having good contact properties with other materials, for example, a double layer of chromium and aluminum alloy or a double layer of molybdenum or molybdenum alloy and aluminum .

The gate wirings 121, 123 and 125 and the gate drive signal wirings 132, 137 and 138 are covered with a gate insulating film 140 made of silicon nitride (SiN _x ).

A semiconductor layer 150 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 140 on the gate electrode 123. An amorphous semiconductor layer 150 doped with an n-type impurity such as phosphorus The ohmic contact layers 163 and 165 made of a semiconductor such as silicon are formed on both sides of the gate electrode 123 as a center.

The data lines 171, 173, 175 and 179 made of a metal or a conductor such as aluminum or an aluminum alloy, molybdenum or a molybdenum-tungsten alloy, chromium, or tantalum, and a gate insulating film 140 are formed on the resistive contact layers 163 and 165 and the gate insulating film 140, A line 172 is formed.

The data lines 171, 173, 175 and 179 have a plurality of data lines 171 extending in the longitudinal direction, a source electrode 173 as a branch of the data line 171, And a data pad 179 connected to the data line 171 and receiving an image signal from the outside to transmit the image signal to the data line 171. [

The bypass line 172 mainly extends in the longitudinal direction and has one end located in the vicinity of the drive signal line 132 of the gate drive signal line. Although not shown in FIG. 6, the other end of the bypass line 172 is located near the gate drive signal line 321d between the third gate drive IC 443 and the fourth gate drive IC 444.

The data lines 171, 173, 175 and 179 and the bypass line 172 may be formed as a single layer like the gate lines 121, 123 and 125 and the gate driving signal lines 132, 137 and 138, As shown in FIG. In the case of forming at least two layers, it is preferable that one layer is formed of a material having a small resistance and the other layer is made of a material having good contact properties with other materials.

Here, the gate electrode 123, the semiconductor layer 150, the source electrode 173, and the drain electrode 175 constitute a thin film transistor (TFT).

A protective film 180 made of silicon nitride or an organic insulating film is formed on the data lines 171, 173, 175 and 179 and the bypass line 172 and the semiconductor layer 150 and the gate insulating film 140 not covered with the data lines 171, The protective film 180 has contact holes 183 and 187 for exposing the data pad 179 and the bypass line 172 at the contact portions C2 and C7 and a contact hole 181 for exposing the drain electrode 175 Have. The protective film 180 may be formed by exposing the gate pad 125 and the pads 138 and 137 of the gate driving signal wiring and the driving signal line 132 with the gate insulating film 140 at the contacts C1, And has contact holes 182, 184, 185, and 186.

A pixel electrode 190 made of a transparent conductive material such as ITO (indium tin oxide) or IZO (indium zinc oxide), an auxiliary gate pad 95, an auxiliary data pad 97, Auxiliary pads 96 and 98 and a connecting member 99 are formed.

The pixel electrode 190 is connected to the drain electrode 175 through the contact hole 181 to receive an image signal. The auxiliary gate pad 95 and the auxiliary data pad 97 are connected to the gate pad 125 and the data pad 179 via the contact holes 182 and 183, Complement the adhesion to circuit devices and protect the pads 125 and 179. The auxiliary pads 96 and 98 are connected to the pads 137 and 138 of the gate driving signal wiring through contact holes 184 and 185, respectively. The connecting member 99 is connected to the driving signal line 132 through the contact hole 186 and is connected to the bypass line 172 through the contact hole 187.

The auxiliary signal connection pad 95 for the gate signal is connected to the connection pad 125 for the gate signal through the contact hole 182.

Next, the structure of the contact portion C7, to which the gate driving signal line 321a and the bypass line 321 are connected, according to another embodiment of the present invention will be described in detail with reference to FIGS. 8 and 9. FIG.

8 is an enlarged view of a gate driving line 321a and a bypass line 321 according to another embodiment of the present invention, and FIG. 9 is a cross-sectional view taken along line IX-IX 'of FIG.

6 and 7, only the bypass line 172 is formed in the same layer as the data line and the gate drive signal lines 132, 137 and 138 are formed in the same layer as the gate line. However, in FIGS. 8 and 9, Both the wirings 176, 174, 179 and the bypass line 172 are formed in the same layer as the data wiring. Therefore, the bypass line 172 is spaced apart from the drive signal line 174 at a certain distance.

In other words, the gate drive signal lines 176, 174, and 179 are disposed between the gate insulating layer 140 and the passivation layer 180 and contact holes 188, 1810, and 189 that expose the gate drive signal lines 176, 174, Only the protective film 180 is formed.

The structure of the bypass line 321 and the contact C8 is the same as the structure of the gate drive signal line 321a and the contact C7 already described and the structure of the contacts C5- And the detailed description thereof will be omitted.

In this embodiment, the voltage value of the first gate drive IC (441) and the third or fourth gate drive IC (443, 444) the gate-on or turn-off voltage (V _on, V _off) is applied to the contact (C7) The shortest path leading to the first driving IC 441 from the contact C7 to the shortest path from the contact C7 to the first path on the signal lines 321a and 421 and the shortest path from the contact C7 to the third driving IC 443, That is, the resistance of the second path through the bypass line 321. The difference between the gate drive signal lines 321a and 421 and the bypass line 321 due to difference in length or width or material. A resistor having a resistance value equal to the difference in wiring resistance value between the two paths may be provided in the bypass line 321 and the gate drive signal line 321a so that the voltage values become equal to each other.

Next, another embodiment of the present invention will be described with reference to FIGS. 10 and 11. FIG.

FIG. 10 is a layout diagram schematically illustrating a liquid crystal display device according to another embodiment of the present invention. FIG. 11 is a cross-sectional view of a liquid crystal display device according to another embodiment of the present invention, FIG.

The bypass line 321 is connected to the gate driving signal line 524 which is not connected to the signal line 521 and is further formed on the data FPC substrate 510 and the signal lines 521 and 523 are connected, (V _on , V _off ) having different values are supplied to the gate electrode of the transistor.

Since the signal path leading to the third or fourth gate driving IC 443 or 444 is longer than the signal path leading to the first gate driving IC 441 through the bypass line 321, The wiring resistance is large. Therefore, it is preferable that the voltage applied to the signal line 524 is made larger than the voltage applied to the signal line 521. [

Although the bypass line 321 is connected to the third gate driving IC 443 and the fourth gate driving IC 444 in the embodiment of the present invention, the position of the bypass line 321 can be changed, 321 may be connected to the respective gate driving ICs 441-444, respectively.

In addition, one has been described in the case where only any one of the embodiments of the invention the gate-on voltage (V _on) and the gate-off voltage (V _off) are supplied to the two paths, both the voltage (V _on, V _off) two Path. ≪ / RTI > At this time, two bypass lines 321 according to the embodiment of the present invention are placed.

Although only the case where the gate driver ICs 441 to 444 are mounted on the gate FPC boards 411 to 414 has been described in the above-described embodiments, the gate driver may be mounted directly on the liquid crystal display panel assembly 300 in the form of chips The present invention can be applied even when it is formed. In this case, since there is no gate FPC substrate, signal lines transmitting gate on or off voltages (V _on , V _off ) are all formed in the liquid crystal panel assembly 300.

When gate on or off voltages are sequentially applied to a plurality of gate driving ICs, a gate on or off voltage is simultaneously supplied to another gate driving IC to which a gate on or off voltage is finally applied using a bypass line. Therefore, the difference in the gate on or off voltage between the gate driving ICs is reduced, and the variation width of the gate on or off voltage sequentially supplied to each gate line can be reduced.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, Of the right.

Claims (20)

A plurality of gate lines and a plurality of data lines formed in row and column directions, A switching element connected to one of the gate lines and one of the data lines, A gate drive voltage wiring for transferring a gate drive voltage for controlling the operation of the switching element, and a plurality of first signal lines located on one edge, A second signal line electrically connected to the first signal line at least at one point, And a liquid crystal panel assembly / RTI > Wherein the gate driving voltage is transmitted through two paths: the first signal line and the second signal line. The method of claim 1, Wherein the first signal lines are separated from each other. 3. The method of claim 2, And a plurality of gate FPC substrates each including a second gate driving wiring and attached to the liquid crystal panel assembly, and the second gate driving wiring is connected to two adjacent ones of the first signal lines. 4. The method of claim 3, And a plurality of gate driving ICs mounted on the respective gate FPC boards for receiving the gate driving voltage through the second gate driving wiring and transmitting the gate driving voltage to the gate lines of the liquid crystal panel assembly. The method of claim 1, And the first signal lines are connected to each other. The method of claim 5, And a plurality of gate driving ICs mounted on the liquid crystal display panel assembly for receiving the gate driving voltage through the gate driving voltage wiring and transferring the gate driving voltage to the gate line. 7. The method according to any one of claims 1 to 6, And a data FPC (flexible printed circuit) substrate attached to the liquid crystal display panel assembly, the first gate drive wiring being connected to the first first signal line and transmitting the gate driving voltage to the first first signal line Liquid crystal display device. 7. The method according to any one of claims 1 to 6, And the second signal line is connected to the first signal line at at least two points. 9. The method of claim 8, One connection point of the first signal line and the second signal line is located in a first first signal line to which the gate driving voltage is applied first and the other is connected to a last one signal line to which the gate driving voltage is last applied, . The method of claim 9, And a resistor connected to the first signal line. The method of claim 9, And a resistor connected to the second signal line. 7. The method according to any one of claims 1 to 6, And the number of the first signal lines is four. The method of claim 1, Wherein the first signal line is formed in the same layer as the gate line, and the second signal line is formed in the same layer as the data line. The method of claim 1, Wherein the first signal line and the second signal line are formed in the same layer as the data line. The method according to claim 13 or 14, Wherein the liquid crystal display panel assembly further includes pixel electrodes connected to the switching elements, and the first signal line and the second signal line are connected to each other through a connection member made of the same layer as the pixel electrode. The method of claim 1, And a gate driving voltage of a different magnitude is applied to the first signal line and the second signal line. 17. The method of claim 16, Wherein a value of a gate driving voltage applied to the second signal line is greater than a gate driving voltage applied to the first signal line. 7. The method according to any one of claims 1 to 6, And the gate driving voltage is a gate-on voltage for turning on the switching element. 7. The method according to any one of claims 1 to 6, And the gate driving voltage is a gate-off voltage for turning off the switching element. 7. The method according to any one of claims 1 to 6, And the second signal line crosses the gate line.

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