KR100840324B1 - Liquid Crystal Display for Compensating Gate Line Signal Delay - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display and a driving method thereof for compensating signal delay on a gate line by appropriately applying a counter electrode voltage in a thin film transistor liquid crystal display (TFT LCD).

In the liquid crystal display of the present invention, the voltage generating unit generates a counter electrode voltage having a predetermined waveform at the time when the gate voltage is changed from the on state to the off state, and applies the same to the liquid crystal panel to charge the amount of charge voltage between the left and right pixels of the liquid crystal panel. By reducing the difference of, the left and right pixels of the liquid crystal panel due to the signal delay in the gate line can effectively improve the display quality difference, DC stress (DC stress) to the liquid crystal material, afterimage problems, and the like.

Liquid crystal display, gate line, RC delay, signal delay, counter electrode

Description

Liquid crystal display for compensating gate line signal delay {A LIQUID CRYSTAL DISPLAY FOR COMPENSATING FOR SIGNAL DELAY IN GATE LINES}

1 is a block diagram of a liquid crystal display according to a first embodiment of the present invention.

2A to 2C are waveform diagrams of gate and counter electrode voltages applied to a liquid crystal display according to a second exemplary embodiment of the present invention.

3A and 3B are waveform diagrams of gate voltages and counter electrode voltages for respective positions on a liquid crystal panel obtained through simulation in a second embodiment of the present invention.

4A and 4B are waveform diagrams of pixel voltages and counter electrode voltages of respective positions on a liquid crystal panel obtained through simulation in a second embodiment of the present invention.

5A to 5C are waveform diagrams of gate and counter electrode voltages applied to a liquid crystal display according to a third exemplary embodiment of the present invention.

6A and 6B are waveform diagrams of pixel voltages and counter electrode voltages of respective positions on a liquid crystal panel obtained through simulation in a third embodiment of the present invention.

7A to 7C are waveform diagrams of gate and counter electrode voltages applied to a liquid crystal display according to a fourth exemplary embodiment of the present invention.

8A and 8B are waveform diagrams of pixel voltages and counter electrode voltages of respective positions on the liquid crystal panel obtained through simulation in the fourth embodiment of the present invention.                 

(Explanation of symbols for the main parts of the drawing)

1: liquid crystal panel 2: gate driver

3: source driver 4: timing controller

5: voltage generator

The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal for compensating signal delay on a gate line by appropriately applying a counter electrode voltage in a thin film transistor liquid crystal display (TFT LCD). It relates to a display device.

In recent years, as a liquid crystal display device is mainly used as a computer monitor, a large screen liquid crystal display device is getting into the spotlight. In a liquid crystal display device, a display is realized by controlling transmittance of a liquid crystal material injected between two layers of electrodes by a voltage difference applied to the two electrodes. Here, the electrode is patterned to form a plurality of pixels, and each pixel is formed with a thin film transistor that operates as a switch element. The thin film transistor controls whether data voltage is applied to a corresponding pixel.

In general, the liquid crystal panel of the thin film transistor liquid crystal display device has a matrix pixel structure. For example, a plurality of gate lines and data lines vertically cross each other, and a thin film transistor is formed between each gate line and the data line. In addition, the thin film transistor is connected with the pixel of the above-described structure. The upper electrode of the electrode layers constituting the pixel is called a pixel electrode, and the lower electrode is called a counter electrode. The on / off of the thin film transistor is controlled according to the level of the gate voltage applied to the gate line. When the thin film transistor is turned on, a data voltage applied through the data line is transferred to the pixel electrode of the corresponding pixel. The gray display of the pixel is performed according to the difference between the voltage applied to the counter electrode and the counter electrode.

The gate driver and the source driver are connected to the liquid crystal panel, and the gate voltage and the data voltage are supplied to the liquid crystal panel through the gate driver and the source driver. As a method of arranging the gate driver and the source driver, a single bank structure in which one gate driver and one source driver are disposed only on one side of the liquid crystal panel, and two gate drivers and two source drivers It is divided into a dual bank structure arranged on both sides of the panel. As the liquid crystal panel becomes larger, the single bank structure is more advantageous because the area occupied by the gate driver and the source driver in the liquid crystal module must be reduced.

However, in the liquid crystal display of the single bank structure, there is a problem that the signal delay in the gate line becomes more severe. This signal delay is caused by parasitic capacitance and self-resistance components present in the gate line. For example, when the gate driver is disposed on the left side of the liquid crystal panel, if a gate voltage is applied to any gate line, the gate voltage actually measured at the rightmost point of the gate line is actually measured at the leftmost point of the gate line. It has a waveform that is much more delayed than the gate voltage. Due to the delay of the gate voltage, the kickback voltage is different in the pixel at each point. This is because charge is supplied through the thin film transistor (TFT) of the pixel at the corresponding position for a predetermined time when the delayed waveform of the gate voltage is applied. Therefore, even when the data voltage of the same gray level is applied to the pixels of one line, the voltage to be charged varies between the leftmost point closest to the gate driver and the rightmost point farthest from the gate driver. This difference in charging voltage is tolerated to a certain extent, but when it reaches a degree exceeding one gradation level interval (about 20 mV), the left and right display difference of the liquid crystal panel for the same gradation may be visually identified. Conventionally, since such a difference in charge voltage is about 110 mV, it is pointed out as a problem which greatly reduces display quality. As described above, the difference in the charging voltage between the left and right pixels of the liquid crystal panel due to the signal delay in the gate line may cause deterioration in image quality by causing DC stress, afterimage problems, etc., in addition to the display quality degradation. It also works as a cause.

SUMMARY OF THE INVENTION The present invention has been made under the above-described technical background, and provides a liquid crystal display device which can reduce a difference in charging voltage between left and right pixels of a liquid crystal panel by applying a counter electrode voltage having a predetermined waveform at a turn-off time of a gate voltage. It aims to do it.

The liquid crystal display device of the present invention for achieving the above object,

A plurality of gate lines to which a gate voltage is applied, a plurality of data lines respectively crossing the plurality of gate lines, and a data voltage to which an image signal is applied, and a gate at a point where the gate lines and the data lines cross each other; A thin film transistor connected to a source line and a source connected to a corresponding data line, a pixel electrode connected to a drain of the thin film transistor, to which a data voltage is applied when the thin film transistor is turned on, and an opposite electrode forming a capacitance together with the pixel electrode. Having a liquid crystal panel;

A gate driver for applying a gate voltage to the gate line to periodically turn on / off the thin film transistor;

A source driver for applying a data voltage representing an image signal to the data line;

A voltage generator configured to generate the gate voltage, the data voltage, and a voltage for applying to the counter electrode, and to have a voltage applied to the counter electrode at a time when the gate voltage changes from an on state to an off state; And

It includes a timing controller for adjusting the timing of the gate voltage and the data voltage to be used in the gate driver and the source driver.

In the above configuration of the present invention, the counter electrode voltage having a predetermined waveform is generated in the voltage generator at the time when the gate voltage drops from the on state to the off state. The waveform of the counter electrode voltage may be a pulse wave, a triangular wave or a trapezoidal wave, and the waveform may have a duration smaller than one horizontal scan period and greater than or equal to the signal delay time of the gate voltage, and the voltage width is 1 V or less. desirable. In this way, by applying a voltage having a predetermined waveform as the counter electrode voltage, even if a signal delay occurs in the gate line, even if the thin film transistor is turned on due to the gate delay effect by the waveform, charge inflow is minimized and the left and right sides of the liquid crystal panel are minimized. The inter-pixel charging voltage difference can be reduced. Accordingly, the left and right pixels of the liquid crystal panel due to the signal delay in the gate line may improve display quality difference, DC stress on the liquid crystal material, and afterimage problems.

The objects, technical configurations, and effects thereof of the present invention described above will become more apparent from the following description of the embodiments.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

First, a liquid crystal display according to a first embodiment of the present invention will be described with reference to FIG. 1, and FIG. 1 illustrates a configuration of a liquid crystal display according to a first embodiment of the present invention.

As shown in FIG. 1, the liquid crystal display according to the first exemplary embodiment of the present invention includes a liquid crystal panel 1, a gate driver 2, a source driver 3, a timing controller 4, and a voltage generator 5. It consists of).                     

In order to show the structure of the liquid crystal panel 1 in more detail, an arbitrary pixel A is displayed in an enlarged state. The liquid crystal panel 1 is composed of two electrode layers and a liquid crystal material injected therebetween, and has a structure in which a plurality of pixels are arranged in a matrix form. The upper electrode, that is, the pixel electrode, of the electrode layer includes an electrode pattern, a thin film transistor, and a plurality of gate lines G and data lines D orthogonal to each other, forming one electrode of the liquid crystal capacitor C _LC and the storage capacitor C _st . ) Is formed. An electrode pattern constituting the other electrode of the liquid crystal capacitor C _LC and the storage capacitor C _st is formed on a lower electrode, that is, an opposite electrode, of the electrode layer. In the above structure, the gate of the thin film transistor is connected to the gate line (G), the source is connected to the data line (D), and the drain is connected to one electrode of the liquid crystal capacitor (C _LC ) and the sustain capacitor (C _st ). It is connected at the same time. The gate voltage applied to the gate line G has an on period and an off period that are periodically repeated, and the thin film transistor is turned on during the on period. In this case, the data voltage applied through the data line is applied to the pixel electrode via the thin film transistor, which is also referred to as the pixel voltage Vp. On the other hand, since the common voltage Vcom and the sustain voltage Vst are applied to the other electrodes of the liquid crystal capacitor C _LC and the sustain capacitor C _st , the pixel voltage Vp and the common voltage Vcom A voltage corresponding to the difference is applied to the liquid crystal capacitor C _LC , and the transmittance of the liquid crystal material is determined according to the voltage, thereby obtaining a predetermined display. Here, the common voltage Vcom and the sustain voltage Vst may be referred to as counter electrode voltages, and the specific names of the above-described voltages may vary according to the type or manufacturer of the liquid crystal display.

In FIG. 1, the voltage generator 5 generates a voltage required for driving the liquid crystal panel 1, that is, a gate on / off voltage, a gray voltage, and an opposite electrode voltage, and supplies the generated voltage to the timing controller 4. Conventionally, a direct current voltage is applied as the counter electrode voltage. However, in the present invention, a pulse wave, a triangle wave, or a trapezoidal wave having a predetermined duration is used as the counter electrode voltage when the gate voltage falls from the on state to the off state. do. Thus, the voltage generator 5 generates pulse waves, triangle waves or trapezoidal waves having the above-described timing as counter electrode voltages. Here, the pulse wave, the triangular wave or the trapezoidal wave has a duration less than one horizontal scanning period which is the display period of the screen and greater than or equal to the signal delay time of the gate voltage, and the voltage width is preferably 1 V or less. In this way, by applying a voltage having a predetermined waveform as the counter electrode voltage, even if a signal delay occurs in the gate line, even if the thin film transistor is turned on due to the gate delay effect by the waveform, charge inflow is minimized and the left and right sides of the liquid crystal panel are minimized. The inter-pixel charging voltage difference can be reduced.

The timing controller 4 receives the RGB data, the control signal, and the voltages supplied from the voltage generator 5, adjusts the timing of these signals, and receives signals necessary for driving the liquid crystal panel 1. Create

The gate driver 2 appropriately converts the gate voltage generated by the voltage generator 5 through the timing controller 4 to be applied to the liquid crystal panel 1, and then converts the gate voltage. Is applied to each gate line.

The source driver 3 may receive the gray voltage generated by the voltage generator 5 through the timing controller 4, select an appropriate gray voltage according to the RGB data, and apply the gray voltage to the liquid crystal panel 1. Are converted and applied to each data line of the liquid crystal panel 1.

Next, a liquid crystal display according to a second exemplary embodiment of the present invention will be described with reference to FIGS. 2 to 4.

2A to 2C are waveform diagrams of gate and counter electrode voltages applied to the liquid crystal display according to the second embodiment of the present invention, and FIGS. 3A and 3B are simulations of the second embodiment of the present invention. Waveform diagrams of the gate voltage and the counter electrode voltage for each position on the liquid crystal panel obtained through FIG. 4 are shown. FIGS. 4A and 4B show the pixel voltage and the counter electrode voltage for each position on the liquid crystal panel obtained through simulation in the second embodiment of the present invention. The waveform diagram of is shown.

The second embodiment of the present invention is characterized in that a pulse wave having a predetermined pulse width is used as the counter electrode voltage at the time when the gate voltage changes from the on state to the off state instead of the direct current voltage.

The waveform of FIG. 2A is the waveform of the gate voltage 21 supplied to the gate line and the waveform 22 actually measured at the gate line, the waveform of FIG. 2B is the waveform of the counter electrode voltage, and the waveform of FIG. 2C is the conventional counter electrode voltage. Waveform.                     

The counter electrode voltage has a waveform in the form of a pulse at the time when the gate voltage falls from the on state to the off state, the pulse width of which is smaller than one horizontal scanning period and greater than or equal to the signal delay time of the gate voltage, and whose amplitude is 1 V or less. It is preferable. That is, when the gate voltage is actually delayed in the liquid crystal panel due to the signal delay, the counter electrode voltage as shown in FIG. 2B is applied at the time when the gate voltage is turned off, thereby increasing the pixel voltage by the counter electrode voltage. At this time, the thin film transistor is turned on in the pixel of the liquid crystal panel that is far from the driving part of the gate line due to the delayed gate voltage waveform, but the charge voltage is minimized by the increase of the pixel voltage due to the counter electrode voltage of the pulse waveform. do. In the related art, an unintended turn-on state of a thin film transistor is continued in a pixel of a gate line far from the gate driver due to the delayed gate waveform, thereby overcharging the pixel, thereby expanding the charge voltage difference between the left and right pixels. However, in the present invention, even when the thin film transistor is turned on due to the gate delay effect in the gate-off period by the counter electrode voltage as described above, by minimizing charge inflow, the difference in charge voltage between the left and right pixels of the liquid crystal panel can be significantly reduced. have.

3A and 3B, referring to the gate voltage and the counter electrode voltage obtained through the simulation, it can be seen that the gate voltage is delayed according to the position of the gate line. In FIG. 3A, V (PG1) is a voltage applied to the gate line closest to the gate driver, and V (PG9) is a voltage applied to the gate line furthest from the gate driver. That is, the higher the number, the farther it is from the gate driver. In FIG. 3A, these voltages are distinguished from each other by appropriate symbols. The waveform shown by the thick line in FIG. 3A and FIG. 3B is a counter electrode voltage. In the present embodiment, the pulse width of the counter electrode voltage is set to be equal to the delay period of the gate voltage, but the technical scope of the present invention is not limited thereto, and an optimum value can be selected within the range of one horizontal scanning period. .

Referring to FIG. 4A, it can be seen that the pixel voltage jumps in the turn-off period of the gate voltage due to the counter electrode voltage, thereby minimizing charge inflow even when the thin film transistor is turned on due to the gate delay effect. do. Referring to FIG. 4B, it can be seen that the voltage difference of the pixel voltage for each position on the liquid crystal panel is about 10 mV, which is a good level within a display interval (20 mV) of one gradation.

Next, a liquid crystal display according to a third exemplary embodiment of the present invention will be described with reference to FIGS. 5 and 6.

5A to 5C are waveform diagrams of gate and counter electrode voltages applied to the liquid crystal display according to the third exemplary embodiment of the present invention, and FIGS. 6A and 6B are obtained by simulation in the third exemplary embodiment of the present invention. The waveform diagram of the pixel voltage and the counter electrode voltage for each position on the liquid crystal panel is shown.

In the third embodiment of the present invention, a triangular wave is used as the counter electrode voltage.

In FIG. 5A, reference numeral 51 denotes a waveform of a gate voltage applied to the gate line closest to the gate driver, and 52 denotes a waveform of a gate voltage actually applied to the gate line furthest from the gate driver. Referring to FIG. 5B, the counter electrode voltage has a waveform in the form of a triangular wave at the time when the gate voltage falls from the on state to the off state, and the pulse width thereof is smaller than one horizontal scan period and greater than or equal to the signal delay time of the gate voltage. The amplitude is preferably 1V or less.

6A and 6B are waveforms obtained by simulation of pixel voltages for positions of liquid crystal panels when the triangular waves are used as counter electrode voltages. As shown in FIG. 6A, when the gate voltage drops from the on state to the off state, the pixel voltage jumps due to the opposite electrode voltage, which is a triangular wave. Accordingly, as shown in FIG. 6B, the pixel voltage difference between the left and right pixels of the liquid crystal panel is about 17 mV, which is considerably reduced compared with the conventional art.

Next, a liquid crystal display according to a fourth exemplary embodiment of the present invention will be described with reference to FIGS. 7 and 8.

In FIG. 7A, reference numeral 71 denotes a waveform of a gate voltage applied to the gate line closest to the gate driver, and 72 denotes a waveform of a gate voltage actually applied to the gate line furthest from the gate driver. Referring to FIG. 7B, the counter electrode voltage has a trapezoidal waveform at the time when the gate voltage falls from the on state to the off state, and the pulse width thereof is smaller than one horizontal scan period and greater than the signal delay time of the gate voltage. The amplitude is preferably 1 V or less.

8A and 8B are waveforms obtained by simulation of pixel voltages for respective positions of the liquid crystal panel when the trapezoidal wave is used as the counter electrode voltage. As shown in FIG. 8A, when the gate voltage drops from the on state to the off state, the pixel voltage jumps by the counter electrode voltage which is a trapezoidal wave. Accordingly, as shown in FIG. 8B, the pixel voltage difference between the left and right pixels of the liquid crystal panel becomes about 7 mV, which is considerably reduced compared with the conventional art. In this embodiment, when the trapezoidal wave is used as the counter electrode voltage, the pixel voltage difference is most greatly reduced. This means that the trapezoidal wave with nonlinear characteristics is most effective because the kickback voltage decreases nonlinearly due to signal delay in the gate line.

As described above, the liquid crystal display of the present invention reduces the difference in the amount of charge voltage between the left and right pixels of the liquid crystal panel by applying an opposite electrode voltage having a predetermined waveform at the time of turning off the gate voltage, The left and right pixels of the liquid crystal panel due to signal delays are effective in improving display quality differences, direct current stress (DC stress), and afterimage problems.

Claims (8)

A plurality of gate lines to which a gate voltage is applied, a plurality of data lines respectively crossing the plurality of gate lines, and a data voltage to which an image signal is applied, and a gate at a point where the gate lines and the data lines cross each other; A thin film transistor connected to a source line and a source connected to a corresponding data line, a pixel electrode connected to a drain of the thin film transistor, to which a data voltage is applied when the thin film transistor is turned on, and an opposite electrode forming a capacitance together with the pixel electrode. Having a liquid crystal panel; A gate driver for applying a gate voltage to the gate line to periodically turn on / off the thin film transistor; A source driver for applying a data voltage representing an image signal to the data line; A voltage generator configured to generate the gate voltage, the data voltage, and a voltage to be applied to the counter electrode, and to have a waveform of a voltage applied to the counter electrode when the gate voltage changes from an on state to an off state; And And a timing controller for adjusting the timing of the gate voltage and the data voltage to be used in the gate driver and the source driver. The method of claim 1, And a pulse width of the voltage applied to the counter electrode generated by the voltage generator is smaller than one horizontal scanning period and greater than or equal to the signal delay period of the gate voltage. The method of claim 1, The amplitude of the voltage applied to the counter electrode generated by the voltage generator is greater than 0V and less than 1V. The method of claim 1, The waveform of the voltage applied to the counter electrode is a pulse wave. The method of claim 1, And a waveform of the voltage applied to the counter electrode is a triangular wave. The method of claim 1, The waveform of the voltage applied to the counter electrode is a trapezoidal wave, characterized in that. The method according to any one of claims 1 to 6, And the counter electrode is a common electrode for forming a liquid crystal capacitance. The method according to any one of claims 1 to 6, And the counter electrode is a sustain electrode for forming a sustain capacitance.

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