KR100835683B1 - Analog-to-digital converters using digitally controlled comparators, including pacemakers, analog-to-digital converters using digitally controlled comparators - Google Patents

Abstract

An analog-to-digital converter using a digitally controlled comparator, a pacemaker including the same, and an analog-to-digital conversion method using a digitally controlled comparator are disclosed.

The present invention is designed for each voltage section that evenly divides the input section of the input voltage, a plurality of digital control comparator for generating a bit value sequentially from the most significant bit by comparing the input voltage and the other reference voltage for each voltage section A digital analog converter for generating a reference voltage applied to the plurality of digital control comparators according to the generated bit value, and a comparator for generating bit values of adjacent bits according to the generated bit value among the plurality of digital control comparators. Select and turn on to include the approximation logic circuit to perform binary search.

According to the present invention, by selecting and operating an appropriate digital control converter for each bit unit, low power consumption can be realized while maintaining reliability, and no additional circuit is required for low power implementation.

Description

Apparatus for converting analog to digital and pacemaking with digitally controlled comparator, Method for converting analog to digital with digitally controlled comparator }

1A is a block diagram of an analog-to-digital converter device of a sequential approximation logic circuit to which the present invention is applied.

1B and 1C illustrate an example of a binary search algorithm to which the present invention is applied.

2A to 2C illustrate an example of an input terminal of an analog-to-digital converter to which the present invention is applied.

3A is a flowchart of an algorithm of an analog-to-digital converter device of a sequential approximation logic circuit to which the present invention is applied.

3B illustrates an example in which the algorithm of FIG. 3A is applied.

4 is a block diagram of an analog-to-digital converter using a digitally controlled comparator according to an embodiment of the present invention.

5 is a block diagram of an analog digital conversion apparatus using a digitally controlled comparator according to another embodiment of the present invention.

6 is a block diagram of a pacemaker including an analog-to-digital converter using a digitally controlled comparator according to another embodiment of the present invention.

FIG. 7 illustrates an example of a comparator applied to FIGS. 4 to 6.

8A is a circuit diagram of the comparator shown in FIG. 7.

FIG. 8B illustrates an example of a signal applied to the Vactive terminal of FIG. 8A.

The present invention relates to an analog-to-digital converter, and more particularly, to an analog-to-digital converter using a digital control comparator, a pacemaker including the same, and an analog-to-digital conversion method using a digital-controlled comparator.

In battery-powered systems, the issue is to operate for a long time with constant power. Since power consumption is proportional to voltage, the supply voltage is gradually decreasing. When powered at very low voltages, the noise margin in the analog circuit is not reduced with the power supply. Therefore, as the power supply decreases, the range of the input voltage increases relatively. This causes the input to swing from Vdd to Vss, that is to say rail-to-rail.

In digital circuits, when the supply voltage is lowered, the threshold voltage is also lowered. Therefore, in analog circuits, it is important to secure a constant bias voltage at the bias stage. Therefore, a special technique is required to compensate for the low supply voltage. Accordingly, bootstrapping techniques and low-threshold techniques are currently used, but they all use additional circuits or additional devices, which are far from actual low power implementations.

In particular, the bootstrapping technique used in low voltage circuits is a technique that increases the bias voltage applied to the gate of the MOSFET more than the voltage that can be applied using an additional circuit. It is currently most commonly used as a low voltage technique, but it is more reliable than the voltage that can withstand the reduced oxide capacitance as the size of the device decreases, leading to oxide breakdown. ) Has a disadvantage.

In order to lower the threshold voltage of the MOSFET used in the bias stage, a MOSFET having a thick oxide may be used, but at a low voltage of less than 1V since it is only 200 mV smaller than the threshold voltage of a thin oxide MOSFET. It is difficult to use in a working circuit.

Therefore, the conventional analog-to-digital converter does not implement low power consumption while maintaining reliability, and there is a problem that it is not easy to lower the overall power consumption by requiring additional circuitry for low power implementation.

The first technical problem to be achieved by the present invention is to provide an analog-to-digital converter using a digital control comparator that can implement low power consumption while maintaining reliability, and does not require additional circuitry for low power implementation.

The second technical problem to be achieved by the present invention is to provide a pacemaker comprising an analog-to-digital converter using the digital control comparator described above.

The third technical problem to be achieved by the present invention is to provide an analog-to-digital conversion method using a digital control comparator applied to the analog-to-digital conversion device using the digital control comparator.

In order to achieve the above first technical problem, the present invention is designed for each voltage section that evenly divides the input section of the input voltage, and compares the reference voltage and the input voltage different for each voltage section sequentially from the most significant bit A plurality of digital control comparators for generating a value, a digital analog converter for generating a reference voltage applied to the plurality of digital control comparators in accordance with the generated bit values, and a plurality of digital control comparators adjacent in accordance with the generated bit values. The present invention provides an analog-to-digital converter using a digitally controlled comparator including a sequential approximation logic circuit that performs binary search while selecting and turning on a comparator for generating a bit value of a bit.

In addition, in order to achieve the first technical problem, the present invention is designed for each voltage section that evenly divides the input section of the input voltage, and compares the reference voltage and the input voltage for each voltage section from the most significant bit A plurality of digital control comparators for generating bit values sequentially, a digital analog converter for generating a reference voltage applied to the plurality of digital control comparators according to the generated bit values, and a bit value of the most significant bit is 1 and bits of the remaining bits Binary search while setting an input value of 0 as an initial input value of the digital-to-analog converter and selecting and turning on a comparator for generating bit values of adjacent bits according to the generated bit values among the plurality of digital control comparators. Digital control, including successive approximation logic circuit to perform the It provides an analog-to-digital conversion apparatus using a Gyoki.

In order to achieve the second technical problem, the present invention is a heart pacemaker comprising an analog to digital converter, the sensor unit for converting the heart rate into an analog input signal, the analog to digital conversion unit for converting the analog input signal into a digital signal And a stop watch for generating a reference clock at a predetermined cycle, and an electric shock unit for outputting an electrical stimulus according to the digital signal and the reference clock, wherein the analog-to-digital converter unit equally divides an input section of an input voltage. Designed for the purpose, a plurality of digital control comparator for generating a bit value sequentially from the most significant bit by comparing the reference voltage and the input voltage for each of the voltage interval, applied to the plurality of digital control comparator according to the generated bit value Digitally generated reference voltage A digital control comparator including a sequential approximation logic circuit for performing binary search while selecting and turning on a comparator for generating bit values of adjacent bits according to the generated bit value among analog converters and the plurality of digital control comparators; It provides a heart pacemaker comprising an analog-to-digital converter.

In order to achieve the third technical problem, the present invention uses a plurality of digital control comparator designed for each voltage section that evenly divides the input section of the input voltage by comparing the different reference voltage and the input voltage for each voltage section Generating bit values sequentially from the most significant bit, generating reference voltages applied to the plurality of digital control comparators according to the generated bit values, and adjacent to the generated bit values among the plurality of digital control comparators. An analog-to-digital conversion method using a digitally controlled comparator including performing a binary search while selecting and turning on a comparator for generating a bit value of a bit is provided.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-to-digital converter, that is, a device for converting an analog input signal into a digital signal and outputting the digital signal. In particular, the present invention relates to an analog-to-digital converter of Successive Approximation Resister (SAR).

The analog-to-digital converter converts an analog signal into a digital value by comparing it with internally divided reference voltages. The SAR analog-to-digital converter sets the most significant bit (MSB) to the least significant bit (LSB) through a binary search method.

Hereinafter, with reference to the drawings will be described a preferred embodiment of the present invention. However, embodiments of the present invention illustrated below may be modified in many different forms, and the scope of the present invention is not limited to the embodiments described below.

1A is a block diagram of an analog-to-digital converter device of a sequential approximation logic circuit to which the present invention is applied.

As shown in FIG. 1A, the analog-to-digital converter of the SAR method includes a comparator 110, a digital to analog converter (DAC) 120, and a successive approximation logic circuit 130. do.

The digital analog converter 120 converts a digital signal, which is a reference value for converting an analog input signal Vin into a digital signal, into an analog signal. The comparator 110 compares the analog input signal with the reference analog signal output from the digital analog converter 120 and outputs a comparison result. The successive approximation logic circuit 130 is composed of SAR control logic including a SAR register to control a digital signal which becomes a reference value in response to a comparison result output from the comparator 110.

1B and 1C illustrate an example of a binary search algorithm to which the present invention is applied.

The example of FIG. 1B shows an 8-bit analog-to-digital converter and a case where the analog input is 7.09 V. FIG. At this time, the least significant bit represents 39.22 mV. In this case, the SAR outputs one of two outputs according to whether the output of the comparator is TRUE or FALSE. The comparator outputs HIGH when the estimated current value is smaller than the input value, and outputs LOW when the estimated current value is greater than the input value.

That is, the SAR operates as follows. If the estimate is too small, one is subtracted from MSB- (n + 1), and if the estimate is too large, one is added from MSB- (n + 1). At this time, MSB is the most significant bit, n is the current clock cycle.

FIG. 1C is a table illustrating a process of estimating an input voltage up to an eighth cycle (n = 7) according to FIG. 1B. In FIG. 1C, it can be seen that the digital estimate of the input value converges between 180 and 181.

2A to 2C illustrate an example of an input terminal of an analog-to-digital converter to which the present invention is applied.

The N-bit SAR analog-to-digital converter (ADC) receives the analog input signal, distributes the reference voltage according to the N-bit digital code, compares it with the input signal, and compares the N-bit digital code corresponding to the input signal according to the comparison result. An analog-to-digital converter (ADC) that sequentially determines bit by bit.

Since the comparator is an analog circuit, the common-mode input range is limited due to the gate voltage securing problem of the bias stage. Because of this, other structures are used to receive rail-to-rail input.

The structure of the rail-to-rail operational amplifier of FIG. 2C is a combination of the N type input terminals (N input) and the input stages of the P type input terminals (P input) of FIGS. 2A and 2B. . However, at the ultra-low voltage operating voltage of 1V or less, since there are more than four MOSFET stacks in the load stage, the voltage swing at the output stage and sufficient overdrive voltage of each load MOSFETs are ensured. Is not easy.

3A is a flowchart of an algorithm of an analog-to-digital converter device of a sequential approximation logic circuit to which the present invention is applied.

First, the input voltage is sampled at V, and the variable i is initialized to 1 (step 310).

Next, if the voltage V is greater than 0 (step 320), the value obtained by dividing the reference voltage by 2 ^ i is subtracted from V, and the bit value of the i-th bit is determined as 1 (steps 331 and 341). On the contrary, if the voltage V is less than or equal to 0 (step 320), the value obtained by dividing the reference voltage by 2 ^ i is added to V, and the bit value of the i-th bit is determined to be 0 (steps 332 and 342).

Next, the variable i is increased by 1 (350).

At this time, if the variable i is greater than n, which is the number of bits of the analog-to-digital converter, the procedure ends. If the variable i is less than or equal to n, which is the number of bits of the analog-to-digital converter, the above process (steps 320-350) is performed. Repeat.

3B illustrates an example in which the algorithm of FIG. 3A is applied.

As you can see, we first determine whether the input is greater than or less than (Vdd-Vss) / 2 (the initial value of the DAC is set to '10000000' for 8 bits by the SAR register). ', If it is small, output' 0 '. If the previous value is '1' then it goes to half 3 (Vdd-Vss) / 4 of the upper part, and if it is '0', it goes to half- (Vdd-Vss) / 4 of the lower part. The value is compared with the input again to sequentially determine the binary code of the input value from the most significant bit (MSB) to the least significant bit (LSB).

By using this algorithm, it is possible to digitally control and use the comparator by dividing the comparator which was low voltage and it was impossible to design the rail-to-rail input. The comparator designed for each interval can be controlled by dividing the input common-mode interval of the comparator evenly from Vdd to Vss according to the values sequentially from the SAR register.

4 is a block diagram of an analog-to-digital converter using a digitally controlled comparator according to an embodiment of the present invention.

In FIG. 4, the four input sections are divided into four parts. In this case, assuming that Vdd is 1.5V and Vss is 0V, each of the four digital control comparators 411-414 has an input common-mode range of 0.375V from the top and the reference voltage is sequentially As appropriate, the digital control comparators 411-414 are selected accordingly. The reference voltage of the digital control comparator (411-414) is first set to '10000000' (8-bit) of the DAC output to generate a reference voltage corresponding to (Vdd-Vss) / 2. At this time, since the initial value of the MSB is fixed to 1 and the lower bit is fixed to 0, as shown in FIG. 4, the upper two bit values are read and the '10' digital control comparator 412 is selected first. Compare with a value. If the input value is the upper two bits corresponding to '11', then select '11' digital control comparator 411 with the highest input common-mode range and compare the next lower bits. Done. In FIG. 4, the digital control comparators 411-414 are selected using the upper two bits of the output of the successive approximation logic circuit 430.

5 is a block diagram of an analog digital conversion apparatus using a digitally controlled comparator according to another embodiment of the present invention.

The plurality of digital control comparators 511-519 are designed for each voltage section that evenly divides the input section of the input voltage, and generate bit values sequentially from the most significant bit by comparing different reference voltages and input voltages for each voltage section. do.

Preferably, the plurality of digital control comparators 511-519 may have a structure of a rail-to-rail OP amplifier in which an N type input terminal and a P type input terminal are combined into one stage. Preferably, the plurality of digitally controlled comparators 511-519 may be designed to be off so that comparators not selected by the sequential approximation logic circuit 530 are turned off. Preferably, the plurality of digital control comparators 511-519 may limit the input voltage to a positive voltage. Preferably, the plurality of digitally controlled comparators 511-519 has a switch between the comparator and a constant current source, and can be designed to turn on or off the switch according to the comparator selection signal of the sequential approximation logic circuit 530. .

The digital-to-analog converter 520 generates a reference voltage applied to the plurality of digital control comparators according to the generated bit value. In this case, the input of the digital-to-analog converter 520 includes at least a part of the output of the successive approximation logic circuit 530.

The successive approximation logic circuit 530 performs binary search while selecting and turning on a comparator for generating a bit value of an adjacent bit (next bit) according to the generated bit value among the plurality of digital control comparators 511-519. Preferably, the successive approximation logic circuit 530 may be designed to select a comparator according to the size of the bit value of the most significant two bits among the plurality of digital control comparators 511-519.

6 is a block diagram of a pacemaker including an analog-to-digital converter using a digitally controlled comparator according to another embodiment of the present invention.

Analog-to-digital converter 610 is an analog-to-digital converter using a digital control comparator according to the present invention, converts the analog input signal into a digital signal. The output signal of the analog-digital converter 610 may be composed of a plurality of bits and transmitted in parallel. Preferably, the analog input terminal of the analog to digital converter 610 may be connected to the sensor unit 600 for detecting a heartbeat.

The stop watch 640 generates a reference clock at predetermined periods. The reference clock is a clock to provide a reference for the human heartbeat cycle.

The electric shock unit 650 outputs an electrical stimulus according to the digital signal of the analog-digital converter 610 and the reference clock of the stopwatch 640. At this time, the electrical stimulation is an electrical signal for pacing, has a small voltage and a small current of harmless levels to the human body.

Preferably, the electric shock unit 650 includes a means for comparing the digital signal of the analog-digital converter 610 and the reference clock of the stopwatch 640, and the period of the digital signal of the analog-digital converter 610. May be configured to output an electrical stimulus when the signal becomes slower than the reference clock of the stop watch 640.

FIG. 7 illustrates an example of a comparator applied to FIGS. 4 to 6.

As shown in FIG. 7, the comparators may be designed to be turned off after the moment of comparison and to be turned off in a non-operating section by switching a lower end of the constant current source.

8A is a circuit diagram of the comparator shown in FIG. 7.

The comparator shown in FIG. 8A has a structure similar to a conventional differential amplifier, but has a bias stage Vbias and a switch stage Vactive for low power implementation. That is, when the comparator is turned on according to the comparator selection signal of the successive approximation logic circuit, when a voltage equal to or greater than the threshold voltage of the MOSFET is applied to the Vactive stage, and the comparator is turned off according to the comparator selection signal of the successive approximation logic circuit. The Vactive stage can be designed to apply a voltage or ground voltage below the threshold voltage of the MOSFET.

FIG. 8B illustrates an example of a signal applied to the Vactive terminal of FIG. 8A. The signal applied to the Vactive terminal may be a periodic signal as shown in FIG. 8B.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary and will be understood by those of ordinary skill in the art that various modifications and variations can be made therefrom. However, such modifications should be considered to be within the technical protection scope of the present invention. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the present invention, by selecting and operating an appropriate digital control converter for each bit unit, low power consumption can be realized while maintaining reliability, and an additional circuit is not required for low power implementation.

Claims (11)

A plurality of digital control comparators designed for each voltage section equally dividing an input section of an input voltage, and generating bit values sequentially from the most significant bit by comparing the input voltage with another reference voltage for each voltage section; A digital analog converter for generating a reference voltage applied to the plurality of digital control comparators according to the generated bit value; And A sequential approximation logic circuit for performing binary search while selecting and turning on a comparator for generating bit values of adjacent bits according to the generated bit values among the plurality of digital control comparators; The plurality of digital control comparator, Analog-to-digital converter using a digitally controlled comparator, characterized in that the structure of a rail-to-rail op amp combining the N type input terminal and the P type input terminal into one stage. A plurality of digital control comparators designed for each voltage section equally dividing an input section of an input voltage, and generating bit values sequentially from the most significant bit by comparing the input voltage with another reference voltage for each voltage section; A digital analog converter for generating a reference voltage applied to the plurality of digital control comparators according to the generated bit value; And A sequential approximation logic circuit for performing binary search while selecting and turning on a comparator for generating bit values of adjacent bits according to the generated bit values among the plurality of digital control comparators; The plurality of digital control comparator, And a comparator not selected by the successive approximation logic circuit is turned off. A plurality of digital control comparators designed for each voltage section equally dividing an input section of an input voltage, and generating bit values sequentially from the most significant bit by comparing the input voltage with another reference voltage for each voltage section; A digital analog converter for generating a reference voltage applied to the plurality of digital control comparators according to the generated bit value; And A sequential approximation logic circuit for performing binary search while selecting and turning on a comparator for generating bit values of adjacent bits according to the generated bit values among the plurality of digital control comparators; The plurality of digital control comparator, And an analog-to-digital converter using a digitally controlled comparator, wherein the input voltage is limited to a positive voltage. The method of claim 3, wherein The plurality of digitally controlled comparator And a switch between the comparator and the constant current source, and switching the switch on or off in accordance with the comparator selection signal of the successive approximation logic circuit. A plurality of digital control comparators designed for each voltage section equally dividing an input section of an input voltage, and generating bit values sequentially from the most significant bit by comparing the input voltage with another reference voltage for each voltage section; A digital analog converter for generating a reference voltage applied to the plurality of digital control comparators according to the generated bit value; And A sequential approximation logic circuit for performing binary search while selecting and turning on a comparator for generating bit values of adjacent bits according to the generated bit values among the plurality of digital control comparators; The successive approximation logic circuit, And a comparator is selected from among the plurality of digital control comparators according to the magnitude of the bit value of the most significant two bits. The logic of any one of claims 1 to 5, wherein the successive approximation logic circuit, And an input value having a bit value of the most significant bit of 1 and a bit value of the remaining bits of 0 as an initial input value of the digital-to-analog converter. A pacemaker comprising an analog to digital converter, A sensor unit for converting a heartbeat into an analog input signal; An analog-digital converter for converting the analog input signal into a digital signal; A stop watch generating a reference clock at a predetermined period; And An electric shock unit configured to output an electrical stimulus according to the digital signal and the reference clock, The analog to digital converter, A plurality of digital control comparators designed for each voltage section equally dividing an input section of an input voltage, and generating bit values sequentially from the most significant bit by comparing the input voltage with another reference voltage for each voltage section; A digital analog converter for generating a reference voltage applied to the plurality of digital control comparators according to the generated bit value; And A sequential approximation logic circuit for performing binary search while selecting and turning on a comparator for generating bit values of adjacent bits according to the generated bit values among the plurality of digital control comparators; The plurality of digital control comparator, And an analog-to-digital converter using a digitally controlled comparator, comprising a switch between a comparator and a constant current source, the switch being turned on or off in accordance with a comparator selection signal of the successive approximation logic circuit. A pacemaker comprising an analog to digital converter, A sensor unit for converting a heartbeat into an analog input signal; An analog-digital converter for converting the analog input signal into a digital signal; A stop watch generating a reference clock at a predetermined period; And An electric shock unit configured to output an electrical stimulus according to the digital signal and the reference clock, The analog to digital converter, A plurality of digital control comparators designed for each voltage section equally dividing an input section of an input voltage, and generating bit values sequentially from the most significant bit by comparing the input voltage with another reference voltage for each voltage section; A digital analog converter for generating a reference voltage applied to the plurality of digital control comparators according to the generated bit value; And A sequential approximation logic circuit for performing binary search while selecting and turning on a comparator for generating bit values of adjacent bits according to the generated bit values among the plurality of digital control comparators; The successive approximation logic circuit, And an analog-to-digital converter using a digitally controlled comparator, wherein the comparator is selected from among the plurality of digitally controlled comparators according to the magnitude of the bit value of the most significant two bits. Generating bit values sequentially from the most significant bit by comparing the input voltage with different reference voltages for each of the voltage sections using a plurality of digitally controlled comparators designed for each voltage section that equally divides the input section of the input voltage; Generating a reference voltage applied to the plurality of digitally controlled comparators according to the generated bit value; And Performing binary search while selecting and turning on a comparator for generating a bit value of an adjacent bit according to the generated bit value among the plurality of digital control comparators; The plurality of digital control comparator is an analog-to-digital conversion method using a digital control comparator, characterized in that the structure of the rail-to-rail OP amplifier combining the N type input terminal and the P type input terminal in one stage. Generating bit values sequentially from the most significant bit by comparing the input voltage with different reference voltages for each of the voltage sections using a plurality of digitally controlled comparators designed for each voltage section that equally divides the input section of the input voltage; Generating a reference voltage applied to the plurality of digitally controlled comparators according to the generated bit value; And Performing binary search while selecting and turning on a comparator for generating a bit value of an adjacent bit according to the generated bit value among the plurality of digital control comparators; And the plurality of digitally controlled comparators limit the input voltage to a positive voltage. Generating a bit value sequentially from the most significant bit by comparing the input voltage with different reference voltages for each of the voltage sections using a plurality of digitally controlled comparators designed for each voltage section that equally divides the input section of the input voltage; Generating a reference voltage applied to the plurality of digitally controlled comparators according to the generated bit value; And Performing binary search while selecting and turning on a comparator for generating a bit value of an adjacent bit according to the generated bit value among the plurality of digital control comparators; The performing of the binary search comprises selecting a comparator according to the size of the bit value of the most significant two bits from the plurality of digital control comparators.

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