KR100832022B1 - Method of forming contact plug of semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can reduce the step difference generated during the storage node contact plug process due to dishing during the etch back or chemical mechanical polishing process, the manufacturing method of the semiconductor device of the present invention Forming an insulating film on the substrate; Etching the insulating film to form a contact hole; Forming a contact plug material on the front surface until filling the inside of the contact hole; Etching the contact plug material through at least an etch back to form a first contact plug inside the contact hole; And forming a second contact plug on the first contact plug using a selective epitaxial growth method (SEG) having the same surface as the surface of the insulating film. By forming the contact plug additionally, there is an effect of reducing the step or dish caused by etch back or chemical mechanical polishing during the contact plug process such as the landing plug and the storage node contact plug.

Description

Method of forming contact plug of semiconductor device {METHOD FOR FABRICATING CONTACT PLUG IN SEMICONDUCTOR DEVICE}

1A and 1B schematically illustrate a method of forming a storage node contact plug according to the prior art;

Figure 2a is a simplified view showing a landing plug forming method according to the prior art.

Figure 2b is a photograph showing the dishing after forming the landing plug according to the prior art.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

4A through 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 substrate 32 insulating film

34A: 1st contact plug 35: 2nd contact plug

36 etch stop nitride film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for reducing a step caused by topology or dishing.

During the DRAM device manufacturing process, during the plug process embedded in the contact hole such as the landing plug and the storage node contact plug, the conductive film is deposited and etched back in order. The process proceeds in the order of film deposition, etch back and chemical mechanical polishing (CMP).

1A and 1B are views illustrating a method of forming a storage node contact plug according to the prior art, and FIG. 2A is a view illustrating a method of forming a landing plug according to the prior art.

First, referring to FIGS. 1A and 1B, after the storage node contact hole is formed in the interlayer oxide layer 11, the storage node contact plug 12 is formed by polysilicon deposition and etching. Subsequently, after the etch stop layer 13 is formed on the entire surface, the storage node isolation layer 14 is formed on the etch stop layer 13. Subsequently, the storage node isolation layer 14 is etched and the etch stop nitride layer 13 is etched to form an open region 15 in which the storage node is to be formed.

The prior art as described above forms an etch stop layer 13 to prevent etching of the lower interlayer oxide layer 11 when etching the open region 15 in which the storage node SN is to be formed.

However, in the related art, the top of the storage node contact plug 12 and the storage may be formed due to the global topology generated when the storage node contact plug 12 is formed by the storage node contact hole formation, polysilicon deposition, and the etch back process. Since the thickness of the etch stop layer 13 deposited on the interlayer oxide layer 11 around the node contact plug 12 is changed, loss of the etch stop layer 13 is inevitable when the open region 15 is etched.

Referring to FIG. 1A, when sufficient etching of the etch stop layer 13 is performed for connection with the storage node contact plug 12, an etch stop formed on the interlayer oxide layer 11 around the storage node contact plug 12 is formed. Since the nitride film 13 is etched and the lower interlayer oxide film 11 is etched, a punch is generated.

When the etch stop layer 13 is etched to prevent the punch phenomenon, as shown in FIG. 1B, it is difficult to form the open area 15 for connection with the storage node contact plug 12. This decreases. That is, since the etch stop nitride film 13 is not completely etched, the bottom of the open area 15 is not opened.

As described above, the not-open and punch-out phenomenon of the etch stop layer is caused by a topology step after the storage node contact plug is formed, resulting in an uneven thickness of the etch stop layer.

Referring to FIG. 2A, the gate line 22 is formed on the substrate 21, and the etch stop layer 23 and the interlayer insulating layer 24 are formed. Subsequently, contact holes are formed through etching the interlayer insulating layer 24 and etching stop layer 23, and the landing plug 25 is sequentially formed by sequentially depositing polysilicon, etching back, and chemical mechanical polishing.

In the formation of the landing plug 25 of FIG. 2A, dishing after chemical mechanical polishing is unavoidable, and such dishing causes a step between the surface of the landing plug 25 and its surrounding structure. Here, dishing is caused by the selectivity between the films to be polished.

The deeper the formation of dishing, the more uneven the topography of the surface, making the patterning process for subsequent bit line contact formation difficult. In addition, excessive cleaning must be performed to remove Pinocchio defects present on the surface by dishing. At this time, the loss of the interlayer insulating film is increased, thereby increasing the degree of dishing and eliminating the step by dishing. In order to solve this problem, further polishing occurs.

Figure 2b is a photograph showing the dishing after forming the landing plug according to the prior art.

The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce the step difference generated during the storage node contact plug process by etch back.

In addition, another object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce the step difference caused by dishing during the chemical mechanical polishing process.

Method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming an insulating film on the substrate; Etching the insulating film to form a contact hole; Forming a contact plug material on the front surface until filling the inside of the contact hole; Etching the contact plug material through at least an etch back to form a first contact plug inside the contact hole; And forming a second contact plug on the first contact plug using a selective epitaxial growth method (SEG), the second contact plug having the same surface as the surface of the insulating film. And forming a polysilicon film as a contact plug material and then etching back, wherein the first contact plug is formed by sequentially performing etch back and chemical mechanical polishing after forming the polysilicon film as the contact plug material. It features.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

The embodiments described below are methods for reducing the step by chemical mechanical polishing (CMP) or etch back.

In the first embodiment, the thickness of the etch stop nitride film is made uniform by reducing the step difference in the front topology generated when the storage node contact plug is formed, thereby preventing the punch phenomenon and the open defect of the etch stop nitride film.

The etch stop nitride film is deposited along the topology of the bottom, and is relaxed by transferring the curvature of the bottom to the top, so that the etch stop nitride film on the storage node contact plug is deposited thicker. Therefore, if the step difference between the storage node contact plug and the etch stop nitride film is reduced, the probability of forming a punch is lowered and the etching margin is increased.

The second embodiment reduces the step by dishing generated after chemical mechanical polishing.

In both the first and second embodiments, the contact plug is further formed by selective epitaxial growth (SEG) to reduce the step, so that the subsequent process can be stably performed.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

As shown in FIG. 3A, after forming the interlayer oxide layer 32 on the substrate 31, the interlayer oxide layer 32 is etched to form the storage node contact hole 33. At this time, although not shown, as is well known before the interlayer oxide film 32 is formed, a word line, a landing plug, a bit line, or the like may be formed. Thus, the substrate 31 may be a landing plug or a source / drain junction, the landing plug is polysilicon, and the source / drain junction is silicon doped with impurities.

Subsequently, the first polysilicon layer 34 is deposited on the entire surface until the storage node contact hole 33 is filled. In this case, the first polysilicon layer 34 is deposited using chemical vapor deposition (CVD) using SiH ₄ as a silicon source. Here, the silicon source may use a known source gas in addition to SiH ₄ .

As shown in FIG. 3B, the first polysilicon layer 34 is etched through an etchback to form a first contact plug 34A that fills the inside of the storage node contact hole 33. .

As described above, a step is generated between the first contact plug 34A and the surface of the interlayer oxide film 32 around it by the deposition and etch back of the first polysilicon film 34.

In the first embodiment, the contact plug material is re-formed on the first contact plug 34A to reduce the above step difference.

As shown in FIG. 3C, the polysilicon layer 35 is selectively grown on the surface of the first contact plug 34A through selective epitaxial growth (SEG). At this time, the thickness of the second polysilicon film 35 is preferably a thickness that reduces the step by filling the upper portion of the first contact plug 34A. That is, the second polysilicon film 35 is grown by the surface height of the interlayer oxide film.

Selective epitaxial growth of the second polysilicon film 35 uses the following two methods depending on gas, deposition temperature and pressure.

In the first method, the reaction material uses a mixture of SiH ₂ Cl ₂ / PH ₃ / HCl, and selectively grows the second polysilicon film at a pressure in the deposition chamber of 90 to 150 torr. The SiH ₂ Cl ₂ gas is a silicon source gas and the PH ₃ gas is a doping gas for doping phosphorus (Phosphorous, P), and the HCl gas is a cleaning gas for removing reaction byproducts. In the case of applying the first method, the deposition temperature is a high temperature of 700 to 950 ° C.

As a second method, the reaction material uses a mixture of SiH ₄ / PH ₃ / H ₂ and selectively grows the second polysilicon film with a pressure in the deposition chamber of 120 to 200 torr. SiH ₄ gas is a silicon source gas and PH ₃ gas is a doping gas for doping phosphorus (Phosphorous, P), and H ₂ gas is a cleaning gas for removing reaction byproducts. In the second method, the deposition temperature is 550 to 700 ° C., which is lower than the deposition temperature in the first method.

According to the first method and the second method as described above, PH ₃ gas is used as a doping gas for doping phosphorus which is an impurity. Thus, phosphorus (P) as an impurity is in situ in the second polysilicon film 35. Doped with (In-situ).

Meanwhile, the surface of the first contact plug 34A, which is a surface on which the second polysilicon film 35 is grown through selective epitaxial growth, is impurity for growth of the high quality second polysilicon film 35. Should be removed. To this end, the present invention proceeds with a cleaning process to remove impurities on the surface of the first contact plug 34A before selective epitaxial growth, wherein the cleaning process uses plasma etching using a mixture of N ₂ gas and H ₂ gas. .

By growing the second polysilicon film 35 as described above, the step difference between the first contact plug 34A and the interlayer oxide film 32 is removed. In addition, since the second polysilicon film 35 functions as a storage node contact plug together with the first contact plug 34A, the second polysilicon film 35 is hereinafter abbreviated as a 'second contact plug 35'. .

As a result, the storage node contact plug 100 including the first contact plug 34A and the second contact plug 35 is formed.

As shown in FIG. 3D, an etch stop nitride film 36 is formed on the entire surface of the structure in which the second contact plug 35 is formed. At this time, the etch stop nitride film 36 has a uniform thickness on the entire surface of the substructure because the substructure before formation has no step. Therefore, open defects and punches do not occur during an etching process for forming a subsequent open area.

Subsequently, the storage node isolation layer 37 is formed on the etch stop nitride layer 36. In this case, the storage node isolation layer 37 is for isolation and insulation between neighboring storage nodes, and is formed of an oxide layer material such as PSG and PETOS.

Subsequently, etching is performed to form an open area in which the storage node is to be formed. For example, the storage node separation layer 37 may be etched to stop the etching in the etch stop nitride layer 36, and the open region 28 that opens the surface of the second contact plug 35 by sequentially etching the etch stop nitride layer 36. ). In this case, the open area 38 is overlaid in a planar structure as shown in FIG. 1 so that the storage node SN and the storage node contact plug SNC are optimized in the wafer.

As shown in FIG. 3E, the conductive layer is deposited and etched to be used as the storage node to form the storage node 39 of the capacitor in the open area 38.

Although not shown, a dielectric film and a plate are formed in a subsequent process.

4A through 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

As shown in FIG. 4A, after the gate line 42 is formed on the substrate 41, an etch stop nitride film 43 is formed on the entire surface. In this case, the gate line 42 may have a stacked structure in order of a gate oxide film, a gate electrode, and a hard mask nitride film. In addition, the etch stop nitride layer 43 serves as an etch stop to prevent the upper portion of the gate line from being etched when the interlayer oxide layer 34 for subsequent contact hole formation is etched.

Subsequently, after the interlayer oxide layer 44 is formed on the entire surface, the interlayer oxide layer 44 and the etch stop nitride layer 43 are sequentially etched to expose the contact hole 45 exposing the surface of the substrate 41 between the gate lines 42. ). In this case, the substrate 41 exposed by the contact hole 45 may be a source / drain junction, and the source / drain junction is silicon doped with impurities.

As described above, the etching process for forming the contact hole 45 is referred to as landing plug contact etching, and the landing plug contact etching is based on the self aligned contact (SAC) method, and the upper portion of the neighboring gate line is applied. Are all exposed.

As shown in FIG. 4B, the first polysilicon film 46 is deposited on the entire surface until the contact hole 45 is filled. In this case, the first polysilicon layer 46 is deposited using chemical vapor deposition (CVD) using SiH ₄ as a silicon source. Here, the silicon source may use a known source gas in addition to SiH ₄ .

As shown in FIG. 4C, the etch back and chemical mechanical polishing (CMP) are sequentially performed with respect to the first polysilicon film 46 to planarize the first polysilicon film 46, thereby reducing the contact hole 45. A first contact plug 46A is formed to fill the inside. Here, in the chemical mechanical polishing process, the interlayer oxide film 44 is also polished at the same time.

As described above, a step due to dishing occurs between the surface of the first contact plug 46A and the structure (here, the etch stop nitride film on the upper gate line) by chemical mechanical polishing of the first polysilicon film 46. do. Such dishing is caused by the difference in selectivity between the films to be polished.

The second embodiment re-forms the contact plug material on the first contact plug 46A to reduce the step difference caused by dishing.

As shown in FIG. 4D, the second polysilicon layer 47 is selectively grown on the surface of the first contact plug 46A through selective epitaxial growth (SEG). At this time, the thickness of the second polysilicon film 47 is preferably a thickness to reduce the step by filling the upper portion of the first contact plug 46A to remove the dishing. That is, the second polysilicon film 47 is grown by the surface height of the etch stop nitride film 43 on the gate line 42.

Selective epitaxial growth of the second polysilicon film 47 uses the following two methods depending on the gas, deposition temperature and pressure.

In the first method, the reaction material uses a mixture of SiH ₂ Cl ₂ / PH ₃ / HCl, and selectively grows the second polysilicon film 47 at a pressure in the deposition chamber of 90 to 150 torr. SiH ₂ Cl ₂ gas is a silicon source gas and PH ₃ gas is a doping gas for doping phosphorus (Phosphorous, P), and HCl gas is a cleaning gas for removing reaction byproducts. In the case of applying the first method, the deposition temperature is a high temperature of 700 to 950 ° C.

As a second method, the reaction material uses a mixture of SiH ₄ / PH ₃ / H ₂ , and selectively grows the second polysilicon film 47 at a pressure in the deposition chamber of 120 to 200 torr. SiH ₄ gas is a silicon source gas and PH ₃ gas is a doping gas for doping phosphorus (Phosphorous, P), and H ₂ gas is a cleaning gas for removing reaction byproducts. In the second method, the deposition temperature is 550 to 700 ° C., which is lower than the deposition temperature in the first method.

According to the first method and the second method as described above, PH ₃ gas is used as a doping gas for doping phosphorus which is an impurity. Thus, phosphorus (P) as an impurity is in situ in the second polysilicon film 47. Doped with (In-situ).

On the other hand, the surface of the first contact plug 46A, which is the surface on which the second polysilicon film 47 is grown through selective epitaxial growth, is impurity for growth of the high quality second polysilicon film 47. Should be removed. To this end, the second embodiment performs a cleaning process to remove impurities on the surface of the first contact plug 46A before the selective epitaxial growth, wherein the cleaning process is plasma etching using a mixture of N ₂ gas and H ₂ gas. Use

By the growth of the second polysilicon film 47 described above, the step with the peripheral structure due to dishing on the first contact plug 46A is removed. In addition, since the second polysilicon film 47 acts as a landing plug together with the first contact plug 46A, the second polysilicon film 47 is hereinafter abbreviated as a 'second contact plug 47'.

As a result, the landing plug 200 including the first contact plug 46A and the second contact plug 47 is formed. And, as is well known, since the landing plug 200 is formed not only in the cell region but also in the peripheral circuit region, the landing plug 200 can form a landing plug in which the step is removed in the peripheral circuit region, thereby polishing both the cell region and the peripheral circuit region. Uniformity can be secured.

According to the second embodiment, the polysilicon film is further grown through the selective epitaxial growth method as the second contact plug, thereby eliminating dishing by the polishing selectivity between the landing plug and the insulating film around the landing plug.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention described above can form contact plugs by the selective epitaxial growth method, thereby reducing step or dishing caused by etch back or chemical mechanical polishing during contact plug processes such as landing plugs and storage node contact plugs. It has an effect.

Claims (11)

delete Forming an insulating film on the substrate; Etching the insulating film to form a contact hole; Forming a contact plug material on the front surface until filling the inside of the contact hole; Etching the contact plug material through at least an etch back to form a first contact plug inside the contact hole; And Forming a second contact plug on the first contact plug using a selective epitaxial growth method (SEG) having the same surface as the surface of the insulating film; Method for manufacturing a semiconductor device comprising a. The method of claim 2, The method for manufacturing a semiconductor device, wherein the second contact plug by the selective epitaxial growth method is a polysilicon film. The method of claim 3, Selective epitaxial growth of the polysilicon film, A method of manufacturing a semiconductor device in which a mixture of SiH ₂ Cl ₂ / PH ₃ / HCl is used as a reactant and the pressure in the deposition chamber is set to 90 to 150 torr. The method of claim 4, wherein In the selective epitaxial growth of the polysilicon film, the deposition temperature is 700 ~ 950 ℃ manufacturing method of a semiconductor device. The method of claim 3, Selective epitaxial growth of the polysilicon film, A method of manufacturing a semiconductor device in which a mixture of SiH ₄ / PH ₃ / H ₂ is used as a reactant and the pressure in the deposition chamber is set to 120 to 200 torr. The method of claim 6, In the selective epitaxial growth of the polysilicon film, the deposition temperature is in the range of 550 ~ 700 ℃ manufacturing method of a semiconductor device. The method of claim 2, The first contact plug, And forming a polysilicon film as the contact plug material and then etching back to form the polysilicon film. The method of claim 2, The first contact plug, And forming a polysilicon film as the contact plug material and then sequentially performing etch back and chemical mechanical polishing. The method according to any one of claims 2 to 9, The insulating film, A method of manufacturing a semiconductor device which is an oxide film or a nitride film. The method according to any one of claims 2 to 9, The first and second contact plugs are a landing plug or a storage node contact plug.

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