KR100828196B1 - Soft Program and Soft Program Verification of Core Cells in Flash Memory Arrays - Google Patents

Abstract

A method 900 and a system 400 are disclosed for adjusting or correcting a threshold voltage between a target minimum 380 and a maximum 390 for memory cell soft program and soft program verification, a dual bit memory cell structure. Can be employed in connection with 50. The method 900 includes applying one reference voltage signal 455 to the transient erase core cell and the reference cell 480, comparing the two currents 475 generated by each, and the cell 405. Selectively verifying the appropriateness of soft programming of one or more bits of s) (485, 435) and determining (950) whether the dual bit memory cell is properly soft programmed. The method may also include selectively soft programming 965 at least one or more bits 980 of the cell, and then selectively revalidating 950, 955 as appropriate to soft programming of the cell.

Description

SOFT PROGRAM AND SOFT PROGRAM VERIFY OF THE CORE CELLS IN FLASH MEMORY ARRAY

FIELD OF THE INVENTION The present invention relates generally to memory systems, in particular by the new reference cell structure (and the application of inherent reference voltages during soft program and soft program verify operations), bringing the reference cell to a low threshold voltage. A flash memory system and method that eliminates the previous problems of trimming, control the erase core cell threshold voltage distribution, thereby also promoting fast programming time.

EP-A-0 953 985 discloses a nonvolatile flash EEPROM memory device. This memory device has a reference cell with a predetermined, accurate threshold voltage. This threshold is the upper limit of the threshold voltage for erasing the memory cells. Flash EEPROM includes erase check, program check and transient erase check. The transient erase check needs to check that the memory cell threshold voltage after erasing is higher than the lower limit (transient check level).
WO-A-99 / 60631 discloses a nitride programmable read only memory (NROM) cell with improved programming, erasing and periods.
Flash memory is a type of electrical memory medium that can be rewritten and retain its data without power. Flash memory devices typically have a lifespan of write cycles from 100K to 1MEG. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) chips that can erase a single byte, flash memory is typically a fixed multi-bit block or sector. Are erased and written in units of. Advancing from properly erasable electrically erasable and programmable read only memory (EEPROM) chip technology, flash memories are cheaper and more dense. This new class of EEPROMs has emerged as an important nonvolatile memory that combines the benefits of EPROM density with the possibility of EEPROM electrical erasure.

Conventional flash memories, for example, have a cell structure in which a single bit of information is stored in each cell, as indicated by reference numeral 10 of the prior art FIG. In such a single bit memory structure, each cell 10 has a source 12, a drain 14, and a channel 16 on a substrate or P well 18, and also has a stacked gate structure (covered over the channel 16). Metal oxide semiconductor (MOS) transistor structures having 20). The stacked gate 20 may further include a thin gate dielectric layer 22 (sometimes referred to as tunnel oxide) formed on the surface of the P well. The stacked gate 20 also includes a polysilicon floating gate 24 overlying the tunnel oxide 22 and an interpoly dielectric layer 26 overlying the floating gate. Interpoly dielectric layer 26 is often composed of a multi-layered insulator, such as an oxide-nitride-oxide (ONO) layer sandwiched between two oxide layers. Finally, a polysilicon control gate 28 is covered over the interpoly dielectric layer 26.

This control gate 28 is connected to a wordline associated with a row of cells, forming sectors of those cells within a typical NOR structure. In addition, the drain regions 14 of the cells are connected together by conductive bit lines. The channel 16 of the cell conducts current between the source 12 and the drain 14 in accordance with an electric field developed in the channel 16 by the stacked gate structure 20. In the NOR structure, each drain terminal 14 of transistors in one column is connected to the same bit line. Further, each flash cell associated with a given bit line has stacked gate terminals 28 connected to different word lines, while the source terminals 12 of all flash cells of the array are connected to a common source terminal. In operation, individual flash cells are addressed through respective bit lines and word lines using peripheral decoders and control circuitry (not shown) for programming (write), read or erase functions.

This conventional single bit stacked gate flash memory cell 10 is programmed by applying a relatively high voltage to the control gate 28 and connecting the source 12 to ground and the drain 14 to a predetermined potential greater than the source. do. The resulting high electric field across the tunnel oxide 22 results in a phenomenon called "Fowler-Nordheim" tunneling. During this process, electrons in the core cell channel region 16 tunnel through the gate or tunnel oxide 22 into the floating gate 24, which is trapped at the floating gate, which causes the floating gate to be interpoly dielectric. This is because it is surrounded by 26 and tunnel oxide 22. As a result of the trapping of the electrons, the threshold voltage of the cell 10 increases. The change in the cell's threshold voltage (and thus the channel conductance) generated by these trapped electrons causes the cell to be programmed.

In order to erase the conventional single bit stacked gate flash memory cell 10, a relatively high voltage is applied to the source 12, the control gate 28 is maintained at a negative potential, and the drain 14 is floated. do. Under these conditions, a strong electric field develops in the tunnel oxide 22 between the floating gate 24 and the source 12. The electrons trapped in the floating gate 24 flow toward the portion of the floating gate covered over the source region 12 and are dense therein, and are extracted from the floating gate to form the source region by Fowler Nordheim tunneling through the tunnel oxide 22. 12). As the electrons are removed from the floating gate 24, the cell 10 is erased.

In a conventional single bit flash memory device, erase verification is performed to determine whether each cell or set of such cells in a block has been properly erased. Current single bit erase verify methods provide verification of bit or cell erase and application of supplemental erase pulses to individual cells that have failed initial verification. Thereafter, the erased state of the cell is verified again, and the process continues until the cell or bit is successfully erased or the cell is determined to be unusable.

After erase, some cells may be over erased, causing excessively low threshold voltages and correspondingly high drain current leakage, which may cause problems with subsequent read, program verify, or even erase operations. The process of soft programming has typically been adopted as a means of correcting over erased cells. This process generally involves applying one or more program pulses to the transient erase cell. The soft program process raises (or corrects) the low threshold voltage of the identified cells, effectively narrowing the distribution of erase cell threshold voltages across the flash memory array.
Recently, dual bit flash memory cells have been introduced that can store two bits of information in a single memory. 1B illustrates an exemplary prior art dual bit memory cell 50. The memory cell 50 includes a silicon dioxide layer 52, and the P-type substrate 54 has buried N + source 56 and N + drain 58 regions. Silicon dioxide 52 is located between two silicon nitride layers 60 and 62. Alternatively, this layer 52 may include buried polysilicon islands or any other type of charge trapping layer.

The polysilicon gate 64 is covered over the nitride layer 60. This gate 64 is doped with N-type impurities (for example, phosphorus). The memory cell 50 may store two data bits, a left bit indicated by a dotted circle A and a right bit indicated by a dotted circle B. FIG. Since the dual bit memory cell 50 is generally symmetrical, the drain 58 and the source 56 are interchangeable. Thus, with respect to the right bit B, the left junction 56 can function as a source terminal, and the right junction 58 can function as a drain terminal. Similarly, with respect to left bit A, the right junction 58 can function as a source terminal, and the left junction 56 can function as a drain terminal.

After erasing the dual bit cell, the conventional soft programming and soft program verification methods employed in single bit stacked gate structures may be applied to such dual bit devices in certain circumstances, but the end of the erase distribution V _T may be zero. There's still a problem because it's at 0.7 volts. Accordingly, there is a need for a new and improved soft programming and soft program verification method and system that can ensure proper control of the erase cell threshold voltage distribution of data bits in a dual bit memory structure, taking into account its structural characteristics.

Systems and methods are provided that overcome or minimize the problems and disadvantages of conventional memory cell soft program verification techniques and systems. The present invention includes a method and system for verifying a threshold voltage of an erased cell of one or more dual bit cells in a memory device, such as a flash memory. The present invention enables efficient and complete soft program verification that minimizes the unintended and undesired data retention, transient erase and cell read leakage issues associated with dual bit cell structures. The present invention provides an important advantage when employed in connection with dual bit memory cells where only one bit is actively used for data storage. However, it should be noted that the present invention is directed to finding usefulness in the context of dual bit memory cell structures, and therefore the present invention is not limited to any particular dual bit cell use or structure.

According to one aspect of the present invention, a method is provided for verifying a threshold voltage of an erased cell of a dual bit memory cell. The method of verifying the threshold voltage of an erased cell includes performing a determination as to whether the first bit or the second bit of the dual bit memory cell is properly soft programmed.

Verification of proper soft programming of dual bit memory cell structures in accordance with the method of the present invention provides that an unwanted data retention or bit transient erase problem (which results in a low threshold voltage and consequently a high leakage current) results in the operation of the core cell. For example, proper erasure, read / write functions). In this way, the present invention provides significant performance advantages over conventional methods typically used for soft programming of single bit (eg stacked gate) memory cell types. The present invention includes repeating the method for another dual bit memory cell so that byte-based soft programming verification can be achieved, for example in connection with chip erase or sector erase operations.

Soft program verification of the core cell threshold voltage is performed by applying a voltage to the memory cell to be verified and applying another voltage to a reference cell having a known threshold voltage, and then the currents of the core cell and the reference cell under analysis are respectively evaluated. Compare. This comparison shows that when one or more of the soft programming pulses has reduced the current of the cell to be verified less than the current of the reference cell, the core cell threshold voltage is greater than the target minimum erase cell threshold voltage. Further, according to one aspect of the present invention, this process may be repeated for each cell of the array until each erase cell threshold voltage is above a target minimum.

In addition, the method may also include calculating the number of soft program pulses applied to the cell or blocks of cells if any one core cell or blocks of core cells do not respond to soft program verification. have. In this case, if the predetermined maximum soft program pulse count is exceeded, the cell or block of cells is found to have failed soft programming, thus avoiding a continuous soft program loop. For example, the method includes initializing a pulse counter before each new cell address is selected, performing the soft program verification, and the pulse counter exceeding the predetermined maximum pulse count. Determining whether or not the operation has been performed, and then incrementing the pulse counter by applying another soft program pulse if the count did not exceed the maximum pulse count, and if the pulse count And may take appropriate action for failed soft programming if the maximum pulse count has been exceeded.

According to another aspect of the invention, the subsequent soft programming pulses (e.g., pulse width, pulse height) are tailored to the differential current in the comparator, thereby greatly speeding up the entire soft programming process. Alternatively, or a method is provided to minimize the impact of excessive soft programming.

The method of the present invention may include several selected core cells or blocks of cells for soft programming operation as well as selected core cells or blocks of cells for soft program check.

According to another aspect of the present invention, a method of soft programming and verifying a plurality of dual bit flash memory cells is provided, the method comprising soft programming a plurality of dual bit flash memory cells, and at least one of the plurality of Verifying proper soft programming of a first bit of a dual bit flash memory cell, verifying proper soft programming of a second bit of at least one of said plurality of dual bit flash memory cells, and said first and first Determining that the cell is properly soft programmed if the two bits are properly soft programmed.                 

To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly defined in the claims. The following detailed description and the annexed drawings set forth in detail certain illustrative aspects and embodiments of the invention. However, these only illustrate some of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention, with reference to the drawings.

1A is a fragmentary cross-sectional view of an exemplary prior art single bit flash memory cell;

1B is a fragmentary cross-sectional view of an exemplary prior art dual bit memory cell in which various aspects of the present invention may be implemented;

FIG. 2 is a distribution diagram illustrating erase cell threshold voltage distributions of multiple core cells of an exemplary prior art flash memory array; FIG.

3 is a distribution diagram illustrating an erase cell threshold voltage distribution and a programmed cell threshold voltage distribution of multiple core cells of an exemplary dual bit memory array, with transient erase bits requiring soft programming in accordance with the present invention;

4 is a system level functional block diagram illustrating an exemplary soft program and soft program verification system in which various aspects of the invention may be performed;

5A is a schematic diagram illustrating an exemplary core cell, core current and gate voltage of the system of FIG. 4;                 

FIG. 5B is a schematic diagram illustrating an exemplary reference cell, reference current and gate voltage of the system of FIG. 4; FIG.

6 is a functional block diagram illustrating the soft program reference voltage and charge pump logic circuit of the system of FIG. 4;

7 is a schematic diagram illustrating an exemplary soft program multiplexer logic circuit of the system of FIG. 4;

FIG. 8 is a schematic diagram illustrating an exemplary soft program reference voltage logic circuit and a voltage divider circuit of the system of FIG. 6;

9 is a flow diagram illustrating an exemplary method for verifying memory cell soft programming in accordance with the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals designate like elements throughout. The present invention provides a method and system for soft programming of one or more dual bit memory cells and for verifying the suitability of soft programming thereof, and can be used in connection with chip or sector soft program and soft program verify operations in flash memory devices. For example, a sector soft programming verify operation is performed to apply soft programming pulses to each such cell in a flash memory device. The invention can then be employed to verify that the cells of the device are properly soft programmed.

In addition, the present invention reconstructs cells that have been excessively erased (e.g., by selectively applying soft program voltage pulses to one or both individual bits of a dual bit memory cell) during the erase portion of the algorithm performed before the soft program verify operation. Attempts to soft program are optionally made. The present invention also provides for selective revalidation of proper soft programming for one or both bits of the dual bit cell.

According to one aspect of the present invention, proper soft program verification is accomplished by generating a soft program core cell verify voltage and generating a reference cell verify voltage having a value different from the core cell verify voltage. The method further includes generating a core cell current by applying the core cell verify voltage to the gate portion of the transient erasure core cell, and generating a reference cell current by applying the reference cell voltage verify voltage to the gate portion of the reference cell. Include. Finally, the method includes determining whether the threshold voltage associated with the erase core cell is less than a predetermined threshold based on the comparison of the core cell current and the reference cell current.

Although the present invention is shown and described below in connection with a dual bit memory cell structure in which only one bit of each cell is used for data storage, the present invention is also applicable to other types of structures and other dual bit structure usage techniques. You will find that you can.

Referring again to the drawings, FIG. 2 shows a characteristic curve known as the threshold voltage distribution of erased core cells. FIG. 2 illustrates how the core cell threshold voltages of a flash memory array differ after each erase operation, which is illustrated by a curve 200 representing the number of cells having threshold voltages V _T of specific values. The least erased cells have relatively high threshold voltages in the V _TMAX region, while the most erased cells (sometimes referred to as "over erase cells") have low thresholds that can be zero or negative in the V _TMIN region. It can be seen that they have voltages. However, the threshold voltage distribution curve segment 210 indicates that there are still many erase cells with relatively low threshold voltages. After correcting V _T of the most heavily erased cells through soft program and soft program verify operation, the erase core cell threshold voltage distribution curve 200 is at the low voltage end of the curve (shown as curve line 210). Narrow to about 0 volts. Since the background leakage current of the cell changes as a function of the threshold voltage, the lower the threshold voltage of the erase cell, the higher the leakage current will be. Since up to 512 cells can be connected to the bit line, the total background leakage current can adversely exceed the cell read current, causing subsequent read errors. Thus, it is desirable to not only prevent the cells from over erasing, but also to reduce the threshold voltage distribution to the lowest possible range so that ideally all cells have the same high threshold voltage after erasing.

Similarly, FIG. 3 illustrates a characteristic cell threshold voltage distribution curve of an exemplary dual bit memory array showing a preferred erase cell threshold voltage distribution 350 and a programmed cell threshold voltage distribution 360. As noted above, after erasing, some cells are over erased, causing excessively low threshold voltage (shaded region 370) and thus high drain current leakage (which may later cause problems with read, program verify, or erase operations). Can be generated). Conventional chip, sector, or cell soft programming methods typically used in single bit stacked gate cells have attempted to correct a transient erase cell by applying one or more program pulses to the transient erase cell. Soft programming effectively narrows the distribution of the cell threshold voltage across the flash memory array by increasing (or correcting) the low threshold voltage for these cells. Soft program verification was performed by comparing the current generated in the selected core cell (and its associated erase cell threshold voltage) with the current of the reference cell having an acceptable threshold voltage.

Comparing Figures 2 and 3, prior art single bit cells are typically soft program corrected to about 0 volts V _TMIN , whereas for dual bit erase cells, soft program corrected V _TMIN is about 0.7 volts. It can be seen that the increase. In the prior art stacked gate cells, the reference cells are fabricated (compared to each other) similar to the selected core cell, and both the reference cell and the core cell were given the same gate voltage during soft program verification. However, in a dual bit cell structure, the reference cell structure cannot be fabricated as easily as the core cells, and the soft program check is still performed to produce the desired erase core cell threshold voltage V _T (eg, V _T > 0.7 volts). Should be done. The inventors of the present invention have found that in the trimming of V _T of a new reference cell structure, attempting to trim the V _{T below} about 1.7 results in an unusable high cell leakage current.

In accordance with the present invention and the solution to these problems, the inventors apply to the gate and core cell structures of the new reference cell structure, respectively, such that the reference cell produces a current that is compared with the erase core cell current associated with V _T > 0.7 volts. A method and system for generating different voltages are proposed.

The invention and advantages may be understood from FIG. 4, which illustrates a functional block diagram of an exemplary soft program and soft program verification system 400 in which various aspects of the invention may be achieved. For example, the system of FIG. 4 may be comprised of the three functional blocks shown to prevent erase memory cells from having an erase cell threshold voltage below a predetermined level.

The flash memory array system 402 of FIG. 4 typically includes an array of core cells 405 subdivided into sectors, blocks and individual core cells. These cells are arranged in rows and columns, and the control gates of all the cells in the row are connected to a common word line. The drains of cells located in a particular column are all connected to a common bit line, and the sources of all the cells of the array are connected to a common source line 490 to measure the drain current I _CORE of the core cells at 490. This becomes possible. The memory system 402 also has address controllers 410, which are word-row controllers 420 and bit-column controllers 415 used to select individual cells, blocks, or sectors of the core cells 405. It acts as a matrix of multiplexers that work in conjunction with them. Row controller block 420 is connected to the word lines of the array cells, and column controller block 415 is connected to the bit lines of the array. In operation, individual flash cells are individually addressed through each word line and bit line using control circuitry and peripheral decoders for programming (write), read or erase functions. These flash core cells 405 are subject to the soft program and soft program verify operations of the present invention, which are discussed in detail below.

A soft program control circuit 430 of Figure 4 is the soft program multiplexer 435, a charge pump (charge pump) (440) and soft-program composed of the reference voltage circuit 445, reference numeral 450 a soft program voltage (V ₁ to ), A soft program core cell verify voltage V ₃ is generated at 455 and a reference cell verify voltage V _{2 at} 460. In response to a logic command to enter soft program mode, or as a result of, for example, soft program verify compare command 487, multiplexer circuit 430 selects reference logic circuit 445 or, for example, the next core address selection. In order to control 437, a soft program enable signal 436 is generated. Multiplexer circuit 435 also generates a regulated and clamped supply voltage 438 to wordline charge pump circuit 440. Charge pumps at 440 are a drain charge pump for generating a supply voltage for a program verify operation, and a wordline charge pump configured to generate a boosted wordline supply voltage for a voltage divider in the soft program reference voltage circuit 445. It includes. Soft program reference voltage circuit 445 has soft enable signals 436 and 486 and charge pump voltages 442 and 444 used for reference logic circuit multiplexer in soft program reference voltage circuit 445, eg, For example, discontinuous soft program and soft program verify voltages V ₁ , V ₂ and V ₃ are generated via a voltage divider.

In FIG. 4, the soft program verify control circuit 470 uses the reference cell verify voltage 460, ie V ₂ , to generate a reference cell current I _{REF at} 495. It is formed including the reference cell 480. The control circuit 470 may further include a soft program verification comparator circuit 475. The soft program verification comparator circuit 475 may include a transient core cell verification current I _CORE and a reference numeral 495. The reference cell current I _REF is compared to indicate at the output of reference numeral 477 whether the selected erase core cell threshold voltage is less than a predetermined level. The soft program verify comparator circuit 475 operates to provide a V _T indication to the verify control circuit 485, which circuit 485 is one or more soft program control signals 486 to be used in soft programming based on the indication. 487).

In operation, when the comparator 475 of the soft program verification control circuit 470 determines that V _T of the selected core cell is less than 0.7 volts, the comparator 475 generates a signal 477 for starting a predetermined soft program pulse. ) Is supplied back from the verification controller circuit 485 to the soft program control circuit 430 via reference numeral 487.

Alternatively, according to another aspect of the present invention, subsequent soft programming pulses (eg, pulse width, pulse height) can be tailored according to the differential current of comparator 475 to speed up the entire soft programming process. Systems and methods are provided that can greatly increase or minimize the impact of transient soft programming. To achieve this, the differential current can be measured with a sense amplifier (e.g., a differential current amplifier) at 475 and the result is fed to the verification controller circuit 485 via reference 477. This verification controller circuit 485 is configured to convert the differential current generated at 475 to any combination of proportional pulse width or pulse height modulation of the soft program pulses.

In another variation of the invention, subsequent soft programming pulses (eg, pulse width, pulses) through the use of a look-up table located in a portion of the core memory array 405, or in separate memory. A system and method for customizing the height are provided, where the differential current generated at 475 is divided into two or more levels, resulting in the selection of an appropriate optimized pulse width / height modulation of the soft programming pulse. Lose. Another variation and aspect of the present invention is that the entire flash memory array is selected and the differential current generated at 475 can be used for any combination of proportional pulse width or pulse height modulation of the soft program pulses, or for subsequent soft program operation as a whole. Provided by a method used to generate multiple series of pulses, such as a pulse string made for a flash memory array.

As shown in FIGS. 5A and 5B, the inventors have applied a predetermined drain-source bias of about 1.2 volts to both the core cell drain and the reference cell drain, about 2.7 volts to the core cell gate, and about When 3.7 volts were supplied to the reference cell gate, it was found that the currents are equivalent to each other if V _T of the core cell is equal to 0.7 volts. The development of this reference cell voltage is:

Using the equation: I _D = k (V _GS -V _T ) ²

For erased core cells: I _D CORE = k (V _GS CORE-V _T CORE) ²

For reference cell: I _D REF = k (V _GS REF-V _T REF) ²

If you want V _T CORE = 0.7V and V _T REF = 1.7V,

Now, to compare the reference cell current with the core cell current equally:

I _D REF = I _D CORE

And k (V _GS REF-V _T REF) ² = k (V _GS CORE-V _T CORE) ²

Divide both sides: V _GS REF-V _T REF = V _GS CORE-V _T CORE

Solve for new reference values: V _GS REF = V _GS CORE-V _T CORE + V _T REF

Substituting a given value: V _GS REF = V _GS CORE-0.7 + 1.7

Substituting core cell values: V _GS REF = 2.7-0.7 + 1.7

Thus, V _GS REF = 3.7 volts is obtained.

Therefore, if the currents through the core cell and the reference cell are the same, V _T of the core cell is 0.7 volts. On the other hand, if the core cell current is greater than the reference cell current, V _T of the core cell is less than 0.7 volts (predetermined threshold) and requires another soft programming pulse.

Referring now to the functional block diagram of FIG. 6, the various voltages required in the soft program control circuit 430 of FIG. 4 (eg, voltage 610 for soft programming, voltage for soft programming verification 620, An exemplary method and system 600 for generating word line (core cell) gate 630 and voltages for reference cell gate reference voltage 640 are shown. The wordline charge pump circuit 650 generates a supply voltage 670 boosted to the soft program verify supply 620 via the reference logic circuit 680 in response to the soft program mode enable signal 690. The drain charge pump circuit 660 generates a boosted programming voltage 610 to the reference logic circuit 680 in response to a program mode signal (not shown). As can be seen from FIG. 6, the soft program control system 600 may be configured with various voltages (eg, V ₁ , V ₂ , V ₃ ) having different values (eg, V ₁ , V ₂ , V ₃ ) for use in soft program verification mode. For example, via a resistive network). In this manner, unique voltages are provided to each of the core cell and the reference cell.
7 is a schematic diagram illustrating an exemplary soft program multiplexer logic circuit 700 (eg, related to the program multiplexer 435 of FIG. 4). This multiplexer circuit 700 generates a network of logic gates for generating a soft program enable signal 710 to the reference logic circuit 680 of FIG. 6 in response to a soft program mode signal returned through the network of logic gates 702. 702 is used. Multiplexer circuit 700 is also maintained by a latch 715 that is clamped by diode 730 to generate supply voltage 740 provided to wordline charge pump circuit 650 of FIG. regulator) uses a program supply voltage 705 controlled by transistor 720.

8 is a more detailed schematic diagram 800 of an exemplary soft program reference voltage logic circuit 805 and a voltage divider circuit 850 (eg, associated with circuit 600 of FIG. 6). The word line voltage 810 boosted by the charge pump is held by the latch 825 and enters the soft program verify voltage 820 (or in FIG. 2) entering the gate of the regulator transistor 830 and the soft program mode transistor 840. By supplying 620, the voltage divider 850 ratio is set to generate a 3.7 volt reference cell gate reference voltage 860 and an 2.7 volt erase core cell gate reference voltage 870. In the above example manner, voltages having different values are provided such that the core cell and the reference cell have their required gate voltages applied thereto to determine whether the erase core cell V _T is greater than a predetermined value.

According to another aspect of the present invention, a method is provided for ensuring that erase memory cells do not have an erase cell threshold voltage below a predetermined level. 9 is a flow diagram 900 illustrating an exemplary method for verify memory cell soft programming in accordance with the present invention, and will be discussed in connection with the example system of FIG. 4 for description. For example, if an erase or erase verify operation is performed to erase data bits of a memory sector (e.g., by writing a value there), the method 900 begins at step 910 and then The soft program and soft program verify mode are enabled at step 920.

The method 900 proceeds to step 925 where the cell address is initialized to the first address, and at step 930, for example, the pulse counter is initialized to zero. Following step 930, the first cell address is selected at step 940. The first memory cell is then verified with the soft program at step 950. At decision step 950, it is determined whether the core cell has been properly erased rather than excessively erased. As shown and described in more detail with respect to FIG. 4 below, the soft program verify operations performed in steps 950 and 965 of the method 900 apply about 2.7 volts reference voltage to the selected core cell gate. Applying a different reference voltage (e.g., about 3.7 volts) to the reference cell gate, and then comparing the two currents to make a decision based on a comparison of whether the erase core cell threshold voltage associated with it is greater than 0.7 volts. Can be performed.

If, for example, the core cell current selected in step 950 is not less than the reference cell current, it is determined that the core cell has a threshold voltage less than 0.7 volts, and the method 900 proceeds to step 955. Proceeding, calculation of the current number of soft program pulses already applied to the core cell attempting to correct the erase cell threshold voltage can be performed. If the predetermined number of pulses N _P has been exceeded, a determination is made at step 955 to confirm that the core cell has failed the soft program process and proceed to step 970. In this way, repeated soft program pulses will not be applied to the core cell without performing revalidation, which program will not be constrained in a continuous loop if the selected cell is defective, and most importantly, Soft program pulse widths can be shorter, which makes the overall soft programming time faster because the soft programming time should be spent only in the most necessary areas. However, if at step 955 the number of predetermined pulses has not exceeded N _P , the method 900 proceeds to step 960, where the current number of pulses is increased.

At step 960, the method 900 proceeds to step 965 to apply a soft program pulse to the core cell and returns to step 950 for another soft program verification.

If it is found in step 950 that the cell is properly soft programmed, the method 900 proceeds to step 980 to determine whether the last cell address has been reached (e.g., in a given cell memory block or sector). Or in a given multi-cell memory block or sector). For example, this method may optionally be employed for erase verification of any number of cells (e.g. 8 or 16) connected in a NOR structure, but any number of such cells may be continuously verified in accordance with the present invention. Other embodiments are also possible.                 

If the last cell address did not reach decision step 980, the method proceeds to step 985, and prior to proceeding to step 990, the soft program pulse counter is reset. In step 990, the current address is incremented before proceeding back to step 940, so that the next cell address is selected as before. If the last cell has reached decision step 980 (ie, all such cells have been verified), the method 900 ends at step 995.

Thus, the method 900 may optionally verify each cell of the dual bit memory cell to ensure proper soft programming before proceeding to another such cell at step 985 or ending at step 995. , Re-verify, soft program, and soft program again.

In this regard, the method 900 includes other steps that determine, after a number of unsuccessful soft programming / verification attempts, that internal counters or cells are useless (eg, impossible to properly soft program). The cell (eg, a number of related cells such as a byte or word) may be marked as bad, or the portion itself may remain as part of a failed sector erase operation. In this regard, furthermore, if the method 900 is employed in any manufacturing process (e.g., before shipment to the consumer, before or after packaging), one cell or multiple cells are added to mark as bad. ) Can be used and employed to supply replacement or redundant storage cells as a replacement, an acceptable manufacturing yield can be achieved. The method 900 may also be employed in connection with a sector or chip soft program / verification initiated by an end user, and cell failures may be displayed to the user through the corresponding memory device as a result.

While the present invention has been shown and described with respect to one or more embodiments, equivalent replacements and modifications will be possible to those skilled in the art upon reading and understanding the present specification and the accompanying drawings. In particular with respect to the various functions performed by the components disclosed above (assemblies, devices, circuits, etc.), the terms used to describe such components (including "means") are used herein to describe the invention. Although in an exemplary embodiment it is not structurally equivalent to the disclosed structure for performing a function, unless otherwise indicated, it is intended to be consistent with any component (ie, functionally equivalent) that performs the described function of the disclosed component. It became. In addition, while specific features of the present invention have been described with reference to only one of several embodiments, such features may be combined with one or more features of other embodiments, which would be advantageous in any given or particular application. Can be. Moreover, the term "include" as used in the description and claims should be interpreted to have a meaning similar to the term "comprising".

The system and related methods in accordance with the present invention can be used in the field of integrated circuit design to provide a way to narrow the V _T distribution of erase core cells in flash memory devices.

Claims (17)

A method 900 for preventing an erase dual bit flash memory cell having an associated ONO charge trapping layer from exhibiting an erase cell threshold voltage below a predetermined level. Generating (920) a soft program verify core cell verify voltage; Generating a reference cell verify voltage having a value different from the soft program verify core cell verify voltage (925); Applying (940, 965) the soft program verify core cell verify voltage to the gate portion of a dual bit erase core cell having an ONO charge trapping layer, thereby generating a core cell current flowing therethrough; Applying (940) the reference cell voltage verification voltage to a gate portion of a reference cell to generate a reference cell current flowing through it; Based on the comparison of the core cell current and the reference cell current, determining (950) whether a threshold voltage associated with the erase dual bit core cell having an ONO charge trapping layer is less than a predetermined threshold; And Generating a subsequent soft programming pulse to the erase dual bit core cell if the associated threshold voltage is less than the predetermined threshold, the subsequent soft programming pulse depending on the amount of the threshold voltage less than the predetermined threshold. Method comprising a. The method of claim 1, And the subsequent soft programming pulse has a pulse width or pulse height that depends on the amount of threshold voltage less than the predetermined threshold. The method according to claim 1 or 2, Determining whether or not a threshold voltage associated with the erase dual bit core cell is less than the predetermined threshold and generating the subsequent soft programming pulses include: differential current based on the core cell current and the reference cell current; Determining and modulating at least one of pulse width and pulse height based on the differential current. A system 400 for preventing erased dual bit flash memory cells having an associated ONO charge trapping layer from having an erase cell threshold voltage below a predetermined level. Generate a soft program voltage (V1) 450, a soft program core cell verify voltage (V3) 455, and a reference cell verify voltage (V2) 460 having a different value from the soft program core cell verify voltage (V3). A soft program control circuit 430 configured to; Flash memory 402 of dual bit core cells with ONO charge trapping structures 405 functionally coupled to core address control circuit 410, bit / column control circuit 415, and word / row control circuit 420. An array, said dual bit flash memory array operative to generate a core cell verify current 490 for a selected erase dual bit core cell; And Soft program verify control circuit 470 configured to generate a reference current 495 using the reference cell verify voltage (V2) 460 and compare the core cell verify current 490 with the reference cell current 495. ), The soft program verification control circuit 470 is Soft program verify comparator circuit (475) configured to generate an indication (477) of whether the selected erase dual bit core cell has an erase cell threshold voltage that is below a predetermined level based on the comparison; And A verification functionally coupled to the program verify comparator circuit 475 and configured to output one or more soft program control signals 486 and 487 for use in soft programming of the selected dual bit cell based on the indication 477. Control logic circuit 485, wherein the one or more soft program control signals are operable to modulate a subsequent soft programming pulse based on an amount of an erase core threshold voltage that falls below a predetermined level of the indication 477. System characterized. The method of claim 4, wherein The verify control logic circuit 485 controls the next core cell address for use in subsequent erase core cell verification when the comparator circuit 475 indicates that the erase dual bit cell threshold voltage is greater than the predetermined level. Further operate to generate signals (487, 437). The method according to claim 4 or 5, The soft program control circuit 430 is A soft program multiplexer circuit 435 configured to select from a program mode signal 437 or a soft program mode signal 436; Two charges comprising a wordline charge pump circuit 650 configured to generate a boosted wordline voltage signal 670 and a drain charge pump circuit 660 configured to generate a boosted programming voltage signal 610. A group of pumps 440; And A soft program reference selected from a program mode signal 610 or a soft program mode signal 690 and operative to generate a plurality of soft program verify voltages 620, 630, 640 based on the selected voltage signal in response thereto. And a voltage circuit (445, 690). The method of claim 6, The soft program multiplexer circuit 700 is A network (702) of mode selection logic gates operable to generate a soft program enable signal (710) to the reference logic circuit (680) in response to the soft program mode signal (690); And A word line charge pump supply circuit 705, 715, 720, 730 that is operable to generate a supply voltage 740 to the word line charge pump circuit 650 in response to the soft program mode signal 750. System comprising a. The method of claim 6, The group of charge pumps (440, 650, 660), A wordline charge pump circuit (650) operatively coupled to the soft program multiplexer circuit (700) and configured to generate a boosted wordline voltage (670) in response to the soft program mode signal (750); And And a drain charge pump circuit (660) configured to generate a boosted programming voltage (610) in said reference logic circuit (680) in response to a program mode signal (760). The method of claim 7, wherein The group of charge pumps (440, 650, 660), A wordline charge pump circuit (650) operatively coupled to the soft program multiplexer circuit (700) and configured to generate a boosted wordline voltage (670) in response to the soft program mode signal (750); And And a drain charge pump circuit (660) configured to generate a boosted programming voltage (610) in said reference logic circuit (680) in response to a program mode signal (760). The method of claim 6, The soft program reference voltage circuits 445 and 800 are Select the charge pump voltages 670, 610; 810, 830 and their respective modes, and then transfer the selected voltage to the verify divider circuit 850 and functionally coupled to the soft program multiplexer circuit 700, A reference logic circuit (680, 800) configured to receive a soft program enable command (690, 840, 820). The method of claim 7, wherein The soft program reference voltage circuits 445 and 800 are Select the charge pump voltages 670, 610; 810, 830 and their respective modes, and then transfer the selected voltage to the verify divider circuit 850 and functionally coupled to the soft program multiplexer circuit 700, A reference logic circuit (680, 800) configured to receive a soft program enable command (690, 840, 820). The method of claim 8, The soft program reference voltage circuits 445 and 800 are Select the charge pump voltages 670, 610; 810, 830 and their respective modes, and then transfer the selected voltage to the verify divider circuit 850 and functionally coupled to the soft program multiplexer circuit 700, A reference logic circuit (680, 800) configured to receive a soft program enable command (690, 840, 820). The method of claim 9, The soft program reference voltage circuits 445 and 800 are Select the charge pump voltages 670, 610; 810, 830 and their respective modes, and then transfer the selected voltage to the verify divider circuit 850 and functionally coupled to the soft program multiplexer circuit 700, A reference logic circuit (680, 800) configured to receive a soft program enable command (690, 840, 820). The method of claim 10, The soft program reference voltage circuits 445 and 800 are A verify voltage divider circuit 850 configured to generate at least subsequent verify voltages; A 4.0 volt soft program verify voltage (620, 830) used as a power supply for the verify voltage divider (850) and sent to the gate (840) of the soft program verify mode transistor to set an accurate voltage divider ratio; A 3.7 volt reference voltage 860 sent to the gate 480 of the reference cell used to set a predetermined reference cell current 495; And And a 2.7 volt wordline voltage (630, 870) sent to the gate (455) of the dual bit core cell wordline used to set the dual bit core cell current (490). The method of claim 11, The soft program reference voltage circuits 445 and 800 are A verify voltage divider circuit 850 configured to generate at least subsequent verify voltages; A 4.0 volt soft program verify voltage (620, 830) used as a power supply for the verify voltage divider (850) and sent to the gate (840) of the soft program verify mode transistor to set an accurate voltage divider ratio; A 3.7 volt reference voltage 860 sent to the gate 480 of the reference cell used to set a predetermined reference cell current 495; And And a 2.7 volt wordline voltage (630, 870) sent to the gate (455) of the dual bit core cell wordline used to set the dual bit core cell current (490). The method of claim 12, The soft program reference voltage circuits 445 and 800 are A verify voltage divider circuit 850 configured to generate at least subsequent verify voltages; A 4.0 volt soft program verify voltage (620, 830) used as a power supply for the verify voltage divider (850) and sent to the gate (840) of the soft program verify mode transistor to set an accurate voltage divider ratio; A 3.7 volt reference voltage 860 sent to the gate 480 of the reference cell used to set a predetermined reference cell current 495; And And a 2.7 volt wordline voltage (630, 870) sent to the gate (455) of the dual bit core cell wordline used to set the dual bit core cell current (490). The method of claim 13, The soft program reference voltage circuits 445 and 800 are A verify voltage divider circuit 850 configured to generate at least subsequent verify voltages; A 4.0 volt soft program verify voltage (620, 830) used as a power supply for the verify voltage divider (850) and sent to the gate (840) of the soft program verify mode transistor to set an accurate voltage divider ratio; A 3.7 volt reference voltage 860 sent to the gate 480 of the reference cell used to set a predetermined reference cell current 495; And And a 2.7 volt wordline voltage (630, 870) sent to the gate (455) of the dual bit core cell wordline used to set the dual bit core cell current (490).

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