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KR100826791B1 - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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KR100826791B1
KR100826791B1 KR1020020076835A KR20020076835A KR100826791B1 KR 100826791 B1 KR100826791 B1 KR 100826791B1 KR 1020020076835 A KR1020020076835 A KR 1020020076835A KR 20020076835 A KR20020076835 A KR 20020076835A KR 100826791 B1 KR100826791 B1 KR 100826791B1
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oxide film
trench
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forming
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김성래
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means

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Abstract

반도체 소자의 트렌치 산화막을 형성하는 방법에 관한 것으로, 그 목적은 보이드가 형성되지 않고 트렌치가 완전히 매입되도록 트렌치 산화막을 형성하는 방법을 제공하는 것이다. 이를 위해 본 발명에서는 트렌치산화막의 증착 후 1050-1150℃의 비교적 높은 온도로 열처리하여 트렌치산화막을 치밀화 및 안정화시키고, 트렌치산화막 및 실리콘질화막 상에 캡산화막을 형성하여 이후 진행하는 습식식각 공정 진행시 트렌치산화막이 비정상적으로 식각되는 것을 막아준다. The present invention relates to a method for forming a trench oxide film of a semiconductor device, and an object thereof is to provide a method for forming a trench oxide film so that a trench is completely embedded without voids being formed. To this end, in the present invention, after the deposition of the trench oxide film, the heat treatment is performed at a relatively high temperature of 1050-1150 ° C. to densify and stabilize the trench oxide film, and form a cap oxide film on the trench oxide film and the silicon nitride film. This prevents the oxide film from abnormally etching.

트렌치, 열처리, 캡산화막 Trench, Heat Treatment, Cap Oxide

Description

반도체 소자 제조 방법 {Fabrication method of semiconductor device} Fabrication method of semiconductor device

도 1a 내지 도 1c는 종래 반도체 소자 제조 방법을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a conventional semiconductor device manufacturing method.

도 2a 내지 도 2d는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

본 발명은 반도체 제조 방법에 관한 것으로, 더욱 상세하게는 트렌치 산화막을 형성하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor, and more particularly, to a method for forming a trench oxide film.

반도체 소자의 격리구조로서 트렌치 격리구조 (STI : shallow trench isolation)가 많이 사용되고 있다. 트렌치 격리구조에서는 반도체 기판 내에 트렌치를 형성하고 그 내부에 절연물질을 충진시킴으로써 필드영역의 크기를 목적한 트렌치의 크기로 제한하기 때문에 반도체 소자의 미세화에 유리하다.As the isolation structure of the semiconductor device, a trench trench structure (STI: shallow trench isolation) is widely used. In the trench isolation structure, by forming a trench in a semiconductor substrate and filling an insulating material therein, the size of the field region is limited to the desired trench size, which is advantageous for miniaturization of semiconductor devices.

그러면, 종래 트렌치 격리구조의 반도체 소자 제조 방법에 대해 첨부된 도면을 참조하여 설명하면 다음과 같다. 도 1a 내지 도 1c는 종래 반도체 소자 제조 방법을 도시한 단면도이다. Next, a method of manufacturing a semiconductor device having a conventional trench isolation structure will be described with reference to the accompanying drawings. 1A to 1C are cross-sectional views illustrating a conventional semiconductor device manufacturing method.

먼저, 도 1a에 도시된 바와 같이, 반도체 기판(1) 상에 실리콘질화막(2)을 증착한 후, 그 상부에 감광막을 도포하고 노광하여 트렌치로 예정된 영역의 상부에 해당하는 감광막만을 제거하여 감광막 패턴(3)을 형성한다.First, as shown in FIG. 1A, after the silicon nitride film 2 is deposited on the semiconductor substrate 1, a photoresist film is applied and exposed thereon to remove only the photoresist film corresponding to the upper portion of the region intended as a trench. The pattern 3 is formed.

이 때, 실리콘질화막(2)은 후속공정인 화학기계적 연마공정에서 종료층 역할을 하게 된다.At this time, the silicon nitride film 2 serves as an end layer in a subsequent chemical mechanical polishing process.

다음, 도 1b에 도시된 바와 같이, 감광막 패턴(3)을 마스크로 하여 노출된 실리콘질화막(2) 및 목적하는 소정깊이의 기판(1)을 건식식각하여 반도체 기판(1) 내에 트렌치(100)를 형성한 후, 감광막 패턴(3)을 제거하고 세정공정을 수행한다.Next, as shown in FIG. 1B, the trench 100 is dried in the semiconductor substrate 1 by dry etching the exposed silicon nitride film 2 and the substrate 1 having a desired depth by using the photoresist pattern 3 as a mask. After forming, the photoresist pattern 3 is removed and a cleaning process is performed.

이어서, 트렌치(100)를 포함한 상부 전면에 열산화법으로 라이너산화막(4)을 얇게 증착하고, 트렌치(100)를 충분히 충진시키도록 라이너산화막(4) 상에 트렌치 산화막(5)을 두껍게 증착한다.Subsequently, the liner oxide film 4 is thinly deposited on the upper surface including the trench 100 by thermal oxidation, and the trench oxide film 5 is thickly deposited on the liner oxide film 4 to sufficiently fill the trench 100.

이어서, 트렌치 산화막(5)의 안정화 및 치밀화를 위해 1000℃ 온도로 열처리한다.Subsequently, heat treatment is performed at a temperature of 1000 ° C. for stabilization and densification of the trench oxide film 5.

다음, 도 1c에 도시된 바와 같이, 실리콘질화막(2)이 노출될 때까지 트렌치 산화막(5)을 화학기계적 연마하여 평탄화시킨 후, H3PO4를 식각케미칼로 이용한 습식식각으로 실리콘질화막(2)을 제거함으로써 트렌치 격리공정을 완료한다.Next, as shown in FIG. 1C, the trench oxide film 5 is chemically polished and planarized until the silicon nitride film 2 is exposed, and then the silicon nitride film 2 is wet-etched using H 3 PO 4 as an etching chemical. ) To complete the trench isolation process.

그런데, H3PO4를 식각케미칼로 이용한 습식식각으로 실리콘질화막(2)을 제거할 때 열처리를 통해 미처 안정화 및 치밀화가 덜 이루어진 트렌치산화막(5)이 비정상적으로 식각되어 보이드가 발생하는 문제점이 있었다.However, when the silicon nitride film 2 was removed by wet etching using H 3 PO 4 as an etching chemical, there was a problem in which voids were generated due to abnormal etching of the trench oxide film 5 which was less stabilized and densified through heat treatment. .

이와 같이 트렌치 산화막(5) 내에 보이드(6)가 발생하면 트렌치 산화막의 평 탄화를 위한 화학기계적 연마시 그 보이드(6)가 노출되어 평탄화가 어려워지고, 평탄화 후 보이드가 노출되어 있다가 후속 공정에서 전극 형성용으로 증착하는 폴리실리콘이 보이드로 들어가서 누설전류가 발생하여 소자의 오동작을 유발하는 등 소자에 치명적인 악영향을 미치는 문제점이 있었다.As such, when the voids 6 are generated in the trench oxide film 5, the voids 6 are exposed during chemical mechanical polishing for the planarization of the trench oxide film, making it difficult to planarize. Polysilicon deposited for forming the electrode enters the voids, there is a problem that has a fatal adverse effect on the device, such as causing a leakage current caused by the device malfunction.

본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 보이드가 형성되지 않고 트렌치가 완전히 매입되도록 트렌치 산화막을 형성하는 방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method of forming a trench oxide film so that a trench is completely embedded without voids being formed.

상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 트렌치산화막의 증착 후 1050-1150℃의 비교적 높은 온도로 열처리하여 트렌치산화막을 치밀화 및 안정화시키고, 트렌치산화막 및 실리콘질화막 상에 캡산화막을 형성하여 이후 진행하는 습식식각 공정 진행시 트렌치산화막이 비정상적으로 식각되는 것을 막아준다.In order to achieve the above object, in the present invention, after the deposition of the trench oxide film, heat treatment is performed at a relatively high temperature of 1050-1150 ° C. to densify and stabilize the trench oxide film, and form a cap oxide film on the trench oxide film and the silicon nitride film. It prevents the trench oxide film from being abnormally etched during the wet etching process.

즉, 반도체 소자 제조 방법은, 반도체 기판 상에 실리콘질화막을 형성하고, 실리콘질화막 및 소정두께의 반도체 기판을 선택적으로 식각하여 반도체 기판 내에 트렌치를 형성하는 단계; 트렌치를 포함한 상부 전면에 트렌치를 충진하도록 트렌치 산화막을 형성하는 단계; 트렌치 산화막의 치밀화를 위해 1050-1150℃의 온도로 열처리하는 단계; 실리콘질화막이 노출될 때까지 트렌치산화막을 화학기계적 연마하여 평탄화하는 단계; 평탄화된 실리콘질화막 및 트렌치산화막의 상부 전면에 캡산화막을 형성하는 단계; 및 캡산화막 및 실리콘질화막을 습식식각하여 제거하는 단계를 포함하여 이루어진다.That is, the semiconductor device manufacturing method includes forming a silicon nitride film on a semiconductor substrate, and selectively etching the silicon nitride film and a semiconductor substrate having a predetermined thickness to form a trench in the semiconductor substrate; Forming a trench oxide layer to fill the trench in the entire top surface including the trench; Heat treatment at a temperature of 1050-1150 ° C. for densification of the trench oxide film; Chemical mechanical polishing and planarizing the trench oxide film until the silicon nitride film is exposed; Forming a cap oxide film on the entire upper surface of the planarized silicon nitride film and the trench oxide film; And wet etching and removing the cap oxide film and the silicon nitride film.

여기서, 캡산화막은 상압화학기상증착(APCVD) 방법, 반대기압화학기상증착(SACVD) 방법, 플라즈마화학기상증착(PECVD) 방법, 및 고밀도플라즈마(HDP) 방법 중의 어느 한 방법을 이용하여 100-300Å 두께로 증착하는 것이 바람직하다.Here, the cap oxide film is 100-300Å using any one of atmospheric pressure chemical vapor deposition (APCVD) method, counter-pressure chemical vapor deposition (SACVD) method, plasma chemical vapor deposition (PECVD) method, and high density plasma (HDP) method. It is desirable to deposit at a thickness.

캡산화막을 제거할 때에는 식각케미칼로서 HF 케미칼을 사용하고, 실리콘질화막을 제거할 때에는 식각케미칼로서 H3PO4 케미칼을 사용하는 것이 바람직하다. When the cap oxide film is removed, it is preferable to use HF chemical as the etching chemical, and when removing the silicon nitride film, H 3 PO 4 chemical is used as the etching chemical.

이하, 본 발명에 따른 반도체 소자 제조 방법에 대해 첨부된 도면을 참조하여 상세히 설명한다. 도 2a 내지 도 2d는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. 2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

먼저, 도 2a에 도시된 바와 같이, 반도체 기판(11) 상에 실리콘질화막(12)을 증착한 후, 그 상부에 감광막을 도포하고 노광하여 트렌치로 예정된 영역의 상부에 해당하는 감광막만을 제거하여 감광막 패턴(13)을 형성한다. 이 때, 실리콘질화막(12)은 산화막과의 선택비가 큰 재료이므로 후속공정인 트렌치 산화막의 화학기계적 연마 공정에서 종료층 역할을 하게 된다.First, as shown in FIG. 2A, after the silicon nitride film 12 is deposited on the semiconductor substrate 11, a photoresist film is applied and exposed on top of the semiconductor substrate 11 to remove only the photoresist film corresponding to the upper portion of the region intended as a trench. The pattern 13 is formed. At this time, since the silicon nitride film 12 is a material having a large selectivity with respect to the oxide film, the silicon nitride film 12 serves as a termination layer in a subsequent chemical mechanical polishing process of the trench oxide film.

이러한 실리콘질화막(12) 형성 전에 반도체 기판(11) 상에 100-300Å 두께의 얇은 패드산화막을 증착하여 실리콘질화막 자체의 스트레스가 반도체 기판에 그대로 전달되는 것을 억제할 수도 있다.Before the silicon nitride film 12 is formed, a thin pad oxide film having a thickness of 100 to 300 Å may be deposited on the semiconductor substrate 11 to suppress the stress of the silicon nitride film itself from being transferred to the semiconductor substrate.

다음, 도 2b에 도시된 바와 같이, 감광막 패턴(13)을 마스크로 하여 노출된 실리콘질화막(12) 및 목적하는 소정깊이의 기판(11)을 건식식각하여 반도체 기판(11) 내에 트렌치(100)를 형성한 후, 감광막 패턴(13)을 제거하고 세정공정을 수행한다.Next, as shown in FIG. 2B, the trench 100 is etched in the semiconductor substrate 11 by dry etching the exposed silicon nitride film 12 and the substrate 11 having a desired depth by using the photoresist pattern 13 as a mask. After forming, the photoresist pattern 13 is removed and a cleaning process is performed.

이어서, 트렌치(100)를 포함한 상부 전면에 열산화법으로 라이너산화막(14)을 얇게 증착하고, 트렌치(100)를 충분히 충진시키도록 라이너산화막(14) 상에 트렌치 산화막(15)을 두껍게 증착한다.Subsequently, the liner oxide film 14 is thinly deposited on the upper surface including the trench 100 by thermal oxidation, and the trench oxide film 15 is thickly deposited on the liner oxide film 14 to sufficiently fill the trench 100.

트렌치산화막(15)은 상압화학기상증착(APCVD), 반대기압화학기상증착(SACVD), 플라즈마화학기상증착(PECVD), 고밀도 플라즈마(HDP) 방법 등으로 증착할 수 있다.The trench oxide film 15 may be deposited by atmospheric pressure chemical vapor deposition (APCVD), counter-pressure chemical vapor deposition (SACVD), plasma chemical vapor deposition (PECVD), high density plasma (HDP), or the like.

이어서, 공정 진행 중에 트렌치산화막(15)의 표면에 부착된 금속물질 등의 불순물 제거를 위해 트렌치산화막(15)의 표면을 전체두께의 1/20 이하만큼 정도로 얇게 식각한 후, 트렌치산화막(15)의 안정화 및 치밀화를 위해 1050-1150℃ 정도의 온도로 열처리한다. Subsequently, the surface of the trench oxide film 15 is etched thinly by about 1/20 or less of the total thickness in order to remove impurities such as metal materials attached to the surface of the trench oxide film 15 during the process, and then the trench oxide film 15 Heat treatment at a temperature of about 1050-1150 ℃ for the stabilization and densification of the.

이 때 열처리 온도는 트렌치산화막(15)의 안정화 및 치밀화를 더욱 향상시키도록 종래의 1000℃보다 높은 1050-1150℃ 정도로 하는 것이 특징이다.At this time, the heat treatment temperature is characterized in that about 1050-1150 ℃ higher than the conventional 1000 ℃ to further improve the stabilization and densification of the trench oxide film 15.

다음, 도 2c에 도시된 바와 같이, 실리콘질화막(12)이 노출될 때까지 트렌치산화막(15)을 화학기계적 연마하여 평탄화한 후, 노출된 실리콘질화막(12) 및 트렌치산화막(15) 상에 이후 습식식각에 대한 보호용으로서 캡산화막(16)을 형성한다.Next, as shown in FIG. 2C, the trench oxide film 15 is chemically polished and planarized until the silicon nitride film 12 is exposed, and then on the exposed silicon nitride film 12 and the trench oxide film 15. The cap oxide film 16 is formed to protect against wet etching.

캡산화막(16)은 APCVD, SACVD, PECVD, 또는 HDP 방법을 이용하여 100-300Å 두께로 증착할 수 있으며, 바람직하게는 200Å 두께로 증착할 수 있다.The cap oxide film 16 may be deposited to a thickness of 100-300 kV using APCVD, SACVD, PECVD, or HDP, and preferably 200 kW thick.

다음, 도 2d에 도시된 바와 같이, HF 식각케미칼을 이용하여 캡산화막(16)을 습식식각으로 제거한 후, H3PO4 식각케미칼을 이용하여 실리콘질화막(12)을 습식식각으로 제거함으로써, 트렌치 격리공정을 완료한다.Next, as shown in FIG. 2D, after the cap oxide layer 16 is wet-etched using HF etching chemical, the silicon nitride layer 12 is wet-etched using H 3 PO 4 etching chemical, and the trench is removed. Complete the containment process.

이 때 캡산화막(16)의 식각을 위해 먼저 HF 케미칼로 습식식각할 때, 캡산화막(16)을 완전히 제거하지 않고 남겨둔 다음에, 실리콘질화막(12) 제거를 위해 H3PO4 식각케미칼을 이용한 습식식각시 나머지 캡산화막(16)을 제거하기 때문에, 트렌치산화막(15)이 비정상적으로 식각되는 현상이 방지된다. 특히, 트렌치산화막(15)은 1050-1150℃ 정도의 비교적 높은 온도에서 열처리하여 더욱 안정화 및 치밀화되어 있는 상태이므로 실리콘질화막(12)의 습식식각시 비정상적으로 식각될 가능성이 매우 낮다.At this time, when wet etching with HF chemical for etching the cap oxide layer 16, the cap oxide layer 16 is left without being completely removed, and then H 3 PO 4 etching chemical is used to remove the silicon nitride layer 12. Since the remaining cap oxide film 16 is removed during the wet etching, the trench oxide film 15 may be abnormally etched. In particular, since the trench oxide film 15 is further stabilized and densified by heat treatment at a relatively high temperature of about 1050-1150 ° C., it is very unlikely that the trench oxide film 15 may be abnormally etched during wet etching of the silicon nitride film 12.

상술한 바와 같이, 본 발명에서는 게이트산화막의 치밀화 및 안정화를 위한 열처리시 종래보다 더 높은 온도로 열처리하여 보다 더 치밀화 및 안정화시키며, 또한 게이트산화막 상에 별도로 캡산화막을 형성하기 때문에, 이후 실리콘질화막 제거를 위한 습식식각시 트렌치산화막이 비정상적으로 식각되어 보이드가 형성되는 일이 방지되는 효과가 있다.As described above, in the present invention, when the heat treatment for densification and stabilization of the gate oxide film is performed at a higher temperature than before, the densification and stabilization is further performed, and since the cap oxide film is formed separately on the gate oxide film, the silicon nitride film is subsequently removed. During wet etching, the trench oxide film is abnormally etched to prevent voids from being formed.

따라서, 보이드로 인한 누설전류 발생 문제 및 누설전류에 기인한 소자의 신뢰성 감소 요인의 발생을 방지하고, 소자의 수율이 향상되는 효과가 있다.Therefore, there is an effect of preventing the occurrence of leakage current due to voids and the factor of decreasing the reliability of the device due to the leakage current, thereby improving the yield of the device.

Claims (5)

반도체 기판 상에 실리콘질화막을 형성하고, 실리콘질화막 및 반도체 기판을 선택적으로 식각하여 반도체 기판 내에 트렌치를 형성하는 단계;Forming a silicon nitride film on the semiconductor substrate, and selectively etching the silicon nitride film and the semiconductor substrate to form a trench in the semiconductor substrate; 상기 트렌치를 포함한 상부 전면에 상기 트렌치를 충진하도록 트렌치 산화막을 형성하는 단계;Forming a trench oxide layer to fill the trench in the entire upper surface including the trench; 상기 트렌치 산화막의 치밀화를 위해 1050-1150℃의 온도로 열처리하는 단계;Heat treatment at a temperature of 1050-1150 ° C. for densification of the trench oxide film; 상기 실리콘질화막이 노출될 때까지 상기 트렌치산화막을 화학기계적 연마하여 평탄화하는 단계; Chemical mechanical polishing and planarizing the trench oxide layer until the silicon nitride layer is exposed; 상기 평탄화된 실리콘질화막 및 트렌치산화막의 상부 전면에 캡산화막을 형성하는 단계; 및Forming a cap oxide film on the entire upper surface of the planarized silicon nitride film and the trench oxide film; And 상기 캡산화막 및 실리콘질화막을 습식식각하여 제거하는 단계를 포함하고, Wet etching and removing the cap oxide film and silicon nitride film, 상기 트렌치산화막의 형성 후에는, 상기 트렌치산화막의 표면에 부착된 불순물 제거를 위해 상기 트렌치산화막의 표면을 전체 트렌치산화막 두께의 1/20 이하만큼 식각하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자 제조 방법.After the formation of the trench oxide film, etching the surface of the trench oxide film by 1/20 or less of the entire thickness of the trench oxide film to remove impurities attached to the surface of the trench oxide film. Way. 제 1 항에 있어서, The method of claim 1, 상기 캡산화막은 상압화학기상증착(APCVD) 방법, 반대기압화학기상증착(SACVD) 방법, 플라즈마화학기상증착(PECVD) 방법, 및 고밀도플라즈마(HDP) 방법 중의 어느 한 방법을 이용하여 100-300Å 두께로 증착하는 것을 특징으로 하는 반도체 소자 제조 방법.The cap oxide film is 100-300 mm thick using any one of atmospheric pressure chemical vapor deposition (APCVD), counter-pressure chemical vapor deposition (SACVD), plasma chemical vapor deposition (PECVD), and high density plasma (HDP). A semiconductor device manufacturing method characterized in that the deposition. 제 2 항에 있어서, The method of claim 2, 상기 캡산화막을 제거할 때에는 식각케미칼로서 HF 케미칼을 사용하고, 상기 실리콘질화막을 제거할 때에는 식각케미칼로서 H3PO4 케미칼을 사용하는 것을 특징으로 하는 반도체 소자 제조 방법.HF chemical is used as an etching chemical when the cap oxide film is removed, and H 3 PO 4 chemical is used as an etching chemical when the silicon nitride film is removed. 제 3 항에 있어서, The method of claim 3, wherein 상기 실리콘질화막 형성 전에 상기 반도체 기판 상에 100-300Å 두께의 패드산화막을 형성하고, 상기 패드산화막 상에 상기 실리콘질화막을 형성하는 것을 특징으로 하는 반도체 소자 제조 방법.Forming a pad oxide film having a thickness of 100-300 상 에 on the semiconductor substrate before forming the silicon nitride film, and forming the silicon nitride film on the pad oxide film. 삭제delete
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KR19990080352A (en) * 1998-04-16 1999-11-05 윤종용 Trench isolation method and structure
KR20010092398A (en) * 2000-03-21 2001-10-24 니시가키 코지 Method for forming element isolation region

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990080352A (en) * 1998-04-16 1999-11-05 윤종용 Trench isolation method and structure
KR20010092398A (en) * 2000-03-21 2001-10-24 니시가키 코지 Method for forming element isolation region

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