KR100823874B1 - High Density FUNI Field Effect Transistor with Low Leakage Current and Manufacturing Method Thereof - Google Patents

Abstract

The present invention relates to a Fin field effect transistor having a low leakage current and excellent shrinkage characteristics and a method of manufacturing the same. The fin field effect transistor is a bulk silicon substrate, a fenced body formed by patterning on the substrate, a body separation portion formed by filling an insulating material in a trench formed by etching a center portion of the upper portion of the fenced body, the surface of the substrate and An insulating film formed to a predetermined height of the fence-shaped body, a gate insulating film formed on sidewalls and an upper surface of the fence-shaped body on which the insulating film is not formed, a gate electrode formed on the gate insulating film, and the fence on which the gate electrode is not formed A source / drain region formed in a predetermined region of the mold body. The gate electrode is formed by contacting the first gate electrode and the second gate electrode having different work functions, and in particular, the second gate electrode having the small work function is disposed toward the drain. As a result, the FinFET according to the present invention increases the threshold voltage by using a material having a large work function for the gate electrode, and reduces the gate induced drain leakage (GIDL) by lowering the work function of the gate electrode overlapping the drain. .

Description

High density Fin field effect transistor having low leakage current and method of manufacturing the same {High density Fin field effect transistor having low leakage current and method of manufacturing the FinFET}

1 is a perspective view showing a FinFET according to a first preferred embodiment of the present invention (which is a first embodiment of a gate electrode), and FIG. 2 is a view showing the FinFET of FIG. 1, wherein (a) is AA ′. It is a cross-sectional view shown in a cut along the direction, (b) is a cross-sectional view shown in a cut along the BB 'direction excluding the gate electrode, and (c) is a plan view shown by cutting along the C-C'.

3 is a diagram illustrating a second embodiment of a gate electrode in a FinFET according to a first preferred embodiment of the present invention, where (a) is a perspective view and (b) is a plan view.

4 is a diagram illustrating a third embodiment of a gate electrode in the FinFET according to the first preferred embodiment of the present invention, where (a) is a perspective view and (b) is a plan view.

FIG. 5 is a diagram illustrating a fourth embodiment of a gate electrode in a FinFET according to a first preferred embodiment of the present invention, where (a) is a perspective view and (b) is a plan view.

FIG. 6 illustrates a FinFET according to a second embodiment of the present invention, where (a) is a perspective view and (b) is a cross-sectional view taken along the line BB ′ except for the gate electrode.

FIG. 7 is a perspective view illustrating a FinFET according to a third embodiment of the present invention. FIG. 8 is a perspective view of the FinFET of FIG. 7, wherein (a) is a plan view and (b) is cut along the AA ′ direction. (C) is sectional drawing cut along the BB 'direction, (d) is sectional drawing cut along C-C'.

FIG. 9 illustrates a FinFET according to a fourth embodiment of the present invention, where (a) is a perspective view and (b) is a cross-sectional view taken along the line BB ′ except for the gate electrode.

10 illustrates various embodiments of the upper region of the fenced body of the FinFET according to the present invention, (a) is a cross-sectional view showing the shape of the top edge of the fenced body, (b) ) Is a cross-sectional view showing the rounded shape of the upper surface of the fence body.

FIG. 11 is a cross-sectional view illustrating various embodiments of a lower region of a fence body of a FinFET according to the present invention, in which (a) shows a separated body of an upper portion of the fence body as the width of the fence body gradually widens as it goes to the substrate. Inside is a cross-sectional view showing a structure having a vertical profile, (b) is a cross-sectional view showing a structure in which the width of the body formed separately separated on top of the fence-like body gradually widens to both sides from the top surface downward ( c) is a cross-sectional view showing a structure in which the width of the fence body is substantially constant at the top and gradually widens as it goes to the substrate from below, and (d) is the width of the body formed separately from the top of the fence body. It is a cross-sectional view showing a structure that widens from the inside of the separated body while going down from the surface.

FIG. 12 illustrates an example of a process of implementing a first gate electrode and a second gate electrode using polysilicon as a gate electrode in a first embodiment of a FinFET manufacturing method according to the present invention.

FIG. 13 illustrates an example of a process of implementing a separated body formed on an upper portion of a fenced body in a second embodiment of the FinFET manufacturing method according to the present invention.

14 is an example for showing the effect of the present invention, when n ⁺ / p ⁺ polysilicon gate length is 50 nm, body width 30 nm, n ⁺ polysilicon is 15 nm in length of the separation structure of the fence body ( NC: non-separate body, SC: body length along the direction in which the both separate body, LSC: a graph showing the I _D -V _DS characteristics of the channel only in a separate body topically).

<Explanation of symbols for main parts of the drawings>

110: silicon substrate

120: fence body

130: body separator

150: insulating insulating film (or field insulating film)

160: gate insulating film

170: first gate electrode

180: second gate electrode

190, 192 Source / Drain Area

The present invention relates to a fin field effect transistor having a low leakage current. More specifically, in a fin field effect transistor formed on a bulk silicon substrate among high density DRAM cell devices, a gate electrode using two materials having different work functions is provided. Fin field effect transistor to reduce GIDL (Gate Induced Drain Leakage) by reducing the work function of the region of the gate electrode overlapping the drain region, and to reduce the short channel effect by reducing the width of the body where the channel is formed. And a method for producing the same.

DRAM technology continues to be a major player in the silicon semiconductor market, and is actively researching and developing next-generation DRAMs around the world. In particular, the gate length of DRAM cell devices continues to shrink to reduce cell size and increase integration. The biggest problem in cell device miniaturization is the so-called short channel effect. There is a problem that the drain current in the off state increases due to the short channel effect.

The MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) according to the related art has a channel structure formed on a flat surface, and source / drain regions are formed on both sides of the channel. These conventional flat channel MOSFETs suffer from the short channel effects mentioned above as they are applied to DRAM technology of 100 nm or less. In general, MOS field effect transistors have to be reduced as they shrink, such as decreasing the thickness of the gate insulating layer, decreasing the depth of the source / drain junction, and increasing the channel doping concentration. Due to the gate length reduction, DRAM cell devices have a big problem in miniaturization of cell devices because they cannot reduce the thickness of the gate insulating film and relatively reduce the depth of the source / drain compared to conventional logic MOSFETs. In addition, in order to prevent so-called drain induced barrier lowering (DIBL) as the device shrinks, the doping of the channel must be increased. In this case, the electric field between the channel and the drain increases and the leakage current increases due to band-to-band tunneling. . In the DRAM cell device, the off-state leakage current of the drain current should be approximately 1 fA or less. Therefore, it is expected to reduce the gate length of a cell device to about 70 nm or less with a conventional flat channel MOSFET.

Due to a problem when a device having a conventional flat channel structure is used as a DRAM cell device, a lot of researches are being conducted to overcome this problem. The direction of the study is to study cell structures with device structures in which three-dimensional device structures or channels are no longer flat. Representative devices considered as DRAM cell devices are devices having a recessed channel structure and a bulk FinFET, each of which is described below.

What is important in a memory cell device is to increase the on current and reduce the off current while reducing the cell area on the two-dimensional surface. The recessed channel structure described above is a structure that suppresses short channel effects such as DIBL by lengthening the effective channel while preventing the surface area of the two-dimensional surface from increasing. For example, a recessed channel structure was announced in 2003 by Samsung Electronics for DRAM applications (JY Kim et al., The breakthrough in data retention time of DRAM using recess-channel-array transistor (RCAT) for 88nm feature size). and beyond, in Proc. Symp. on VLSI Tech., p. 11, 2003). The off current can be greatly reduced by suppressing the short channel effect, but the on current due to the relatively long channel length and narrow channel width is greatly reduced. On current reduction has the disadvantage of slowing down the DRAM operation speed. In addition, the recessed channel region may have two corners near the bottom in the channel length direction, and when the channel doping concentration is slightly changed around these corners, the threshold voltage may be greatly changed. These devices typically increase doping only in recessed channel portions, in which case the doping concentration may affect the corner region. A larger problem is that when the recessed width of the recessed channel decreases as the device shrinks, it becomes difficult to control the etch profile near the recessed bottom and the control to uniform the recessed depth becomes difficult. As the depression width decreases, the sensitivity of the threshold voltage increases with the change of the etching profile near the recessed floor. Since the channel structure of the recessed channel device is concave, the back-bias effect occurs seriously, and the NMOS field effect transistor has a problem in that the threshold voltage increases significantly compared to the flat channel for the negative substrate bias. A common feature of recessed channel devices is that the gate electrodes have less control over the channels than flat channel devices, which is related to the greater substrate bias effect.

The structure in which the gate electrode has excellent control over the channel is a double / triple-gate MOS structure in which the gate surrounds the channel region. However, a double / triple-gate (or SOI FinFET) device implemented in an SOI substrate is almost impossible due to the characteristics of the device to be applied as a DRAM cell device. Body-tied double / triple-gate MOSFETs having very high practicality by the present inventors (Korean Patent No. 0458288, Korean Patent No. 0471189, US Patent No. 6885055, Japanese Patent Application No. No. 2003-298051, U.S. Patent Application No. 10/358981, and Japanese Patent Application No. 2002-381448) have been published for the first time in the world, and the present inventors have referred to this structure as a bulk fin field effect transistor (bulk Fin FET). It is called). In the above structure, the channel is not recessed, and the channel is formed on the top and both sides of the active fenced body, or the channel is formed on both sides of the fenced body. Much better than the channel device. Therefore, the device has a high ability to suppress short channel effects and a small DIBL, which is very advantageous for device size reduction. In addition, since the gate electrode has excellent control of the channel, there is little substrate bias effect. When viewed from a two-dimensional surface, the area occupied by the cell is small and the effective channel width is large, effectively increasing the on current, which in turn speeds up the DRAM operation. There are many advantages to applying such a bulk FinFET structure to DRAM cell devices.

However, in general, n ⁺ polysilicon gates are applied to n-type FinFETs. In this case, a low threshold voltage of the device increases the off-state current. Increasing the channel doping to increase the threshold voltage is difficult to increase the channel doping because the leakage current due to band-to-band tunneling between the drain and the channel increases. To overcome this, negative wordline method can be applied, but it is not common and it has the disadvantage of complicated peripheral circuit. To increase the threshold voltage, the work function of the gate can be changed from n ⁺ to p ⁺ , in which case the band warpage increases in the drain region overlapping with the gate electrode, increasing the gate induce drain leakage (GIDL) and eventually increasing the off current. There is a drawback to this.

Accordingly, the present applicant proposes a structure of the present invention to solve the problem that occurs when applying the conventional FinFET to DRAM as described above.

In bulk FinFETs, the nano-sized bodies needed to achieve drain induced reduced barrier (DIBL) below about 100 mV / V should be about two-thirds the gate length. The DIBL of the DRAM cell device must of course be much smaller than 100 mV / V, so the width of the body must be further reduced. When the bulk FinFET structure is applied to DRAM cell devices, reducing the width of the body further reduces the short channel effect, thereby improving device miniaturization.

As mentioned above, when the body width is reduced in the FinFET, when n ⁺ polysilicon is used as the gate electrode, the threshold voltage is lowered and the drain current, that is, the off current increases when the gate voltage is 0V. A simple solution to this problem is solved by increasing the work function of the gate electrode rather than n ⁺ polycrystalline silicon. For example, switching to p ⁺ polysilicon gate increases the threshold voltage, enabling the threshold voltage required by conventional DRAM.

However, in this case, GIDL (Gate Induced Drain Leakage) per channel width at a given surface increases, resulting in a problem of lowering the refresh time of the DRAM cell. There are two main reasons for the increase in GIDL. One is due to the change in band structure in using p ⁺ polysilicon or a high work function gate instead of n ⁺ , and the other is due to an increase in the effective area of overlapping gate electrode and drain per given surface area according to FinFET device structure. .

First, we look at the increase in GIDL by using p ⁺ polysilicon gate instead of n ⁺ polysilicon gate. If the cell element is a NMOS field-effect transistor, n ⁺ is greater as the drain overlapping the p ⁺ polycrystalline silicon gate is the energy band gap of the work function of silicon compared to the n ⁺ drain. Simply looking at the equilibrium with 0V gate bias, the energy band in the drain region must be tilted by the bandgap of silicon to match the gate and Fermi levels. The inclination of the energy band in the n ⁺ drain region overlapping the p ⁺ gate signifies the presence of an electric field, especially because of its large slope. When the three fields are large, electron-hole pairs are created near the surface of the drain region overlapping the gate, and electrons flow to the drain, resulting in a drain current. If the drain voltage increases, the energy band will be tilted further, and the leakage current caused by GIDL will increase.

Next, we look at the increase of the effective area that causes GIDL in FinFET structure. In the case of a conventional flat channel, a given channel width on a two-dimensional surface becomes the actual channel width, and a GIDL corresponding to the channel width is generally acceptable. However, in the FinFET, the channel is formed not only in a given channel width on the two-dimensional surface of the body but also in a part of both sides, and the gate electrode and drain overlap each other along the channel width, thereby increasing the area of GIDL. GIDL per cell is increased. In order to solve this problem, the present invention devised a device structure in which the work function of the gate electrode of a double / triple-gate MOSFET or a FinFET is changed.

In the following, we first review the paper relating to gate work function in the double-gate structures according to the prior art.

The structure presented by S. Tiwari (International Electron Device Meeting, pp. 737-740, 1998) is a silicon on insulator (SOI) device with a work gate directly attached to the side of the main gate. Edo is a double-gate device with a gate having the same work function as the main gate. In this structure, since the side gate is configured in the form of a spacer, the actual gate length is long. In particular, because of the SOI type device structure, it is very unsuitable for application of leakage current sensitive devices such as DRAM. The lower gate is made of the same material as the main gate. This structure is not intended to reduce the GIDL, but is designed to suppress the short channel effect of the device and increase its performance.

The conventional device structure disclosed by GV Reddy (IEEE Trans.on Nanotechnology, vol. 4, no. 2, pp. 260-268, March 2005), etc. shows a double-gate device structure implemented on an SOI substrate. In this structure, half of the upper gate is formed by a main gate having a large work function, the other half is formed by a gate having a small work function, and the lower gate is composed of a gate having a small work function. The upper gate was originally composed of one p ⁺ polysilicon, and by switching half of this gate to n ⁺ , the short channel effect can be further suppressed. In this paper, the SOI substrate is used, and the upper gate uses two materials with different work functions, and the lower gate uses n ⁺ doped single gate structure. Since the lower gate is n ⁺ , the threshold voltage is low, and therefore cannot be applied to DRAM.

The conventional device structure presented by S. Han (IEEE Trans.on Electron Devices, vol. 48, no. 9, pp. 2058-2064, Sep. 2005) has a main gate with a large work function. It is formed by isolation from the insulating film. The gate features a channel that can be easily channeled to the underlying channel, allowing the electrically inverted inversion layer to act as the device's lightly doped drain (LDD). Since the channel structure is a flat channel structure, all of the problems of the conventional flat channel structure are present. Also, there is no need to reduce GIDL, and there is no mention of it.

The existing device structure published by AA Orouji (IEEE Trans. On Device and Materials Reliability, vol. 5, no. 3, pp. 509-514, Sep. 2005) has a double-gate structure. The lower gate of the double-gate is the n ⁺ gate, and the upper gate is the p ⁺ main gate and the n ⁺ side gate electrically isolated from the main gate. In this document, the gate electrode structure described above can improve the short channel effect and suppress the generation of hot carrier. Since it is formed in the SOI substrate, there is a problem with the SOI element. In addition, the upper gate is electrically separated from the side gate having a small work function and the main gate having a large work function, thereby increasing the area of the device in actual device fabrication.

SUMMARY OF THE INVENTION An object of the present invention for solving the above-mentioned problems is to provide a FinFET which can be used as a highly integrated DRAM cell with excellent miniaturization characteristics and minimizing off-state leakage current.

Another object of the present invention is to provide a FinFET using a bulk silicon substrate having a structure capable of reducing a gate induced drain leakage (GIDL) and suppressing a short channel effect while increasing a threshold voltage as a whole.

It is yet another object of the present invention to provide a method of manufacturing the FinFET described above.

Fin field effect transistor having a low leakage current according to a first aspect of the present invention for achieving the above technical problem,

Bulk silicon substrate,

A fence-shaped body formed on the substrate and having a fence shape having a predetermined height and width and a predetermined length;

Is formed in a predetermined region of the upper surface of the fence-shaped body of the channel to be formed of the device, and has a shape of a trench having a predetermined depth and a predetermined width, the interior of the trench is filled with an electrically insulating material, the body separator;

An insulating insulating film made of an electrically insulating material and formed to the first height of the surface of the substrate and the fence body;

A gate insulating film formed on sidewalls and top surfaces of the fence-like body protruding onto the insulating insulating film,

A gate electrode formed on the gate insulating film, the body separating part, and the insulating insulating film, the gate electrode being formed to intersect at an angle with a length direction of the fence body;

A source / drain region formed in an area in which the gate electrode is not formed in the fence body;

The gate electrode includes a first gate electrode and a second gate electrode electrically coupled to the first gate electrode, the second gate electrode having a work function lower than that of the first gate electrode, and the second gate electrode. The gate electrode is formed on one side of the first gate electrode but on the drain region side.

Fin field effect transistor having a low leakage current according to a second aspect of the present invention,

Bulk silicon substrate,

A fence-shaped body formed on the substrate and having a fence shape having a predetermined height and width and a predetermined length;

Is formed in a predetermined region of the upper surface of the fence-shaped body of the channel to be formed of the device, and has a shape of a trench having a predetermined depth and a predetermined width, the interior of the trench is filled with an electrically insulating material, the body separator;

An insulating insulating film made of an electrically insulating material and formed to the first height of the surface of the substrate and the fence body;

A gate insulating film formed on sidewalls and top surfaces of the fence-like body protruding onto the insulating film;

A gate electrode formed on the gate insulating film, the insulating insulating film, and the body separator, the gate electrode being formed so as to intersect at an arbitrary angle with a length direction of the fence body;

A source / drain region formed in an area in which the gate electrode is not formed in the fence body;

The fence body may be separated by the body separator, and the gate electrode may be disposed between a first gate electrode, the second gate electrode, and a gate disposed between the first gate electrode and the second gate electrode. The second gate electrode has a lower work function than the first gate electrode, and the second gate electrode is formed on one side of the first gate electrode via the insulating film between the gates and is formed on the drain region side. do.

Fin field effect transistor having a low leakage current according to a third aspect of the present invention,

Bulk silicon substrate,

A fence-shaped body formed on the substrate and having a fence shape having a predetermined height and width and a predetermined length;

A body separator filled between body regions separated from the top of the fenced body,

An insulating insulating film made of an electrically insulating material and formed to the first height of the surface of the substrate and the fence body;

A gate insulating film formed on sidewalls and top surfaces of the fence-like body protruding onto the insulating film;

A gate electrode formed on the gate insulating film, the insulating insulating film, and the body separator, the gate electrode being formed to intersect at an angle with a length direction of the fence body;

A source / drain region formed in an area in which the gate electrode is not formed in the fence body;

The fence-type body may be separated by the body separator. The gate electrode may include a first gate electrode and second gate electrodes formed on both sides of the first gate electrode. The gate electrodes have a lower work function than the first gate electrode, and the second gate electrode is formed on both sides of the first gate electrode, respectively, and is formed on the source and drain regions, respectively.

Fin field effect transistor having a low leakage current according to a fourth aspect of the present invention,

Bulk silicon substrate,

A fence-shaped body formed on the substrate and having a fence shape having a predetermined height and width and a predetermined length;

Is formed in a predetermined region of the upper surface to form the channel of the element of the fence-shaped body, made of a shape having a trench having a predetermined depth and a predetermined area, the inside of the trench is filled with an electrically insulating material body,

An insulating insulating film made of an electrically insulating material and formed to the first height of the surface of the substrate and the fence body;

A gate insulating film formed on sidewalls and top surfaces of the fence-like body protruding onto the insulating insulating film,

A gate electrode formed on the gate insulating film, the insulating insulating film, and the body separator, the gate electrode being formed to cross at an angle with a length direction of the fence body;

A source / drain region formed in an area in which the gate electrode is not formed in the fence body;

The fence body may be separated by the body separator. The gate electrode may include a first gate electrode, second gate electrodes formed on both sides of the first gate electrode, and the first gate electrode. And insulating layers disposed between the second gate electrode and the second gate electrode, wherein the second gate electrodes have a lower work function than the first gate electrode, and the second gate electrodes have both side surfaces of the first gate electrode. Respectively formed on the source and drain regions.

In the fin field effect transistor having the first, second, third and fourth features described above, the isolation insulating film formed to the first height of the fence body has a thickness of 0.5 nm to 30 nm on the side surface of the substrate and the fence body. It may include a thermal oxide film (first insulating film) formed in the range, and a device isolation film deposited on the thermal oxide film to electrically separate the device from the adjacent device.

In the above-described second and fourth features, an insulating film is formed between the first gate electrode and the second gate electrode and separated from the side, but is electrically connected to each other by a conductive material formed thereon. This conductive material may be formed over the first gate electrode and the second gate electrode in the first and third features described above.

In the fin field effect transistor having the first, second, third and fourth features described above, the isolation insulating film formed to the first height of the fence body may include a thermal oxide film formed on a side surface of the substrate and the fence body; A nitride film formed on the thermal oxide film and a device isolation layer deposited on the nitride film to electrically separate the device from an adjacent device may be included.

In the Fin field effect transistor having the above-described first, second, third and fourth features, the body separator formed to separate the channels formed on both sides of the upper portion of the fenced body is 1 nm to It is formed by etching to a width in the range of 80 nm and a depth in the range of 5 nm to 300 nm from the top of the body and filling the insulating layer in the etched region,

The length separating the upper portion of the fence-shaped body is formed along the entire body region formed with the channel and the source / drain, or is limited to only the body region crossing the gate region, based on both edges in the longitudinal direction of the gate electrode. Longer or shorter formations within the 50 nm range improve the short channel effect of the device.

In the Fin field effect transistor having the above-described first, second, third and fourth features, the corner portion of the upper surface of the fence body is rounded,

The width of the fenced body is generally uniform in the vertical direction, or gradually widens from the top surface of the fenced body to the substrate, or is formed with a uniform width from the top surface to near the first height and gradually from the first height to the substrate. To broaden,

The height of the side channels formed on the side of the fence-like body is preferably determined in the range between 2 nm and 200 nm.

In the Fin field effect transistor having the first, second, third and fourth features described above, the thickness of the gate insulating film formed on the side of the fence-type body of the gate insulating film is 0.5 nm to 10 nm, the fence The thickness of the gate insulating film formed on the upper surface of the type body is preferably formed to be 0.5 nm ~ 200 nm,

The thickness of the gate insulating layer formed on the side and the top of the fence-type body is 0.5 nm to 200 nm inside the channel, and gradually increases the thickness of the gate insulating film toward the source / drain side, but finally 0.6 nm to 201 nm. It is preferable.

 In the Fin field effect transistor having the above-mentioned first, second, third and fourth features, the depth of the source / drain region is preferably 10 nm to 500 nm from the upper surface of the fence body.

In the Fin field effect transistor having the above-mentioned first, second, third and fourth features, the width of the fence body is formed to be uniform in the channel length direction, or the source / except an area crossing the gate electrode. The width of the fenced body of the region where the drain is formed may be wider or narrower than the width of the fenced body of the region crossing the gate electrode. In particular, when the width of the fenced body of the region where the source / drain is formed is wider than the width of the fenced body of the region that intersects the gate electrode, the source / drain resistance can be reduced.

In the Fin field effect transistor having the above-described first, second, third and fourth features, the first gate electrode and the second gate electrode are made of the same material, but the impurity doping type is changed or the work function is It is preferable that the work function of the first gate electrode and the second gate electrode is different from each other by using different materials, or by using different materials and changing the type of impurity doping.

The gate electrode may be polycrystalline silicon, polycrystalline SiGe, polycrystalline Ge, amorphous silicon, amorphous SiGe, amorphous Ge, silicon, or a silicide of semiconductor materials and metals, various metal oxides, metals of various work functions, such as TaN, TiN, WN, etc. It may be made of at least one of binary metals.

In the Fin field effect transistor having the above-described first, second, third and fourth features, the body isolation part forms a gate insulating film on the bottom surface and both sidewalls of the trench, and fills the gate electrode on the gate insulating film to bulk. FinFETs can be configured.

Fin field effect transistor manufacturing method according to a fifth aspect of the present invention,

(a) forming a fenced body of monocrystalline silicon on a bulk silicon substrate,

(b) forming an insulating insulating film from the surface of the bulk silicon substrate to near the surface of the fenced body,

(c) forming a trench having a predetermined depth by etching the center region of the upper portion of the fence body in the longitudinal direction of the body, and forming an insulating insulating film from the surface of the bulk silicon substrate to a first height of the fence body; Exposing a top and side of the body above the height and filling the etched trench with an insulating material to form a body separator;

(d) forming a gate insulating film on side surfaces and top surfaces of the fence-shaped body having a first height or more,

(e) forming a gate electrode on the insulating film and the gate insulating film, wherein the gate electrode comprises a first gate electrode and a second gate electrode having different work functions;

(f) forming a source / drain region in the remaining region of the fenced body except for the region covered by the gate electrode.

(A) The fence body forming step of the FinFET manufacturing method according to the fifth feature described above,

(a1) forming an oxide film, a nitride film, or an oxide film and a nitride film as a hard mask material on a silicon substrate,

(a2) patterning the mask material to form a mask for the fence body;

(a3) Preferably, the silicon substrate is etched using the mask for the fenced body to form a fenced body.

The (b) isolation insulating film forming step of the FinFET manufacturing method according to the fifth feature described above is

(b1) leaving a nitride film used as a hard mask and a thin oxide film formed thereunder on the upper part of the body when forming the fenced body on the substrate,

(b2) performing a process of improving the surface characteristics of the exposed silicon and thermally oxidizing the surface of the bulk silicon substrate and the surface of the fence-like body to form a first insulating film, and

(b3) forming a second insulating film on the first insulating film;

(b4) planarizing the second insulating film and the first insulating film to the surface of the nitride film formed on the fence-type body.

Step (c) of the FinFET manufacturing method according to the fifth feature described above,

(c1) selectively etching a nitride film of a hard mask material (a nitride film and a thin oxide film formed thereon) on the fence body in the step (b);

(c2) depositing a selective insulating film during etching of the fenced body and anisotropically etching to form an insulating film spacer along the edge of the upper surface of the body;

(c3) forming an insulating film (or polysilicon or amorphous silicon) having a predetermined thickness and opening the region where the gate electrode is to be formed as part of the damascene gate process and etching to the upper surface of the fence body to expose the insulating film spacer and between the insulating film spacers. Revealing a portion of the upper surface of the body,

(c4) etching the exposed fenced body upper surface to a depth between 5 nm and 300 nm,

(c5) forming an insulating film on the side of the fence body to the first height;

(c6) performing a process of improving the surface properties of silicon revealed in the step or a process of rounding the upper profile of the body; And

(c7) a process step of filling the region etched in the upper part of the body with an insulating film and exposing the body surface on the upper and side surfaces of the body.

In the process steps (c1) to (c7) for implementing the (c) of the FinFET manufacturing method according to the fifth feature described above, step (c3) may be omitted and may be provided in the same process step.

Etching the upper center of the body shorter than the length of the gate electrode is formed by modifying the step (c3) of the process steps (c1) to (c7) to implement (c) of the FinFET manufacturing method according to the fifth feature described above In the step (c3), an insulating film (or polysilicon or amorphous silicon) having a predetermined thickness is formed, and a region where a gate electrode is to be formed is opened to be etched to the upper surface of the fence body to expose the insulating film spacer and between the insulating film spacers. A portion of the upper surface of the body is exposed, again using an insulating (or conductive) thin film to form a second spacer in the direction in which the gate electrode is to be formed, and again revealing a portion of the upper portion of the body between the spacers and then performing the rest of the process. Can be configured to perform.

In the forming of the gate insulating film (d) of the finFET manufacturing method according to the fifth aspect, the gate oxide film may be formed to have a uniform thickness on the upper surface and the side surface of the exposed fenced body of the first height or more, By considering the oxide film growth, the oxide film is grown thicker on the upper surface relative to the side surface, or the thickness of the gate insulating film formed on the upper surface of the fence body is greater than the thickness of the gate insulating film formed on the side of the fence body. It can be made thick.

 In the forming of the (e) gate electrode of the FinFET manufacturing method according to the fifth aspect, a gate electrode is formed on the insulating film and the gate insulating film, wherein the gate electrode is a drain of the first gate electrode and the first gate electrode. It is preferably made of a second gate electrode connected to the lateral side, the second gate electrode is preferably less work function than the first gate electrode.

The (c) body and isolation insulating film forming step, and (d) the gate insulating film forming step of the FinFET manufacturing method according to the fifth feature described above,

 Sequentially forming a first insulating film, a nitride film, and an insulating insulating film on surfaces of the substrate and the fenced body from which the insulating film is completely removed,

Planarizing to near the surface of the nitride film formed on the upper portion of the fence-like body,

Etching the nitride film by the thickness of the nitride film on the body;

Forming a spacer using an insulating film on the surface at an edge of the upper surface of the body,

Forming an insulating film (or conductive thin film) having a predetermined thickness on the surface and etching the insulating film (or conductive thin film) so that the upper surface of the body is exposed between the spacer and the spacer formed on the body by opening a region where a gate electrode is to be formed. step,

Etching the upper surface of the body exposed from the surface to a depth of between 5 nm and 300 nm and filling the etched region with an insulating film;

Selectively etching the nitride film on the side of the fenced body from a top surface of the fenced body to a first depth,

Etching the first insulating layer on the side of the exposed fenced body to expose the side of the fenced body;

Process steps to improve surface properties with the side of the fenced body exposed;

Forming a gate insulating film on the upper surface and the side of the exposed fenced body to form a similar thickness or thicker at the upper surface of the fenced body.

The (e) gate electrode forming step of the FinFET manufacturing method according to the fifth feature described above,

(e1) forming a polycrystalline silicon film for forming a gate electrode on the gate insulating film;

(e2) doping the polycrystalline silicon film with a high concentration of p ⁺ ,

(e3) forming an insulating film having a predetermined thickness on the doped polycrystalline silicon film;

(e4) etching and patterning the insulating film and the polycrystalline silicon film using a photolithography process;

(e5) It is preferable to include the step of counter-doping the side of the p ⁺ doped polycrystalline silicon film to n ⁺ but do both sides or cover the side exposed to the source side.

The (e) gate electrode forming step of the FinFET manufacturing method according to the fifth feature described above,

(e1) forming a polycrystalline silicon film on the gate insulating film for forming a gate electrode,

(e2) doping the polycrystalline silicon film with a high concentration of p ⁺ ,

(e3) forming an insulating film having a predetermined thickness on the doped polycrystalline silicon film,

(e3) etching and patterning the insulating film and the polycrystalline silicon film using a mask for a gate electrode,

(e4) depositing a thin film of nitride and anisotropically etching to form a nitride film spacer to cover the side of the polysilicon film,

(e5) growing an oxide film having a predetermined thickness in the source / drain region,

(e6) removing the nitride film spacers so that the side surface of p ⁺ polycrystalline silicon is exposed;

(e7) preferably counter-doping the side of the exposed p ⁺ polycrystalline silicon to n ⁺ but both sides or covering the side exposed to the source side.

The (f) source / drain region forming step of the FinFET manufacturing method according to the fifth feature described above,

(f1) After the gate electrode is formed, ion implantation or plasma doping is performed to form a lightly doped drain (LDD), or an ion implantation or plasma doping to form an LDD is performed after forming an insulating film having a predetermined thickness as a spacer. Performing steps,

(f2) forming a spacer using an insulating film,

and (f3) performing ion implantation or plasma doping to form an n ⁺ HDD (Heavily Doped Drain) source / drain.

First preferred embodiment

Hereinafter, a structure of a FinFET having a low leakage current and a method of manufacturing the same will be described in detail with reference to the accompanying drawings.

1 is a perspective view showing a Fin field effect transistor 10 having a low leakage current according to a first preferred embodiment of the present invention. For the convenience of explanation and understanding, a metal layer, a contact, and an insulating layer for wiring of a FinFET device are shown. Only the main parts are shown. (A) is sectional drawing cut along the A-A 'direction, (b) is sectional drawing cut along BB' in the state except the gate electrode, (c) is a top view cut along C-C '.

FinFET 10 according to the first embodiment of the present invention is a substrate 110, the fence body 120, the device isolation layer 150, the gate insulating film 160, the first gate electrode 170, the second gate electrode 180, the source / drain regions 190 and 192 and a body separator 130 separating the upper portion of the fenced body.

The substrate 110 uses a bulk silicon substrate.

The fence body 120 is formed on the substrate 110, and d1 represents the width of the fence body and its width is determined in a range between 2 nm and 200 nm. d7 is the overall height of the fence body 120, and is determined in the range between 50 nm and 900 nm. d2 represents the height of the fence-like body protruding above the device isolation layer 150, and the height is determined in the range between 2 nm and 200 nm, which is the height of the channel formed on the side of the fence-like body 120. Height. On the other hand, in Figure 1 (a) for convenience, the corner of the upper surface of the fence-like body 120 is shown as 90 ° can also be formed in an acute or obtuse angle, and also rounded corners or the upper shape of the semi-circular variety Can be formed. The width of the fence-shaped body separated by the body separator 130 formed on the fence-shaped body 120 is determined in the range of 0.5 nm to 100 nm.

The gate insulating layer 160 is formed to a predetermined thickness on the side and top surfaces of the fence body 120 and the top surface of the body separator 130. In the gate insulating layer 160, the gate insulating layer formed on the side of the fence body 120 is formed to have a thickness between 0.5 nm and 10 nm, and is formed on the upper surface of the fence body 120. Is formed to a thickness between 0.5 nm and 100 nm. In this case, the thickness of the gate insulating layer 160 formed on the upper surface and the side of the fence-like body may be formed uniformly as a whole, and the thicknesses of the upper surface and the side may be different from each other.

In particular, in the gate insulating film 160 formed on the upper surface of the fence-like body 120, the gate insulating film corresponding to the inner region of the channel is formed with a thickness d8 between 0.5 and 100 nm, and toward the source / drain region. The thickness gradually increases, but the thickness is finally between 0.6 nm and 101 nm (d9).

The gate electrode of the FinFET according to the first embodiment of the present invention is composed of a first gate electrode 170 and a second gate electrode 180 having different work functions, and the first gate electrode 170 and the second gate. The electrodes 180 are formed in electrical contact with each other, and d3 represents the total length of the sum of the lengths of the first gate electrode and the second gate electrode.

The first gate electrode 170 is a gate electrode on the source side, and is formed of a material having a larger work function than the material constituting the second gate electrode 180. Therefore, the threshold voltage of the FinFET device according to the present invention is mainly determined by the first gate electrode 170 having a large work function. On the other hand, the second gate electrode 180 is a gate electrode on the drain side, and has a lower work function than the first gate electrode 170, and the length d4 is 1/2 of the length d3 of the entire gate electrode. It is determined in the range smaller than and larger than 0.1 nm.

The first gate electrode 170 and the second gate electrode 180 may be formed of the same material, but the work function of the second gate electrode 180 may be reduced by changing the type of impurity doping. The work function of the second gate electrode 180 may be smaller than the work function of the first gate electrode 170 by different materials of the electrode 170 and the second gate electrode 180. In addition, another embodiment of the gate electrode according to the present invention by varying the material and impurity doping type of the first gate electrode 170 and the second gate electrode 180 to vary the work function of the second gate electrode 180. It may be smaller than the work function of the first gate electrode 170.

The first gate electrode 170 and the second gate electrode 180 may use a semiconductor material such as polycrystalline silicon, polycrystalline SiGe, polycrystalline Ge, amorphous silicon, amorphous SiGe, amorphous Ge, silicon, or Ge, or silicides with various metals, Various metal oxides, metals of various work functions, binary metals such as TaN, TiN, WN, and the like can be used.

The device isolation layer 150, also called an element isolation oxide film or a field oxide film, is formed on the side of the fence body 120 to electrically isolate the device from an adjacent device. The thickness of the device isolation layer 150 is represented by d5, and d5 is determined in the range of 50 nm to 700 nm. The device isolation layer 150 according to the first embodiment of the present invention may be composed of a first insulating film and a second insulating film, wherein the first insulating film is formed on the surface of the silicon substrate on which the fence body is formed and the surface of the fence body. The thermal oxide film may be formed by thermal oxidation, and the second insulating film may be formed by depositing an oxide film on the thermal oxide film.

The source / drain regions 190 and 192 are formed in predetermined regions of the fenced body 120, and are formed on both sides of regions in which the first gate electrode 170 and the second gate electrode 180 are formed. Each is formed. In this case, a portion of the source / drain region may or may not overlap a portion of the first gate electrode and the second gate electrode.

The depth d6 of the source / drain regions 190 and 192 is defined in the vertical direction below the surface of the fenced body, and d6 is determined in the range of 5 nm to 500 nm. In addition, when the source / drain 190 and 192 overlap with the first and second gate electrodes 170 and 180, respectively, the length is 0.1 nm to 30 nm, as indicated by d15 in FIG. Is determined between.

A corner of the portion 'B' where the fenced body 120 and the substrate 110 meet may be formed at a right angle or a round shape.

The upper portion of the fence-like body 120 in the region overlapping the gate electrodes 170 and 180 is formed to be separated by the body separator 130 having a depth between 5 nm and 30 nm and a width between 1 nm and 80 nm. do. The length of the body separator is represented by d14 shown in FIG. 1C, and may be longer or shorter within a range of 50 nm than the length d3 of the entire gate electrode including the first and second gate electrodes. The body separator 130 is preferably formed not to contact the source / drain regions 190 and 192.

Although not shown in FIG. 1, contact regions must be formed in the source / drain and gate electrodes, respectively, for the wiring of the FinFET device. The size of the contact area, which makes it in contact with the metal layer to improve the device integration density and reduce the contact resistance, can be formed to be similar to or larger than the width of the fenced body 120, and if the contact is made larger, source / drain Contact may also be made to a portion of the upper surface and side surfaces of the fenced body where the regions 190 and 192 are formed.

The width of the fenced body where the source / drain regions 190 and 192 are formed is larger than the width of the fenced body below the first and second gate electrodes 170 and 180 to reduce the resistance of the source / drain region. Can be reduced. In the FinFET device according to the present invention, the work function of the second gate electrode 180 is reduced, thereby reducing the electric field from the gate to the fence body in the drain region overlapping the second gate electrode, as well as the horizontal generated from the drain bias. It also reduces the electric field. As a result, the GIDL, which is the object of the present invention, is reduced, and additionally, by reducing the electric field due to the drain voltage, hot carrier generation can also be suppressed, so that durability of the device can be improved.

FIG. 2A is a cross-sectional view taken along the line AA ′ of FIG. 1. Through (a) of FIG. 2, the thickness profile of the gate insulating layer 160 can be seen. In the region where the second gate electrode 180 and the drain region 192 overlap, the thickness d9 of the gate insulating layer 160 is formed to be thick as it goes from the channel to the drain region 192 so that GIDL (Gate Induced Drain Leakage) To reduce Here, the thickness d8 of the gate insulating film in the channel region is determined in the range of 0.5 nm to 100 nm, whereas the thickness d9 of the gate insulating film 160 in the region where the second gate electrode and the drain region overlap is 0.6 nm to Allow it to be determined in the range of 101 nm.

3, the second embodiment of the gate electrode of the FinFET according to the first preferred embodiment of the present invention will be described. The FinFET 20 according to the present embodiment has the same structure and doping as described in FIG. 1 except for the gate electrode.

A feature of the present embodiment is that an insulating film 282 between gates is formed between 0.2 nm and 10 nm between the first gate electrode 270 and the second gate electrode 280. The second gate electrode 280 is formed on the side of the first gate electrode 270, but only on the drain side. The thickness of the insulating film 282 between the gates is indicated by d18 in FIG. 3A. As an example of a manufacturing process for forming this structure, after defining the first gate electrode 270, an insulating film 282 is formed between the gates, the second gate electrode 280 is formed in a spacer shape, and then formed in the source region. The second gate electrode 280 may be removed and formed. When the conductive material is formed on the first gate electrode 270 and the second gate electrode 280, the first and second gate electrodes 270 and 280 are electrically connected to each other.

Hereinafter, with reference to FIG. 4, 3rd Embodiment of the gate electrode of the FinFET which concerns on 1st Example of this invention is described. The FinFET 30 according to the present embodiment has the same structure and doping as described in FIG. 1 except for the gate electrode.

In the present embodiment, the second gate electrode 380 and the third gate electrode 382 are formed on both sides of the first gate electrode 370, respectively. As an example of a manufacturing process for forming this structure, the first gate electrode 370 may be defined, and the second and third gate electrodes 380 and 382 may be formed in the form of a spacer in contact with the first gate electrode. Alternatively, when formed using a polycrystalline semiconductor, first doping with p ⁺ and etching using a gate mask is followed by counter doping with both sides exposed to n ⁺ .

 Hereinafter, with reference to FIG. 5, the 4th Embodiment of the gate electrode of the FinFET which concerns on 1st Example of this invention is described. The FinFET 40 according to the present embodiment has the same structure and doping as described in FIG. 1 except for the gate electrode.

In the present embodiment, the second and third gate electrodes 480 and 482 are formed on both sides of the first gate electrode 470, respectively, but the first gate electrode 470 and the second gate electrode 480 are formed. ) Is formed between the first gate insulating film 472, and the second gate insulating film 484 is formed between the first gate electrode 470 and the third gate electrode 482. The insulating layers 472 and 484 between the first and second gates are formed to have a thickness between 0.2 nm and 10 nm. The thicknesses of the insulating films 472 and 484 between the first and second gates are indicated by d18 in FIG. 5A. As an example of a manufacturing process for forming this structure, after defining the first gate electrode 470, insulating layers 472 and 484 are formed between the first and second gates, and the second and third gate electrodes 480 and 482. Can be formed in the form of a spacer.

Second embodiment

Hereinafter, a FinFET having a low leakage current according to a second embodiment of the present invention will be described in detail. FIG. 6A is a perspective view of the FinFET 50 according to the second embodiment of the present invention, and FIG. 6B is a cross-sectional view taken along the direction B-B 'of a state before the gate electrode is formed. Referring to FIG. 5, the FinFET 50 according to the second embodiment may include a substrate 510, a fenced body 520, a gate insulating film 560, a body separator 530, a first insulating film 542, The nitride layer 540, the second insulating layer 550, the first gate electrode 570, the second gate electrode 580, and the source / drain regions 590 and 592 are included. In the description of the components constituting the FinFET according to the second embodiment, descriptions overlapping with the components of the first embodiment will be omitted for convenience. Meanwhile, various embodiments of the structure of the gate electrode described in the first preferred embodiment described above are applied to the gate electrode of the second embodiment as it is.

The second insulating film 550 is also referred to as a field oxide film as a device isolation film for electrically separating the device from a neighboring device. A nitride film 540 is formed under the isolation insulating film, and a first insulating film is formed below the substrate or the fence body. When the second insulating film 550 is flattened to the surface of the nitride film formed on the upper surface of the fence body and removed by the thickness of the nitride film, a step is formed between the planarized insulating insulating film surface and the top of the body. Using this step, a spacer is formed along the edge of the upper portion of the body with a selectable material for etching the silicon body in the same manner as mentioned in the first preferred embodiment, and the upper surface of the body exposed between the spacers is directed downward. Etching forms a trench and fills the inside of the trench with an insulating material to form a body separator 530. The spacer layer is removed and the exposed nitride layer 540 is selectively etched to a predetermined depth d2 to expose the upper sidewall of the fence body 520. In this case, the thickness d5 of the second insulating film 550 is formed to be 2 nm to 200 nm thicker than that described in the first preferred embodiment, thereby reducing parasitic capacitance. The nitride film 540 may be removed from the upper surface of the fenced body 520 in the vertical direction in the range of 2 nm to 200 nm, so that the upper sidewall of the fenced body 520 may be exposed more clearly. have. The thickness d10 of the nitride film 540 is preferably formed in the range of 2 nm to 200 nm.

Hereinafter, a process of manufacturing the FinFET according to the second embodiment described above will be described schematically. The FinFET fabrication process according to the second embodiment includes forming a fenced body of monocrystalline silicon on a bulk silicon substrate, forming a first insulating film 542 and a nitride film 540 on the structure; 2 planarizing the insulating film 550 to the surface of the nitride film 540 formed on the upper surface of the fence-like body 520, and removing the nitride film by the thickness d10 formed thereon, and then planarizing the insulating insulating film surface and the top of the body. A step is formed between the steps of forming spacers along the upper edge of the fenced body with a material that is selective when etching the fenced body 520 using the step; Forming a trench by etching a predetermined depth of the upper portion in a downward direction to form a trench, and filling the inside of the formed trench with an insulating material to form a body separator 530; Removing the spacers and selectively etching the exposed nitride film 540 to a depth d2, removing the first insulating film on the sidewall of the fenced body, and removing the spacers from the sidewalls and the top surface of the fenced body region protruding above the first insulating film. Forming a gate insulating film on the first and second insulating films, the nitride film, and the gate insulating film, and forming a gate electrode formed of a gate material having a large work function and a gate material having a small work function; Forming a source / drain region in a region of the body except for the region covered by the gate electrode, and forming an insulating layer for electrically isolating the metal layer on the first and second insulating layers, the gate insulating layer, and the gate electrode; Forming a contact on the source, drain, and gate electrodes and forming a metal layer for wiring; The subsequent steps follow the existing steps.

In the second embodiment according to the present invention, the geometry and doping profile of each component except those related to the nitride film 540 are the same as those mentioned in the first preferred embodiment. Also, the damascene gate step described in the first embodiment can be similarly applied to form the device of the structure of the second embodiment.

Third embodiment

Hereinafter, the structure of the FinFET having the low leakage current according to the third embodiment of the present invention will be described in detail with reference to FIGS. 7 and 8. Since the FinFET 60 according to the present embodiment has the same components as those of the above-described first embodiment except for the fenced body structure, redundant description is omitted. In addition, various embodiments of the structure of the gate electrode described in the first preferred embodiment described above are applied to the gate electrode of the third embodiment as it is.

FIG. 7 is a perspective view illustrating a FinFET 60 according to a third embodiment of the present invention, FIG. 8A is a plan view, and FIG. 7B is a cross-sectional view taken along line AA ′ of FIG. 7. c) is a cross-sectional view taken along line B-B 'in FIG. 7, that is, along the body separator 630, and (d) is a plan view taken along line C-C' in FIG. 7. The difference between the third embodiment shown in FIG. 7 and the first embodiment described above is the structure of the fence body 620 and the body separator 630. That is, in the first embodiment, the body separation unit 130 is formed around the fenced body overlapping the gate electrode, but in the third embodiment, the body separation unit 630 is generally formed along the length direction of the fence body. Formed. In FIG. 8D, d17 represents the width of the body separator 630.

The body separating part 630 according to the present exemplary embodiment forms a trench having a predetermined depth as a whole along the longitudinal direction of the fence-shaped body 620 and fills the inside of the trench with an insulating material to complete the trench. Accordingly, channel regions formed on the sidewalls and the upper side of the fenced body under the gate electrode are separated by the body separator 630.

In FIG. 7, for convenience, the first embodiment of the gate electrode in the first embodiment, that is, the same electrode as the gate electrode composed of the first gate electrode and the second gate electrode is shown. Various embodiments of the structure of the gate electrode of the first embodiment can be applied to the third embodiment as it is.

Fourth embodiment

Hereinafter, the structure of the FinFET having the low leakage current according to the fourth embodiment of the present invention will be described in detail with reference to FIG. 9. In the FinFET 70 according to the present embodiment, the rest of the components except for the structure of the fence body are the same as those of the first embodiment described above, and thus redundant description is omitted.

FIG. 9A is a perspective view illustrating the FinFET 70 according to the fourth embodiment of the present invention, and FIG. 9B is a cross-sectional view taken along the line BB ′ except the gate electrode. In FIG. 9A, the gate electrode structure is the same as that of FIG. 1A, and the structure of the gate electrode illustrated in FIG. 3 to 5 may be applied. A trench 730 having a predetermined depth is formed in a predetermined region of the fenced body 720 in the fourth embodiment, and the surface of the trench 730 and the sidewall thereof have the same gate insulating film as the surface of the fenced body. 760 is formed, and a gate electrode is formed on the gate insulating film 760. Therefore, a gate insulating film is formed on the surface and sidewalls of the trench 730 of the FinFET 70 according to the present embodiment, and a gate electrode is formed on the gate insulating film.

According to the present embodiment, the surface area of the channel through which the current can flow can be widened to increase the current driving capability, and the short channel effect can be further improved. However, compared to the first, second, and third embodiments mentioned in the present invention, the overlapping area between the drain region and the gate region is wider, and thus, the GIDL is more likely to increase, resulting in an increase in the leakage current in the off state. As in the present embodiment, the gate electrode as described in the first preferred embodiment is formed with the gate insulating film formed on the surface and sidewalls of the trench instead of forming a trench in the fence body and filling a separate insulating material therein. Various embodiments of the structure may be applied. This structure can also be applied to the second embodiment of FIG. 6 and the third embodiment of FIG.

Meanwhile, according to the present exemplary embodiment, the structure of the body separator in which the gate insulating layer is formed on the lower surface and the sidewall of the trench and the gate electrode is formed on the gate insulating layer may be applied to the body separator of the first to third embodiments.

Various embodiments of fenced body structure

Hereinafter, the structure of the fence body 120 disclosed in the first to fourth embodiments according to the present invention described above will be described in detail.

10 is a cross-sectional view showing two embodiments of the structure of the upper region of the fenced body according to the present invention. Referring to FIG. 10, both (a) and (b) maintain a vertical profile from the top of the fenced body 820 and the body separator 830 to the substrate, and in (a) the top of the fenced body. The corners of the surface are formed at right angles, and (b) shows that the corners of the upper surface of the fence body are rounded. On the other hand, the corners of the upper surfaces of the fenced body 820 and the body separator 830 are more preferably rounded, and in this case, it is possible to improve the durability of the device by preventing the electric field from being concentrated from the gate electrode. .

On the other hand, the body of the fence body 820 is formed perpendicular to the substrate 810, it is preferable that the portion where the substrate 810 and the fence body 820 meet is formed to be round.

The profile of the bottom of the shallow trench of the body separator 830 formed on the top of the fenced body 820 may be formed at right angles or rounded as shown in the figure.

Hereinafter, a profile of the lower region of the fence body 920 according to the present invention will be described with reference to FIG. 11.

11 is a cross-sectional view showing various embodiments of the structure of the lower region of the fenced body 920 according to the present invention. (A) and (b) of FIG. 11 show a profile in which the width of the fence-like body gradually increases linearly while going from the top of the fence-shaped body separated by the body separator 930 to the substrate. It can be widened linearly or nonlinearly as needed. Looking at the upper region of the fenced body 920 separated by the body separator 930 with reference to FIG. 11A, a nearly vertical profile on the side of the body separator 930 filled with insulating material in a shallow trench. On the outside, the width of the fence-type body gradually increases toward the substrate.

Looking at the upper region of the fence-like body 920 separated by the body separation unit 930 with reference to Figure 11 (b), the width of the upper portion of the fence-like body is configured to gradually widen from the top toward the substrate Increasing these widths can increase linearly or nonlinearly.

Referring to (c) of FIG. 11, a profile is formed almost vertically from an upper portion of the fenced body to an area including a region where a channel is formed while going to a substrate, and a profile in which the width of the body gradually increases linearly or nonlinearly thereunder. Is showing. As shown in FIG. 11C, the sidewalls of the upper region of the fenced body in contact with the body separator 930 are formed in a vertical profile.

Referring to FIG. 11D, in the upper region of the fenced body 920 separated by the body separator 930, the upper region of the fenced body in contact with the body separator 930 is directed toward the substrate. Towards gradually become wider.

Meanwhile, the shape of a region where the fenced body 920 and the substrate 910 meet and the bottom of the shallow trench of the body separating part 930 formed on the fenced body shown in FIGS. 11A to 11D are illustrated. The shape of the region is as described in FIG.

First embodiment of the manufacturing process of the FinFET

12 illustrates an example of a process of reducing the work function of the gate electrode toward the drain region when the polysilicon gate is used as a gate material in the present invention. It begins with the assumption that the process before the gate electrode formation is all performed. As an example, a process of forming the first and second gate electrodes described with reference to the cross-sectional view taken along the line AA ′ in FIG. 1 will be described.

Referring to FIG. 12A, a body separator 1030 is formed in a fenced body on a substrate 1010, and source / drain regions 1090 and 1092 are formed on both sides thereof, and on the upper side thereof. The gate insulating film 1060 is formed. A polysilicon 1070 is formed on the gate insulating layer 1060 and doped with p ⁺ to form a first gate electrode, and then a third insulating layer 1012 is formed thereon, and a mask operation for defining the gate electrode is performed. The third insulating film 1012 and the polysilicon 1070 are etched through.

Next, referring to FIG. 12B, the first gate electrode covering the photoresist 1016 and the side surface of which is exposed from the drain 1092 side is countered by a distance d4 to n ⁺ by the same process as plasma ion implantation. Doping to form second gate electrode 1080 is performed. If PR is removed, it is formed as shown in FIG.

Second Embodiment of FinFET Manufacturing Process

Figure 13 shows an example of a process for separating the upper portion of the fence body 1120 in the present invention.

Referring to FIG. 13A, the sixth and fourth insulating layers 1120 and 1130 are formed of a hard mask material for forming a fenced body on the silicon substrate 1110 and a mask operation for forming the fenced body is performed. After forming a living pattern, etching is sequentially performed to form a profile of the fence body 1120.

Next, referring to FIG. 13B, after the appropriate surface treatment process, the insulating insulating film 1150 is formed and the insulating insulating film 1150 is planarized to the surface of the fourth insulating film 1130 which is a hard mask.

Next, referring to FIG. 13C, the spacers 1140 may be formed by selectively removing the fourth insulating layer 1130 and the sixth insulating layer 1120, covering the insulating layer, and anisotropically etching them. The material of the spacer 1140 and the sixth insulating layer 1120 may be formed of the same material.

Next, referring to FIG. 13D, when the upper region of the fenced body 1120 exposed after the formation of the spacer 1140 is etched, a shallow trench is formed, and the region is separated by filling the region with an insulating material. 1130 is formed. The fifth insulating layer 1190 may be additionally formed to protect the upper portion of the fenced body separated in a subsequent process.

Another embodiment of the body separator 1130 of the present invention may be utilized as a channel by forming a thin trench in the upper region of the fenced body and then forming a gate insulating film on the surface and sidewalls of the trench without filling the insulating material. .

Although the present invention has been described above with reference to preferred embodiments thereof, this is merely an example and is not intended to limit the present invention, and those skilled in the art do not depart from the essential characteristics of the present invention. It will be appreciated that many modifications and applications are not possible in the scope. And differences relating to such modifications and applications should be construed as being included in the scope of the invention defined in the appended claims.

14 is a comparison of I _D -V _GS characteristics according to the superstructure of a body in a FinFET having a low leakage current according to the present invention. Referring to FIG. 14, in the FinFET according to the present invention, the total gate length is fixed at 50 nm, the width d12 of the fenced body is 30 nm, and the side channel height d2 of the fenced body is 50 nm. , The substrate concentration is p-type 10 ¹⁷ cm ^-3 , the gate oxide thickness is 3 nm, the width of the separated body at the top (d1) is 10 nm, the length of n ⁺ region of low work function is 15 nm, drain voltage Is fixed at 1.5 V. In addition, a p-type impurity having a peak value of 3 × 10 ¹⁸ cm ⁻³ is doped in the form of a Gaussian function slightly below the distance d2 from the top of the fence body, so that it can be formed by d2 below the fence body. The punchthrough between the source and the drain is suppressed. In FIG. 14, 'NC' is an abbreviation of normal channel, and the upper portion of the fence body is not separated, and 'SC' is the case where all of the upper portions of the fence body are separated as mentioned in FIG. 7. 'LSC' refers to a case in which the body separator 10 is formed within the gate length to separate the upper region of the body, as mentioned in FIG. 1. As shown in FIG. 14, the short channel effect is the best in the case of 'SC', but the leakage current is greatest when the gate voltage is 0 V, that is, in the off state. In case of 'NC', leakage current in off state is good but short channel effect is the most severe among three. In the case of 'LSC' corresponding to FIG. 1 of the present invention, the short channel effect is also suppressed while showing the smallest off current.

As described above, the present invention proposes a structure in which the work function toward the drain region of the gate electrode is relatively lowered and the upper part of the body is separated within the gate length in order to reduce the GIDL current and reduce the short channel effect in the bulk FinFET. In addition, by presenting the modified forms of these structures it can be applied to the basic concept of the present invention according to various process changes. These device structures can be used as DRAM cell devices having a gate length of 50 nm or less in the future.

Claims (31)

Bulk silicon substrates; A fence-type body formed on the substrate and having a fence shape having a predetermined height and width and a predetermined length; A body separator formed in a predetermined region of an upper surface of the fenced body and having a trench having a predetermined depth from the surface of the fenced body, wherein the body separator is filled with a predetermined material in the trench; An insulating insulating film made of an electrically insulating material, the insulating insulating film being formed up to a first height of the surface of the substrate and the fence body; A gate insulating film formed on sidewalls and top surfaces of the fence-like body protruding above the insulating film; A gate electrode formed on the gate insulating film, the insulating insulating film, and the body separator, the gate electrode being formed to intersect at an arbitrary angle with a length direction of the fence-type body; A source / drain region formed in an area of the fenced body where the gate electrode is not formed; And an upper region of the fenced body is separated by the body separator, wherein the gate electrode includes a first gate electrode and a second gate electrode electrically connected to the first gate electrode. Fin field effect transistor with low leakage current. The method of claim 1, wherein the first and second gate electrodes have different work functions, the second gate electrode has a lower work function than the work function of the first gate electrode, and the second gate electrode has the first function. 1 Fin field effect transistor having a low leakage current, characterized in that formed on one side of the gate electrode, but the drain region side. Bulk silicon substrates; A fence-type body formed on the substrate and having a fence shape having a predetermined height and width and a predetermined length; A body separator formed in a predetermined region of an upper surface of the fenced body and having a trench having a predetermined depth from the surface of the fenced body, wherein the body separator is filled with a predetermined material in the trench; An insulating insulating film made of an electrically insulating material, the insulating insulating film being formed up to a first height of the surface of the substrate and the fence body; A gate insulating film formed on sidewalls and top surfaces of the fence-like body protruding above the insulating film; A gate electrode formed on the gate insulating film, the insulating insulating film, and the body separator, the gate electrode being formed to intersect at an arbitrary angle with a length direction of the fence-type body; A source / drain region formed in an area of the fenced body where the gate electrode is not formed; And an upper region of the fenced body is separated by the body separator, wherein the gate electrode includes a first gate electrode, the second gate electrode, and the first gate electrode and the second gate electrode. And a second gate electrode having a lower work function than the first gate electrode, wherein the second gate electrode has one side surface of the first gate electrode through the insulating film between the gates. Fin field effect transistor having a low leakage current, characterized in that formed on the drain region side. Bulk silicon substrates; A fence-type body formed on the substrate and having a fence shape having a predetermined height and width and a predetermined length; A body separator formed in a predetermined region of an upper surface of the fenced body and having a trench having a predetermined depth from the surface of the fenced body, wherein the body separator is filled with a predetermined material in the trench; An insulating insulating film made of an electrically insulating material, the insulating insulating film being formed up to a first height of the surface of the substrate and the fence body; A gate insulating film formed on sidewalls and an upper surface of the fence-like body protruding onto the insulating insulating film, and an upper surface of the body separating part; A gate electrode formed on the gate insulating film, the insulating insulating film, and the body separator, the gate electrode being formed so as to intersect at an arbitrary angle with a length direction of the fence-type body; A source / drain region formed in an area of the fenced body where the gate electrode is not formed; And an upper region of the fenced body is separated by the body separator, wherein the gate electrodes are formed on both side surfaces of the first gate electrode and the first gate electrode, respectively. And second and third gate electrodes having a lower work function than the first gate electrode, and the second and third gate electrodes are formed on both sides of the first gate electrode, respectively. And a fin leakage field effect transistor having a low leakage current, respectively formed on the drain region side. Bulk silicon substrates; A fence-type body formed on the substrate and having a fence shape having a predetermined height and width and a predetermined length; A body separator formed in a predetermined region of an upper surface of the fenced body and having a trench having a predetermined depth from the surface of the fenced body, wherein the body separator is filled with a predetermined material in the trench; An insulating insulating film made of an electrically insulating material, the insulating insulating film being formed up to a first height of the surface of the substrate and the fence body; A gate insulating film formed on sidewalls and top surfaces of the fence-like body protruding onto the insulating film; A gate electrode formed on the gate insulating film, the insulating insulating film, and the body separator, the gate electrode being formed to intersect at an arbitrary angle with a length direction of the fence-type body; A source / drain region formed in an area of the fenced body where the gate electrode is not formed; And an upper region of the fenced body is separated by the body separator, and the gate electrodes are formed on both side surfaces of the first gate electrode and the first gate electrode, respectively. And an insulating film between the gate electrodes and the first and second gates, wherein the insulating film between the first gates is disposed between the first gate electrode and the second gate electrode, and the insulating film between the second gates includes a first insulating film. The second and third gate electrodes have a lower work function than the first gate electrode, and the second and third gate electrodes are disposed between the gate electrode and the third gate electrode. Fin field effect transistor having a low leakage current, characterized in that formed on both sides of the first gate electrode, respectively on the source region and drain region, respectively Emitter. 4. The Fin field effect transistor of claim 3, wherein the insulating film between the gates has a thickness of 0.2 nm to 10 nm. 6. The fin field effect transistor of claim 1, wherein the interior of the body isolation trench is filled with an insulating material. 7. 6. The gate insulating film of claim 1, wherein a gate insulating film is formed on a surface and a sidewall of the trench of the body separation part, and the gate electrode is formed on the gate insulating film. Fin field effect transistor having a low leakage current, characterized in that made of the same material as the gate insulating film formed on the side and the top of the fence body. The body separator according to any one of claims 1 to 5, wherein the length of the body separator that separates the upper portion of the fenced body is formed along a corresponding region of the fenced body in which the channel and the source / drain are formed. Fin field effect transistor having a low leakage current, characterized in that it is formed only in the region of the cross-type fence body, within 50 nm with respect to both edges in the longitudinal direction of the gate electrode. 10. The low leakage of claim 9, wherein the width of the trench in the body separator is determined in the range of 1 nm to 80 nm, and the depth of the trench is determined in the range of 5 nm to 300 nm from the upper surface of the body. Fin field effect transistor with current. The method according to any one of claims 1 to 5, wherein the insulating insulating film A thermal oxide film formed on a side of the substrate and the fence body in a range of 0.5 nm to 30 nm, and And a device isolation film deposited on the thermal oxide film to electrically isolate the device from adjacent devices.  The method according to any one of claims 1 to 5, wherein the insulating insulating film A thermal oxide film formed on a side of the substrate and the fence body in a range of 0.5 nm to 30 nm, A nitride film formed on the thermal oxide film in a range of 2 nm to 200 nm, and And a device insulating film deposited on top of the nitride film to electrically isolate the device from adjacent devices. The method of claim 1, wherein the first gate and the second gate electrode further include a conductive material layer thereon to lower the resistance of the electrode, or the first gate electrode includes the second gate. Fin field effect transistor having a low leakage current, characterized in that formed by electrically connecting them when the electrode is electrically separated. The method of claim 1, wherein the height of the fenced body is in the range of 50 nm to 900 nm from the surface of the substrate, and the overall width of the fenced body is formed in the range of 2 nm to 200 nm. The fin field effect transistor having a low leakage current, characterized in that the width of the upper region of the fence-like body separated by the body separator is formed in the range of 0.5 nm ~ 100 nm. The Fin field effect transistor according to any one of claims 1 to 5, wherein a corner portion of the upper surface of the fence body is rounded. The method according to any one of claims 1 to 5, wherein the width of the fenced body and the total width of the upper portion of the fenced body and the body separator are kept uniform from the upper surface of the body to the substrate, or the fenced body. Fin field effect transistor having a low leakage current, characterized in that it is wider toward the substrate from the upper surface of the, or is formed to have a uniform width from the upper surface to the first height and to extend from the first height to the substrate. 16. The method of claim 15, wherein the width of the upper region of the fenced body separated by the body separator remains uniform from the top surface to the bottom surface of the trench of the body separator, or widens from the top surface to the bottom surface of the trench. Fin field effect transistor having a low leakage current, characterized in that formed on one side of the upper portion of the separated fence-like body widen or both sides widen to the trench lower surface. The Fin field effect with low leakage current according to any one of claims 1 to 5, wherein the height of the side channels formed on the side of the fence body is determined in a range between 2 nm and 200 nm. transistor. The gate insulating film according to any one of claims 1 to 5, wherein a thickness of the gate insulating film formed on a side surface of the fence body is 0.5 nm to 10 nm, and is formed on an upper surface of the fence body. Fin field effect transistor having a low leakage current, characterized in that the thickness of the insulating film is formed from 0.5 nm to 200 nm. The thickness of the gate insulating film formed on the side and the top of the fence-like body is 0.5 nm to 200 nm inside the channel, the thickness of the channel toward the source / drain side Fin field effect transistor having a low leakage current, characterized in that gradually thickening but finally 0.6 nm ~ 201 nm. The Fin field effect transistor of any one of claims 1 to 5, wherein the source / drain region has a depth of 10 nm to 500 nm from an upper surface of the fenced body. The fin having a low leakage current according to any one of claims 1 to 5, wherein an insulating insulating film is formed up to a first height of the fence-shaped body, and the thickness of the insulating insulating film is 50 nm to 700 nm. Field effect transistor. delete The fenced body according to any one of claims 1 to 5, wherein the width of the fenced body is uniformly formed throughout, or the width of the fenced body of the region where the source / drain is formed is the fenced body of the region where the gate electrode is formed. Fin field effect transistor having a low leakage current, characterized in that formed wider than the width of. The method of any one of claims 1 to 5, wherein the first gate electrode and the second gate electrode are composed of the same material, but the impurity doping type is changed, composed of different materials, or composed of different materials. And changing the impurity doping type so that the work functions of the first gate electrode and the second gate electrode are different from each other. The gate electrode according to any one of claims 1 to 5, wherein the gate electrode is made of polycrystalline silicon, polycrystalline SiGe, polycrystalline Ge, amorphous silicon, amorphous SiGe, amorphous Ge, silicon, or silicides of semiconductor materials and metals, various metal oxides. , Fin field effect transistor having a low leakage current, characterized in that made of one or two or more of a metal, a binary metal of various work functions. The second gate electrode of claim 1, wherein the second gate electrode is formed of a material having a lower work function than the first gate electrode, and the length of the second gate electrode is 1/2 of the length of the entire gate electrode. Fin field effect transistor having a low leakage current, characterized in that less than and larger than 0.1 nm. The method of claim 4, wherein the second and third gate electrodes are formed of a material having a lower work function than the first gate gate electrode, and the lengths of the second and third gate electrodes are all. Fin field effect transistor having a low leakage current, characterized in that less than 1/2 of the length of the gate electrode and larger than 0.1 nm. The method of claim 12, wherein the insulating insulating film is formed to be near the upper surface of the fence body, the thermal oxide film and the nitride film is removed from the upper surface of the body to a depth in the range of 2 nm ~ 200 nm, the gate insulating film and the gate Fin field effect transistor having a low leakage current, characterized in that formed by forming an electrode. (a) forming a fenced body of monocrystalline silicon on a bulk silicon substrate, (b) forming an insulating film from the surface of the bulk silicon substrate to near the surface of the fenced body, (c) forming a trench having a predetermined depth by etching the center region of the upper portion of the fence body in the longitudinal direction of the body, and forming an insulating insulating film from the surface of the bulk silicon substrate to a first height of the fence body; Exposing a top and side of the body above the height and filling the etched trench with an insulating material to form a body separator; (d) forming a gate insulating film on side surfaces and top surfaces of the fence-shaped body having a first height or more, (e) forming a gate electrode on the insulating film and the gate insulating film, wherein the gate electrode comprises a first gate electrode and a second gate electrode having different work functions; (f) forming a source / drain region in the remaining portion of the fenced body except for the region covered by the gate electrode; Fin field effect transistor manufacturing method comprising a.  (a) forming a fenced body of monocrystalline silicon on a bulk silicon substrate, (b) sequentially forming a first insulating film, a nitride film, and a second insulating film on the structure; (c) planarizing the second insulating film to the surface of the nitride film formed on the upper surface of the fence body; (d) forming a step between the surface of the second insulating film and the upper portion of the fence-type body by removing the nitride film by the thickness, and using the step to form a fence-shaped body with a material that is selective when etching the fence-type body. Forming a spacer along an upper edge thereof; (e) forming a trench by etching a predetermined depth of an upper portion of the fenced body exposed between the spacers in a downward direction to form a trench, and filling the inside of the formed trench with an insulating material to form a body separator; (f) removing the spacer and selectively etching the exposed nitride film to a predetermined depth, and removing the first insulating film on the sidewall of the fence body; (g) forming a gate insulating film on side and top surfaces of the fenced body region protruding above the first insulating film; (h) forming a gate electrode on the first and second insulating films, the nitride film, and the gate insulating film, wherein the gate electrode is formed of a gate material having a large work function and a gate material having a small work function; (i) forming a source / drain region in a region of the fenced body except for the region covered by the gate electrode; (j) forming an insulating film for electrical isolation from the metal layer on the first and second insulating films, the gate insulating film and the gate electrode; (k) forming a contact on the source, drain and gate electrodes and forming a metal layer for wiring; Fin field effect transistor manufacturing method comprising a.

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