KR100820913B1 - Semiconductor package, manufacturing method and semiconductor package module for image sensor - Google Patents

Abstract

There is provided a semiconductor package, which is light and short, can be simplified, and a semiconductor package according to the present invention includes a semiconductor chip having a plurality of bonding pads formed thereon, spaced apart from a sidewall of the semiconductor chip, and having lower surfaces A plurality of leads lying on substantially the same plane as the bottom surface of the semiconductor chip, a plurality of bonding wires electrically connecting the bonding pads of the semiconductor chip and the plurality of leads, and a bottom surface of the semiconductor chip; An encapsulant for fixing and sealing the semiconductor chip, bonding wires, and leads while exposing the lower surfaces of the leads.

Packages, leads, encapsulants, transparent materials, tapes, singulation

Description

Semiconductor package, method of fabricating the same and semiconductor package module for image sensor

1 is a cross-sectional view showing an example of a conventional ceramic semiconductor package.

2A, 2B, and 2C are plan views, bottom views, and cross-sectional views illustrating a semiconductor package according to an embodiment of the present invention.

3 is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present invention.

4 is a cross-sectional view illustrating a semiconductor package according to still another embodiment of the present invention.

5A is a cross-sectional view illustrating a semiconductor package in accordance with still another embodiment. FIG. 5B is a bottom view of FIG. 5A.

6 is a schematic cross-sectional view showing a package module for an image sensor in which a semiconductor package and a camera holder are coupled according to another embodiment of the present invention.

7 is a plan view of a lead frame for manufacturing a semiconductor package according to embodiments of the present invention.

8A to 8F are cross-sectional views illustrating an example process of manufacturing the semiconductor package of FIG. 3C taken along the line BB ′ of FIG. 7.

* Explanation of symbols on the main parts of the drawings

30; Leadframe 31; Lower Plating Layer

32, 32a; Lead 33; Upper plating layer

34; Semiconductor chip 36; Bonding pad

38; Bonding wire 40; Encapsulant

32b; Die pad 31a; Die Pad Plating Layer

50; Camera holder 52; Camera lens

60; tape

The present invention relates to a semiconductor package. More particularly, the present invention relates to a semiconductor package including a semiconductor chip for an image sensor, a method of manufacturing the same, and a semiconductor package module for an image sensor.

In mounting a package containing a semiconductor chip for a CMOS image sensor (CIS), a photodetector device widely used for a mobile phone camera or a CCD (Charge Coupled Device) camera, which has recently grown rapidly, As demands are gradually increased in functionality and light weight, the research on semiconductor packages suitable as chip size packages is being conducted. As the chip size package for such an image sensor, a ceramic package and a plastic package have been generally used.

1 is a cross-sectional view showing an example of a ceramic package for a conventional image sensor.

Referring to Fig. 1, a semiconductor chip 12 is mounted on the package bottom portion 11a made of a ceramic material by an epoxy adhesive 16. A plurality of bonding pads 12a are formed along the upper edge of the semiconductor chip 12. A plurality of outer leads 15 and inner leads 17 are formed on the package bottom portion 11a. The external leads 15 serve as a contact portion that may be electrically connected to a specific circuit of a printed circuit board (not shown), and the internal leads 17 may include a plurality of bonding pads formed along an upper edge of the semiconductor chip 12. 12a) and a contact portion that can be electrically connected by the bonding wire 13. A package wall portion 11b made of ceramic material is formed while being spaced apart from the semiconductor chip 12, and a transparent plate 14 such as glass or the like is formed above the package wall portion 11b.

However, the conventional ceramic package as described above has a limitation in implementing a light and thin shortening because of its structural complexity, the price of the ceramic package is expensive, there is a limitation that the manufacturing cost is high due to the production of a single unit.

Accordingly, there is a demand for an image sensor semiconductor package that is lighter and shorter than the conventional image sensor semiconductor package, which simplifies the manufacturing process, is advantageous for mass production, and can reduce the production cost.

DISCLOSURE OF THE INVENTION Technical problem to be solved by the present invention is to provide a light and thin semiconductor package in view of the problems of the prior art.

Another technical problem to be achieved by the present invention is to provide a semiconductor package manufacturing method capable of manufacturing the above-mentioned thin and simple semiconductor package of the present invention in a simple and low cost.

Another object of the present invention is to provide a semiconductor package module for an image sensor using the semiconductor package of the present invention, which is light and thin.

According to one aspect of the present invention, there is provided a semiconductor package including a semiconductor chip having a plurality of bonding pads formed thereon, spaced apart from sidewalls of the semiconductor chip, and lower surfaces of the semiconductor chip. A plurality of leads that are substantially coplanar with the bottom surface, the plurality of bonding wires electrically connecting the bonding pads of the semiconductor chip and the plurality of leads, the bottom surface of the semiconductor chip, and the leads An encapsulant for fixing and sealing the semiconductor chip, bonding wires, and leads while exposing a bottom surface thereof.

Preferably, the encapsulant is a transparent material, and the encapsulant may be formed at a height greater than or equal to an upper surface of the leads. In addition, the height of the leads may be higher or lower than the height of the semiconductor chip.

Meanwhile, upper and lower plating layers are further formed on the exposed upper and lower surfaces of the leads, respectively, and the bonding wires are connected to the upper plating layer formed on the upper surface, and a semiconductor chip pad is provided on the lower surface of the semiconductor chip. Is further formed, and the lower surface of the semiconductor chip pad and the lower surface of the leads may be placed on the same plane.

On the other hand, the semiconductor package manufacturing method according to another aspect of the present invention for achieving another technical problem of the present invention, after preparing a lead frame comprising a plurality of leads protruding toward the inner space, the lower surface of the lead frame Stick the tape on. Subsequently, after bonding the semiconductor chip on the exposed tape in the inner space of the lead frame, wire bonding with bonding wires for electrically connecting the leads and the semiconductor chip. Subsequently, after molding the encapsulant to seal the leads, the bonding wires, and the semiconductor chip, the tape is removed from the semiconductor chip.

The method may further include forming an upper plating layer and a lower plating layer on the upper and lower surfaces of the leads, respectively, before attaching the tape to the lower surface of the lead frame, and singulating the lead frame before removing the tape. Can be separated into unit packages.

On the other hand, the semiconductor package module for an image sensor according to another aspect of the present invention for achieving the technical problem of the present invention includes a semiconductor package and a lens holder disposed above the semiconductor package, the semiconductor package is a plurality Bonding pads spaced apart from sidewalls of the semiconductor chip and the plurality of bonding pads, the lower surfaces of the semiconductor chip being substantially coplanar with the lower surface of the semiconductor chip, and bonding pads of the semiconductor chip And a plurality of bonding wires electrically connecting the plurality of leads to the plurality of leads, and an encapsulant for fixing and sealing the semiconductor chip, the bonding wires and the leads while exposing the bottom surface of the semiconductor chip and the bottom surface of the leads. do.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments described below may be modified in many different forms, and the scope of the present invention is not limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In the drawings illustrating embodiments of the present invention, the thicknesses of certain layers or regions are exaggerated for clarity of specification, and like numerals in the drawings refer to like elements. In addition, where a layer is described as being on the "top" of another layer or substrate, the layer may be directly on top of the other layer or substrate, with a third layer intervening therebetween.

2A, 2B, and 2C are plan views, bottom views, and cross-sectional views illustrating semiconductor packages for image sensors according to embodiments of the present disclosure. 2A and 2B, the upper plating layer 33 and the lower plating layer 31 are not shown for convenience of description, and only the reference numbers are given in the reference numbers of the leads 32. In addition, in the plan view, although the encapsulant 40 is covered thereon, the leads 32, the bonding wires 38, the semiconductor chip 34, and the like are shown to show the arrangement of the leads 32. It was. FIG. 2C is a cross-sectional view taken along the line AA ′ of FIG. 2A.

2A to 2C, a semiconductor chip 34 is positioned at the center of the semiconductor package, and a plurality of leads 32 are formed to be spaced apart from each other to surround the semiconductor chip 34. A plurality of bonding pads 36 are formed along the edge of the upper surface of the semiconductor chip 34. The upper plating layer 33 is formed on the upper surface of each lead 32, and the lower plating layer 31 is formed on the lower surface, respectively.

In addition, the upper plating layer 33 and the bonding pads 36 of the semiconductor chip 34 are electrically connected to each other by bonding wires 38, and seal and fix the leads 32 and the semiconductor chip 34. An encapsulant 40 to be formed is formed. As shown in FIG. 2C, the bottom surface of the semiconductor chip 34 and the bottom surface of the leads 32, or the bottom surface of the bottom plating layer 31 formed on the bottom surface of the leads 32 are essentially the same. It is configured to lie on a plane.

The encapsulant 40 is integrally formed, and may be formed using, for example, a transparent epoxy mold compound (EMC), which is a transparent material through which light can pass. In the present embodiment, the height of the lead 32 spaced apart from the semiconductor chip 34 is formed to be at least greater than the height of the upper surface of the semiconductor chip 32.

The semiconductor chip 34 is formed with a CMOS image sensor, which is a light detecting element used in a mobile phone camera or a CCD camera. A plurality of bonding pads 36 may be formed on the upper surface of the semiconductor chip 34 to be electrically connected to an external circuit along an edge thereof. The plurality of bonding pads 36 are electrically connected to upper surfaces of the exposed leads 32 by bonding wires 38. In the present invention, in order to improve the bonding force with the bonding wire 38 made of aluminum, gold, or the like, the upper plating layer 33 made of a metal such as gold (Au), silver (Ag) or an alloy such as NiPd may be used. On the exposed top surface of the field.

On the other hand, a lower plating layer 31 made of the same material as the upper plating layer 33 is formed on the exposed lower surfaces of the leads 32 or to improve solder adhesion with a substrate (not shown) for mounting a semiconductor package. For example, a SnPb solder plating layer may be formed. Instead of the metals such as gold and silver as the upper plating layer 33, a PPF (Pre-Plated Frame) plating layer composed of metal layers such as Ni, Pd and Au is used, and instead of the SnPb solder plating layer as the lower plating layer 31, It is also possible to use a PPF plated layer composed of a metal layer such as Ni, Pd or Au.

3 is a cross-sectional view illustrating a semiconductor package for an image sensor according to another exemplary embodiment of the inventive concept corresponding to FIG. 2C. Referring to FIG. 3, the overall height of the encapsulant 40 is similar to that of FIG. 2C, but the height of the leads 32 disposed around the semiconductor chip 34, or the upper surface of the leads 32. It is different in that it is substantially the same as the surface height of the formed upper plating layer 33. FIG.

4 is a cross-sectional view illustrating a semiconductor package for an image sensor according to another exemplary embodiment of the present invention corresponding to FIG. 2C. Referring to FIG. 4, the overall similarity with that of FIG. 2C, but the height of the leads 32a disposed around the semiconductor chip 34, or the surface of the upper plating layer 33a formed on the upper surface of the leads 32. The height is different in that the case is lower than the surface height of the semiconductor chip 34.

FIG. 5A is a cross-sectional view illustrating a semiconductor package for an image sensor according to another exemplary embodiment of the inventive concept corresponding to FIG. 2C, and FIG. 5B is a bottom view. 5A and 5B, the overall similarity to that of FIGS. 2C and 2B, but the shape of the lead frame is different. That is, the die pad 32b having the same material as the leads 32 but having a lower height than the leads 32 is formed in the space between the leads 32 in the lead frame, and the semiconductor chip 34 is formed by the die pad ( It is mounted by adhesive (not shown) on 32b). Accordingly, when the lower plating layer 31 is formed on the lower surface of the leads 32, the die pad plating layer 31a is formed on the lower surface of the die pad 32b in the same manner. Therefore, in the present exemplary embodiment, the lower surface of the lower plating layer 31 formed on the leads 32 or the lower surface of the leads 32 and the die pad plating layer 31a are positioned on the same plane.

6 is a cross-sectional view schematically illustrating a module in which a semiconductor package and a camera holder are coupled according to another embodiment of the present invention. In the present embodiment, an example in which the semiconductor package shown in FIG. 2C is applied as the semiconductor package is illustrated, but the semiconductor package of another embodiment shown in FIGS. 3 to 5 may be applied.

Referring to FIG. 6, in the package shown in FIG. 2C, the lens holder 50 is adhered with an adhesive (not shown) along the edge of the semiconductor package. The lens 52 for the camera is coupled to the lens holder 50. The semiconductor package to which the lens holder 50 is coupled as described above may be mounted on a substrate (not shown) such as a printed circuit board.

7, a process of manufacturing a semiconductor package according to an embodiment of the present invention will be described in detail with reference to FIGS. FIG. 7 is a plan view of a lead frame for manufacturing the semiconductor package illustrated in FIG. 2C, and FIGS. 8A to 8F illustrate an example of manufacturing the semiconductor package of FIG. 2C taken along the line BB ′ of FIG. 7. The cross-sectional views are shown.

Referring to FIG. 7, a lead frame 30 in which a plurality of unit units are disposed is prepared. The lead frame may use a conductive material such as copper, copper or copper, and other iron and nickel compounds. The unit unit is formed with a plurality of leads 32 extending by a predetermined length toward the inner space 35. The thickness of the lead frame 30, that is, the thickness of the lead 32 of the present invention is preferably larger than the thickness of the semiconductor chip 34, as can be seen in Figure 2c and may be tens to hundreds of micrometers or more. However, in the embodiment of FIG. 4, the thickness of the lead 32a may be lower than the thickness of the semiconductor chip 34.

Referring to FIG. 8A, the upper plating layer 33 and the lower plating layer 31 are formed on the lead frame 30, more specifically, on the upper and lower surfaces of the leads 32 by the same process or separate processes, respectively. do. The upper plating layer 33 is an upper plating layer 33 made of a metal such as gold (Au) or silver (Ag) or an alloy such as NiPd to improve bonding strength with a bonding wire (38 of FIG. 8D) made of aluminum, gold, or the like. ) Is formed on the exposed top surface of the leads 32. On the other hand, a lower plating layer 31 made of the same material as the upper plating layer 33 is formed on the exposed lower surfaces of the leads 32 or to improve solder adhesion with a substrate (not shown) for mounting a semiconductor package. For example, a SnPb solder plating layer may be formed. Instead of the metals such as gold and silver as the upper plating layer 33, a PPF (Pre-Plated Frame) plating layer composed of metal layers such as Ni, Pd and Au is used, and instead of the SnPb solder plating layer as the lower plating layer 31, It is also possible to use a PPF plated layer composed of a metal layer such as Ni, Pd or Au.

Referring to FIG. 8B, an adhesive and flexible tape 60 is attached to the lower surface of the lead frame 30.

Referring to FIG. 8C, the semiconductor chip 34 formed in advance is attached to the inner space 35 formed between the leads 32 for each unit unit of the lead frame 30 (die attaching).

Referring to FIG. 8D, the bonding pads 36 formed on the upper surface of the semiconductor chip 34 and the upper plating layer 33 formed on the upper surface of the leads 32 may be electrically connected to the bonding wires 38. Wire bond.

Subsequently, referring to FIG. 8E, the semiconductor chip 34, the bonding wires 38, and the leads 32 may be molded while using the transparent EMC as the encapsulant 40.

Referring to FIG. 8F, after the molding is completed, the unit semiconductor package of the present invention is completed by removing the tape 60 after performing a singulation process of separating each unit unit using a blade.

The present invention has been described with reference to various embodiments, but the present invention is not limited to the above-described embodiments, and many modifications are possible by those skilled in the art within the technical spirit to which the present invention belongs. Of course. For example, the heights of the leads 32 and the encapsulant 40 may be appropriately selected and used with respect to the thickness of the semiconductor chip 34. Although the transparent epoxy material is used as the encapsulant 40, the present invention Various molding materials can be selected and used as long as it is applicable. 7 to 8F illustrate a process of manufacturing the semiconductor package of the present invention using a lead frame without a die pad, but in order to manufacture the semiconductor package of FIGS. Of course, the same process as described above can be performed using a lead frame having a die pad.

As described above, according to the present invention, it is possible to realize a light and small-sized semiconductor package, the process is very simple and advantageous for mass production.

Claims (14)

A semiconductor chip in which a plurality of bonding pads are formed; A plurality of leads spaced apart from the sidewalls of the semiconductor chip, the lower plating layer being formed on a lower surface, the lower plating layer being substantially coplanar with the lower surface of the semiconductor chip; A plurality of bonding wires electrically connecting the bonding pads of the semiconductor chip and the plurality of leads; And An encapsulant that fixes and seals the semiconductor chip, bonding wires, and leads while exposing the lower plating layer on the lower surface of the semiconductor chip and the lower surface of the leads and the outer surface of the leads; Semiconductor package comprising a. The semiconductor package of claim 1, wherein the encapsulant is a transparent material. The semiconductor package of claim 1, wherein the encapsulant has a height greater than or equal to an upper surface of the leads. The semiconductor package of claim 1, wherein an upper plating layer is further formed on upper surfaces of the leads, and the bonding wires are connected to an upper plating layer formed on the upper surface. The semiconductor package of claim 1, wherein a semiconductor chip pad is further formed on a bottom surface of the semiconductor chip, and a bottom surface of the semiconductor chip pad and a bottom surface of the leads are disposed on the same plane. Preparing a lead frame including a plurality of leads protruding toward an inner space; Attaching a tape to a bottom surface of the lead frame; Bonding a semiconductor chip onto the tape exposed in the inner space of the lead frame; Wire bonding with bonding wires to electrically connect the leads and the semiconductor chip; Molding with encapsulant to seal the leads, bonding wires, and semiconductor chip; And Removing the tape from the semiconductor chip; Semiconductor package manufacturing method comprising a. The method of claim 6, further comprising forming upper and lower plating layers on upper and lower surfaces of the leads, respectively, before attaching the tape to the lower surface of the lead frame. . The method of claim 6, wherein the sealing of the semiconductor chip is performed such that the encapsulant is greater than or equal to the height of the leads. The method of claim 6, wherein the encapsulant is a transparent material. In the semiconductor package module for an image sensor comprising a semiconductor package and a lens holder disposed on the semiconductor package, The semiconductor package, A semiconductor chip in which a plurality of bonding pads are formed; A plurality of leads spaced apart from the sidewalls of the semiconductor chip, the lower plating layer being formed on a lower surface, the lower plating layer being substantially coplanar with the lower surface of the semiconductor chip; A plurality of bonding wires electrically connecting the bonding pads of the semiconductor chip and the plurality of leads; And And an encapsulant for fixing and sealing the semiconductor chip, bonding wires, and leads while exposing the lower plating layer on the lower surface of the semiconductor chip and the lower surface of the leads and the outer surface of the leads. Semiconductor package module for image sensors. A semiconductor chip in which a plurality of bonding pads are formed; Spaced apart from the sidewalls of the semiconductor chip, a lower plating layer is formed on a lower surface, the lower plating layer is substantially coplanar with the lower surface of the semiconductor chip, and the surface height of the upper surface is greater than that of the semiconductor chip. A plurality of leads higher than the surface height; A plurality of bonding wires electrically connecting the bonding pads of the semiconductor chip and the plurality of leads; And An encapsulant that fixes and seals the semiconductor chip, bonding wires, and leads while exposing the lower plating layer on the lower surface of the semiconductor chip and the lower surface of the leads and the outer surface of the leads; Semiconductor package comprising a. The semiconductor package of claim 11, wherein the encapsulant is a transparent material. The semiconductor package of claim 11, wherein the encapsulation material has a height greater than or equal to an upper surface of the leads. The semiconductor package of claim 1, wherein an upper plating layer is further formed on upper surfaces of the leads, and the bonding wires are connected to an upper plating layer formed on the upper surface.

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