KR100818434B1 - Method of forming a dielectric metal film of a semiconductor device - Google Patents
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- KR100818434B1 KR100818434B1 KR1020060083085A KR20060083085A KR100818434B1 KR 100818434 B1 KR100818434 B1 KR 100818434B1 KR 1020060083085 A KR1020060083085 A KR 1020060083085A KR 20060083085 A KR20060083085 A KR 20060083085A KR 100818434 B1 KR100818434 B1 KR 100818434B1
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 20
- 239000002184 metal Substances 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 239000012495 reaction gas Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 239000011800 void material Substances 0.000 abstract description 4
- -1 PMD Substances 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- 239000010410 layer Substances 0.000 description 6
- 238000005137 deposition process Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 239000011734 sodium Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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Abstract
본 발명은 보이드 발생을 방지하는 반도체 소자의 금속전 유전체막(Pre-Metal Dielectric: PMD) 형성 방법에 관한 것이다. 즉, 본 발명에서는 반도체 소자의 금속전 유전체막 형성 방법에 있어서, BPSG막 갭필전에 High O3/TEOS 방식의 USG 막을 일정 두께로 게이트 전극간 절연막으로 형성한 후, USG 상부에 BPSG막을 갭필하여 게이트 소자간 갭필을 수행함으로써, 게이트 전극간 BPSG 갭필막내 보이드 발생이 방지되어 반도체 소자의 신뢰성을 향상시킬 수 있다.
갭필, 보이드, PMD, BPSG, USG
The present invention relates to a method of forming a pre-metal dielectric film (PMD) of a semiconductor device to prevent voids. That is, in the present invention, in the method of forming a metal dielectric film of a semiconductor device, a high O3 / TEOS type USG film is formed as a gate electrode insulating film with a predetermined thickness before the BPSG film gap fill, and then a BPSG film is gap-filled on top of the USG. By performing the inter gap fill, voids in the BPSG gap fill film between the gate electrodes can be prevented, thereby improving the reliability of the semiconductor device.
Gapfill, Void, PMD, BPSG, USG
Description
도 1 및 도 2는 종래 게이트 전극간 갭필된 BPSG막내 보이드 발생 예시도,1 and 2 illustrate examples of void generation in a gapfill BPSG film between gate electrodes;
도 3은 본 발명의 실시 예에 따른 APCVD 방식의 PMD막 증착장치 예시도,3 is a diagram illustrating an APCVD PMD film deposition apparatus according to an embodiment of the present invention;
도 4는 본 발명의 실시 예에 따른 보이드 발생 방지된 BPSG 갭필막 프로파일도.Figure 4 is a void generation prevented BPSG gapfill film profile in accordance with an embodiment of the present invention.
<도면의 주요 부호에 대한 간략한 설명><Brief description of the major symbols in the drawings>
300 : 인젝터 308 : 배플300: Injector 308: Baffle
310 : 웨이퍼 312 : 컨베이어 벨트310
본 발명은 반도체 소자의 금속전 유전체막 형성 방법에 관한 것으로, 특히 보이드 발생을 방지하는 반도체 소자의 금속전 유전체막(Pre-Metal Dielectric: PMD) 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a metal dielectric film of a semiconductor device, and more particularly, to a method of forming a pre-metal dielectric (PMD) of a semiconductor device for preventing voids.
반도체 소자의 제조 공정 중에서 금속전 유전체막(PMD)은 폴리실리콘과 상부 금속 배선의 층간 절연막으로 사용되고 있다. 이러한 금속전 유전체막은 주로 PSG(Phosphors Silicate Glass) 또는 BPSG(Boron-Phosphors Silicate Glass)가 사용되고 있으며, PMD 증착 공정 진행에 의해 발생된 불순물인 나트륨(Na+) 원자의 포획 및 이동을 저지하기 위해서, 위 금속전 유전체막 증착시에 P를 분순물 형태로 첨가하며, 리플로우(reflow) 특성을 향상시키기 위해 B(Boron)와 같은 불순물을 첨가한다.In the process of manufacturing a semiconductor device, a metal dielectric film (PMD) is used as an interlayer insulating film of polysilicon and an upper metal wiring. The metal dielectric layer is mainly composed of PSG (Phosphors Silicate Glass) or BPSG (Boron-Phosphors Silicate Glass), and in order to prevent the trapping and movement of sodium (Na +) atoms, which are impurities generated by the PMD deposition process, P is added in the form of impurities in the deposition of the pre-metal dielectric layer, and impurities such as B (Boron) are added to improve reflow characteristics.
그러나, 최근에는 반도체 소자의 고집적화로 인한 게이트 전극의 간격이 점점 좁아짐에 따라 갭필(gap fill)시에 도 1에서 보여지는 바와 같이 BPSG갭필막에 보이드(void)가 발생하는 문제점이 있으며, 이러한 보이드가 형성된 상태에서 콘택 식각 세정(contact etch clean) 공정을 실시하는 경우 콘택홀(contact hole)과 이웃한 경계막질의 식각이 이루어져 후속공정 진행 시 장벽금속(barrier metal) 및 텅스텐 플러그 증착(W-plug deposition)시에 상기 식각된 빈 공간에 금속 성분이 침투(diffusion)되어 소자의 쇼트 페일(short fail)이 유발되는 문제점이 있었다.However, recently, as the gap between the gate electrodes due to the higher integration of semiconductor devices becomes narrower, voids occur in the BPSG gap fill film as shown in FIG. 1 during the gap fill. Contact etch clean process is performed in the state that is formed, the contact hole and the neighboring boundary layer is etched and barrier metal and tungsten plug are deposited during the subsequent process. There was a problem in that a metal component penetrated into the etched empty space during deposition, causing a short fail of the device.
이를 위해, 종래에는 게이트 전극간 절연을 위한 금속전 유전체막 증착 시 스페이서 질화막(nitride)를 일부 사용하던 방법과는 달리 금속전 유전체막으로 BPSG막만을 이용하여 게이트 전극간 갭필을 수행하는 방법이 제안되었으나, 이 또한 도 2에서 보여지는 바와 같이 여전히 BPSG 갭필막에 보이드가 발생하는 문제점이 있었다. To this end, conventionally, a method of performing a gap fill between gate electrodes using only a BPSG film as a metal dielectric layer is proposed, unlike a method of partially using a spacer nitride layer when depositing a metal dielectric layer for insulation between gate electrodes. However, this also has a problem that voids still occur in the BPSG gapfill film as shown in FIG.
따라서, 본 발명의 목적은 보이드 발생을 방지하는 반도체 소자의 금속전 유전체막(Pre-Metal Dielectric: PMD) 형성 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of forming a pre-metal dielectric film (PMD) of a semiconductor device to prevent voids.
상술한 목적을 달성하기 위한 본 발명은 반도체 소자의 금속전 유전체막 형성방법으로서, (a)게이트가 형성된 반도체 기판상에 질화막을 형성시키는 단계와, (b)상기 질화막 증착된 게이트 전극간 갭필 시 O3/TEOS를 반응가스로 하여 USG막을 일정 두께로 형성시키는 단계와, (c)상기 게이트 전극간 증착된 USG막 상부에 BPSG막을 연속적으로 증착하여 상기 게이트 전극간 갭필을 수행하는 단계를 포함하는 것을 특징으로 한다.The present invention for achieving the above object is a method of forming a dielectric metal film of a semiconductor device, comprising the steps of (a) forming a nitride film on a semiconductor substrate on which a gate is formed, and (b) gap gap between the nitride film deposited gate electrode Forming a USG film to a predetermined
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시 예의 동작을 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the operation of the preferred embodiment according to the present invention.
도 3은 본 발명의 실시 예에 따른 APCVD(Atmosphere Pressure CVD) 방식의 PMD막 증착장치를 도시한 것이다.3 illustrates a PMD film deposition apparatus of an Atmosphere Pressure CVD (APCVD) method according to an embodiment of the present invention.
상기 도 3을 참조하면, APCVD 방식 PMD막 증착장치는 각각의 챔버를 정의하는 복수개의 인젝터(injector)(300, 302, 304, 306)가 구비되어 있으며, 위 인젝터(300, 302, 304, 306) 양측면에는 배플(baffle)(308)이 장착된다.Referring to FIG. 3, the APCVD PMD deposition apparatus includes a plurality of
또한, 위 복수개의 인젝터(300, 302, 304, 306) 하부에는 PMD-BPSG막 증착 공정이 수행되는 웨이퍼(wafer)(310)가 위 복수개의 인젝터(300, 302, 304, 306)가 나열되어 있는 길이방향으로 이동되도록 하기 위한 컨베이어 벨트(conveyor belt)(312)가 설치되어 있다. In addition, a plurality of
동작을 살펴보면, 위 APCVD 방식 PMD막 증착장치는 위 각각의 인젝터(300, 302, 304, 306)에 의해 정의되는 챔버(chamber)내에 공정 가스를 주입하여 BPSG막 증착 공정이 수행되는 방식으로서, 각각의 인젝터(300, 302, 304, 306)에서 BPSG막 형성을 위한 가스를 챔버내로 주입하여 게이트 소자간 BPSG막을 갭필시키게 된다.In operation, the APCVD type PMD film deposition apparatus is a method in which a BPSG film deposition process is performed by injecting a process gas into a chamber defined by each of the
이때, 위 인젝터들(300, 302, 304, 306)에 의해 정의되는 복수개의 챔버들은 배플(308)이라는 장치에 의해 구분되어 지는데, 배플 상단에는 가스 주입구가 구비되어 있어 가스 주입구를 통해 질소 가스가 주입되어 위 배플을 통해 하방으로 분사되며, 분사되는 질소 가스에 의해 일종의 에어 커튼(air curtain)이 형성되어 위 챔버들이 구분되어 지고, 이에 따라, 챔버들간 공정 가스의 혼합이 방지된다.At this time, the plurality of chambers defined by the injectors (300, 302, 304, 306) are divided by a device called a baffle (308), the upper end of the baffle is provided with a gas inlet nitrogen gas through the gas inlet Injected and injected downward through the upper baffle, a kind of air curtain is formed by the injected nitrogen gas to separate the upper chambers, thereby preventing the mixing of process gases between the chambers.
한편, 위와 같은 금속전 유전체막 형성에 있어 종래에는 게이트 소자간 절연을 위한 갭필막으로 BPSG막만을 사용하여 게이트 소자간 BPSG막 갭필 공정을 진행하는 경우 BPSG막내 보이드가 발생하였음은 전술한 바와 같다.On the other hand, in the formation of the above-mentioned metal-electric dielectric film, as described above, voids in the BPSG film are generated when the BPSG film gap fill process between the gate devices is performed using only the BPSG film as a gap fill film for insulating between gate devices.
따라서, 본 발명의 실시 예에서는 금속전 유전체막(PMD)에 O3/TEOS 방식의 USG 막을 사용하여 충진 능력을 향상시키는 방법인 High O3/TEOS SiO2 막질형성으로 BPSG 갭필막에서의 보이드 발생을 방지시키도록 한다. Therefore, in the exemplary embodiment of the present invention, high O3 / TEOS SiO2 film quality is formed by using a USG film of O3 / TEOS type in the PMD to prevent voids in the BPSG gap fill film. To do that.
즉, 위 도 3에서 보여지는 바와 같이, APCVD 방식 PMD막 증착장치의 제1, 제2인젝터(300, 302)에서는 High O3/TEOS 가스를 플로우(flow)하여 USG(Undoped Silicate Glass) 막이 형성되도록 한 후, 제3, 제4인젝터(304, 306)에서는 상기 형성된 USG막 위에 BPSG막 형성을 위한 가스를 플로우하여 BPSG막을 게이트 전극간 갭필이 수행되도록 함으로써 게이트 전극간 갭필(gap fill)되는 BPSG막에서 보이드 가 발생하는 것을 방지시킬 수 있게 된다. 이때 위 게이트 전극간 거리는 0.18∼0.26μm 범위로 설정되고, O3의 농도는, 133g/m3로 설정되며, BPSG막의 타겟 갭필 두께는 8000∼1200Å 범위로 설정된다. That is, as shown in FIG. 3, in the first and
도 4는 High O3/TEOS USG막을 이용하여 BPSG막내 보이드 발생이 억제된 게이트 형성된 반도체 소자의 수직 단면도를 도시한 것으로, 위 도 4에서 보여지는 바와 같이, BPSG막 갭필전에 USG막을 게이트 전극간 절연막으로 형성한 후, BPSG막에 대한 갭필을 진행함에 따라 게이트 전극간 BPSG 갭필막내 보이드 발생이 방지되는 것을 확인할 수 있다. FIG. 4 is a vertical cross-sectional view of a gated semiconductor device in which void generation in a BPSG film is suppressed using a
상기한 바와 같이, 본 발명에서는 반도체 소자의 금속전 유전체막 형성 방법에 있어서, BPSG막 갭필전에 High O3/TEOS 방식의 USG 막을 일정 두께로 게이트 전극간 절연막으로 형성한 후, USG 상부에 BPSG막을 갭필하여 게이트 소자간 갭필을 수행함으로써, 게이트 전극간 BPSG 갭필막내 보이드 발생이 방지되어 반도체 소자의 신뢰성을 향상시킬 수 있게 된다.As described above, in the present invention, in the method of forming a metal dielectric film of a semiconductor device, a high O3 / TEOS type USG film is formed as an inter-gate electrode insulating film with a predetermined thickness before the BPSG film gap fill, and then a BPSG film is formed on the USG. By performing the gap fill between the gate devices, the generation of voids in the BPSG gap fill film between the gate electrodes can be prevented, thereby improving the reliability of the semiconductor device.
한편 상술한 본 발명의 설명에서는 구체적인 실시 예에 관해 설명하였으나, 여러 가지 변형이 본 발명의 범위에서 벗어나지 않고 실시될 수 있다. 따라서 발명의 범위는 설명된 실시 예에 의하여 정할 것이 아니고 특허청구범위에 의해 정하여져야 한다.Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the invention should be determined by the claims rather than by the described embodiments.
이상에서 설명한 바와 같이, 본 발명은 반도체 소자의 금속전 유전체막 형성 방법에 있어서, BPSG막 갭필전에 High O3/TEOS 방식의 USG 막을 일정 두께로 게이 트 전극간 절연막으로 형성한 후, USG 상부에 BPSG막을 갭필하여 게이트 소자간 갭필을 수행함으로써, 게이트 전극간 BPSG 갭필막내 보이드 발생이 방지되어 반도체 소자의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the method of forming a dielectric metal film of a semiconductor device, a high O3 / TEOS type USG film is formed as a gate-to-electrode insulating film with a predetermined thickness before the BPSG film gap fill, and then the BPSG is formed on the USG. By performing gap fill between the gate devices by gap filling the film, voids in the BPSG gap fill film between the gate electrodes can be prevented, thereby improving reliability of the semiconductor device.
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