KR100818239B1 - Nonvolatile Memory Cell Using Mechanical Switch and Its Operation Method - Google Patents

Abstract

The present invention relates to a nonvolatile memory cell using a mechanical switch and a method of operating the same. Non-volatile memory cells using a mechanical switch according to the present invention is a source and drain formed spaced apart from each other in the substrate, an insulating layer formed on the substrate, a floating gate formed on the surface of the insulating layer between the source and drain, A first electrode (Selection gate) formed on the surface of the insulating layer between the source and drain, spaced apart from one side of the floating gate, a second electrode (Control gate) and the second electrode formed on the surface of the insulating layer, spaced apart from the other side of the floating gate And a moving electrode for transferring the potential of the first electrode to the floating gate according to the potential difference between the first electrode and the second electrode.

Description

Non-volatile memory cell using mechanical switch and its operation method {NON-VOLATILE MEMORY CELL USING MECHANICAL SWITCH AND METHOD OF DRIVING THEREOF}

1 illustrates a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention.

FIG. 2 is a simplified diagram of a nonvolatile memory cell using a mechanical switch in accordance with one embodiment of the present invention of FIG.

3 is a view for explaining a write / erase operation method of a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention;

4A to 4B are views for explaining a read operation method of a nonvolatile memory cell using a mechanical switch according to an exemplary embodiment of the present invention.

FIG. 5 is a table illustrating an example of voltage application according to a write / erase / read operation of a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention. FIG.

6A to 6C are diagrams for describing a multi-bit operating method of a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention.

7 is a simplified diagram of a nonvolatile memory cell array using a mechanical switch in accordance with another embodiment of the present invention.

FIG. 8 illustrates a nonvolatile memory cell array using a mechanical switch according to another exemplary embodiment of FIG. 7.

9 is a timing diagram illustrating a write / erase / read operation of a nonvolatile memory cell array using a mechanical switch according to another embodiment of the present invention.

****** Explanation of symbols for the main parts of the drawing ******

101: substrate

102: source

103: drain

104: insulation layer

105: floating gate

106: selection gate

107: second electrode (control gate)

108: moving electrode

109: protrusion

The present invention relates to a nonvolatile memory cell and a method of operating the same. More specifically, the present invention relates to a nonvolatile memory cell using a mechanical switch and a method of operating the same.

Recently, non-volatile memory devices have a smaller device size and a thinner insulating layer, which leads to a reduction in retention time of the charge injected into the floating gate, and to read / write / erase. In operation, there are problems such as a decrease in reliability generated by a current passing through the insulating layer and a need for a high voltage power supply.

In order to solve this problem, a method of directly injecting a charge into a floating gate using a microelectromechanical device has been proposed, as described in US Patent US006054745A. However, performing read / write / erase operations on a nonvolatile memory cell using a microelectromechanical device requires two additional transistors and complicated wiring to select the nonvolatile memory cell. . This not only makes the nonvolatile memory cell larger, it becomes difficult to integrate on the semiconductor substrate, but also has a problem that a circuit for applying a driving voltage for operation becomes complicated.

The present invention to solve this problem is a non-volatile memory cell using a mechanical switch capable of reading / writing / erasing by using a mechanical switch and a field effect transistor (FET) and its operation Provide a method.

In addition, the present invention provides a nonvolatile memory cell using a mechanical switch capable of high integration with a simple wiring structure and a method of operating the same.

In addition, the present invention provides a non-volatile memory cell using a mechanical switch that improves the dispersion characteristics of the threshold voltage when the unit cell is composed of a multi-level cell, and a driving method thereof.

In order to achieve the above technical problem, a nonvolatile memory cell using a mechanical switch according to the present invention includes a source and a drain spaced apart from each other in a substrate, an insulating layer formed on the substrate, and an insulating layer between the source and the drain. A floating gate formed on a surface, spaced apart from one side of the floating gate, a first electrode formed on a surface of the insulating layer between the source and the drain, spaced apart from the other side of the floating gate, A second electrode (Control gate) formed on the surface of the insulating layer and a moving electrode for transmitting the potential of the first electrode to the floating gate according to the potential difference between the first electrode and the second electrode.

Here, the movable electrode is spaced apart from the floating gate and includes a protrusion formed on the movable electrode, one end of the movable electrode is electrically connected to the first electrode, and the other end of the movable electrode is spaced apart from the second electrode. Can be formed.

Here, the protrusion is preferably a dimple.

A method of operating a nonvolatile memory cell using a mechanical switch of the present invention includes applying a first voltage to the first electrode and applying a second voltage to the second electrode.

The first voltage may be a write / erase voltage, the second voltage may be a control voltage, and the absolute value of the potential difference between the write / erase voltage and the control voltage may be greater than or equal to the pull-in voltage Vpi.

Here, the first voltage is a read voltage, the second voltage is a reference voltage, and the absolute value of the potential difference between the read voltage and the reference voltage is preferably less than the pull-in voltage.

In the method of operating a nonvolatile memory cell using a mechanical switch according to the present invention, applying a plurality of first voltage having a different size to the first electrode and applying a second voltage to the second electrode Steps.

Here, the plurality of first voltages are a plurality of write / erase voltages, the second voltage is a control voltage, and the absolute value of the potential difference between the plurality of write / erase voltages and the control voltage is preferably a pull-in voltage or more.

Here, the plurality of first voltages are a plurality of read voltages, the second voltage is a reference voltage, and the absolute value of the potential difference between the plurality of read voltages and the reference voltage is less than a pull-in voltage.

Mechanical formed in an area where the first signal processing line, the second signal processing line, the third signal processing line and the first signal processing line, the second signal processing line and the third signal processing line intersect according to the present invention. A nonvolatile memory cell array using a mechanical switch including a nonvolatile memory cell using a switch, wherein the nonvolatile memory cell using the mechanical switch is electrically connected to the first signal processing line and a source formed spaced apart from each other in a substrate. A drain connected to the substrate, an insulating layer formed on the substrate, a floating gate formed on a surface of the insulating layer between the source and the drain, and spaced apart from one side of the floating gate, A first electrode formed on a surface of an insulating layer and electrically connected to the third signal processing line; The second electrode is spaced apart from the other side of the gate and formed on a surface of the insulating layer, and is electrically connected to the second signal processing line, and according to a potential difference between the first electrode and the second electrode. And a moving electrode transferring the potential of the first electrode to the floating gate.

Here, the movable electrode is spaced apart from the floating gate and includes a protrusion formed on the movable electrode, one end of the movable electrode is electrically connected to the first electrode, and the other end of the movable electrode is spaced apart from the second electrode. Can be formed.

Here, the protrusion is preferably a dimple.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention;

1 is a view illustrating a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention, and FIG. 2 is a simplified diagram of a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention. One drawing. As shown in FIGS. 1 and 2, a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention may include a source 102, a drain 103, and an insulating layer spaced apart from each other in the substrate 101. 104, a floating gate 105, a first electrode 106, a second electrode control gate 107, and a moving electrode 108.

The substrate 101 uses a silicon substrate in one embodiment of the present invention. However, the present invention is not limited thereto, and in general, any substrate that can replace the silicon substrate can be used.

The insulating layer 104 is formed on the substrate 101.

The floating gate 105 and the first electrode 106 are formed to be spaced apart from each other in the surface of the insulating layer 104 between the source 102 and the drain 103. Here, unlike the drawings, the floating gate 105 and the first electrode 106 may be formed on the surface of the insulating layer 104. The floating gate 105 and the first electrode 106 serve as a gate of a field effect transistor (hereinafter, referred to as a FET).

The floating gate 105 may be electrically connected to the first electrode 106 directly by the moving electrode 108 to directly receive a potential applied to the first electrode 106 to store charge. Detailed description thereof will be described in a method of operating a nonvolatile memory cell using a mechanical switch, according to an exemplary embodiment.

As described above, the first electrode 106 corresponds to a gate for controlling the FET and at the same time corresponds to one electrode of a mechanical switch. One end of the moving electrode 108 is electrically connected to the first electrode 106.

The second electrode 107 is formed on the surface of the insulating layer 104 spaced apart from the floating gate 105. The second electrode 107 is preferably formed on the surface of the insulating layer 104, particularly between the source 102 and the drain 103. In addition, the other end of the moving electrode 109 is spaced apart from the second electrode 107.

The moving electrode 108 includes a protrusion 109, one end of which is electrically connected to the first electrode 106, and the other end of which is spaced apart from the second electrode 107. The moving electrode 108 transfers the potential of the first electrode 106 directly to the floating gate 105 according to the potential difference between the first electrode 106 and the second electrode 107. Detailed description thereof will be described in a method of operating a nonvolatile memory cell using a mechanical switch, according to an exemplary embodiment.

The protrusion 109 is formed between the one end and the other end of the moving electrode 108, particularly above the floating gate 105. The protrusion 109 may be formed as a dimple or a stopper.

Hereinafter, a method of operating a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 to 6 are diagrams for describing a write / erase / read operation method of a nonvolatile memory cell using a mechanical switch according to an exemplary embodiment of the present invention. As shown in FIGS. 3 to 6, in a method of writing / erasing / reading a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention, a first voltage is applied to the first electrode 106. And applying a second voltage to the second electrode 107.

First, FIG. 3 is a diagram for describing a write / erase operation method of a nonvolatile memory cell using a mechanical switch according to an exemplary embodiment of the present invention. As shown in FIG. 3, in the write / erase operation, a write / erase voltage is applied to the first electrode 106 as a first voltage, and a control voltage is applied as a second voltage to the second electrode 107. Ensure that the absolute value of the potential difference between the clearing voltage and the control voltage is greater than the pull-in voltage (Vpi). Here, the pull-in voltage Vpi may be defined as a voltage difference between the first electrode 106 and the second electrode 107 which are necessary for the first electrode 106 and the floating gate 105 to electrically conduct. Then, the potential of the write / erase voltage applied to the first electrode 106 forms the same potential to the other end of the movable electrode 108 electrically connected to the first electrode 106, and the movable electrode 108 Since the potential of the control voltage applied to the second electrode 107 spaced below the other end of the second electrode 107 is greater than the pull-in voltage, the other end of the moving electrode 108 and the second electrode 107 are attracted to each other by the electrostatic force. Force is generated. By this force, the first electrode 106 and the floating gate 105 are electrically connected by the protrusion 109 formed on the moving electrode 108 and the potential of the write / erase voltage applied to the first electrode 106. Is transferred to the floating gate 105 so that charge can be stored or erased. At this time, the other end of the moving electrode 108 is not in contact with the second electrode 107 by the protrusion 109.

4A to 4B are views for explaining a read operation method of a nonvolatile memory cell using a mechanical switch according to an exemplary embodiment of the present invention. First, as shown in FIG. 4A, a read operation of a logic '0' having no charge in the floating gate 105 applies a read voltage to the first electrode 106 as a first voltage. A reference voltage is applied to the second electrode 107 as a second voltage so that the absolute value of the potential difference between the read voltage and the reference voltage is less than the pull-in voltage. Thus, since the other end of the movable electrode 108 electrically connected to the first electrode 106 and the second electrode 107 do not have a pull-in voltage or more, an electrostatic force does not occur, and the protrusion 109 is a floating gate 105. Is not directly connected electrically. In this case, an electron channel is generated in the region between the source 102 and the drain 103 under the first electrode 106, but is floating in the region between the source 102 and the drain 103 under the floating gate 105. Since no charge is present in (), an electron channel is not generated and current does not flow between the source 102 and the drain 103.

Next, as shown in (b) of FIG. 4, the read operation of logic '1' in which the charge is present in the floating 105 is also similar to the operation method of FIG. A read voltage is applied as the first voltage to the electrode 106 and a reference voltage is applied as the second voltage to the second electrode 107 so that the absolute value of the potential difference between the read voltage and the reference voltage is less than the pull-in voltage. Thus, no electrostatic force is generated between the other end of the moving electrode 108 and the second electrode 107 electrically connected to the first electrode 106, and the protrusion 109 is not directly connected to the floating gate 105. . However, the logic '1' is a state in which charge is present in the floating gate 105 unlike the logic '0' shown in FIG. 4A, and thus, between the source 102 and the drain 103. Electron channels are created and current flows.

FIG. 5 is a table illustrating an example of voltage application according to a write / erase / read operation of a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention. As shown in FIG. 5, during a write operation, a write voltage Vwirte is applied to the first electrode and a control voltage VCC is applied to the second electrode, and erase is erased. In operation, the erase voltage (0V) is applied to the first electrode, and the control voltage (VCG) is applied to the second electrode. In the read operation (Read '0', Read '1'), the read voltage (Vread) is applied to the first electrode. The reference voltage (0V) is applied to the second electrode. Then, the write / erase / read operation of the nonvolatile memory cell using the mechanical switch according to an embodiment of the present invention shown in FIGS. 3, 4 (a) and 4 (b) may be performed. .

As described above, a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention can perform both write / erase / read operations using only one mechanical switch and one FET, and is nonvolatile. The degree of integration of the memory device can be further increased.

6A to 6C are diagrams for describing a multi-bit operating method of a nonvolatile memory cell using a mechanical switch according to an exemplary embodiment of the present invention.

In the multi-bit operating method of a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention, a method of applying a plurality of first voltages having different sizes to a first electrode and a second voltage to the second electrode are provided. The step of applying a.

First, a write / erase operation method applies a plurality of write / erase voltages as a first voltage to a first electrode and a control voltage as a second voltage to a second electrode. Here, the absolute value of the potential difference between the plurality of write / erase voltages and the control voltage is equal to or greater than the pull-in voltage.

Next, the read operation method applies a plurality of read voltages as a first voltage to the first electrode and a control voltage as a second voltage to the second electrode. Here, the absolute value of the potential difference between the plurality of read voltages and the control voltage is made less than the pull-in voltage. Hereinafter, a multi-bit operating method will be described with reference to FIGS. 6A to 6C.

FIG. 6A is a diagram showing the structure of a flash memory cell well known in the art. As shown in FIG. 6A, when the voltage applied to the control gate connected to the wordline is properly adjusted, the amount of charge injected to the floating gate can be controlled. Accordingly, the threshold voltage of the MOS field effect transistor (hereinafter referred to as a "MOSFET") can be controlled. However, in general, since the charges injected into the floating gate cannot be accurately determined, the threshold voltages of the MOSFETs of all the memory devices cannot be controlled to the correct values.

However, as shown in (b) of FIG. 6, since the MOSFET has a normal distribution of threshold voltages, the memory is divided into multilevels by dividing states (phases 1 to 3) within a range where the normal distribution curves do not overlap. Can drive. At this time, reducing the standard deviation of each normal distribution for each state (phase 1 to 3) divided according to the normal distribution of the threshold voltage is known as one of the biggest difficulties in implementing a multi level flash memory.

플랑크 상수(Plank's constant),

주입장벽(Injection barrier),

단일 전자의 전하량(the charge of a single electron),

자유전자의 질량(the mass of a free electron),

실리콘산화막의 밴드갭에서 전자의 유효질량(the effective mass of an electron in the band gap of SiO₂),

h/2π,

산화막을 통과하는 실제의 전압(the voltage applied across the oxide),

플랫밴드전압(the flat band voltage),

절연층의 두께 편차(the thickness of the oxide) 이다.here,

Plank's constant,

Injection barrier,

The charge of a single electron,

The mass of a free electron,

The effective mass of an electron in the band gap of SiO ₂ ,

h / 2π,

The voltage applied across the oxide,

The flat band voltage,

The thickness of the oxide.

Referring to Equations 1 and 2, it is difficult to reduce the standard deviation of the normal distribution because of the Fowler-Nordheim tunneling or the channel hot carrier effect, which is a widely used electron injection method. Effect) is very sensitive to the thickness variation Δtox of the insulating film resulting from the process deviation of the device.

However, in a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention, electrons are not injected through the insulating layer into the floating gate, but are floated by a direct contact method between the first electrode and the floating gate of the mechanical switch. By injecting electrons into the gate, it is possible to eliminate the influence of the thickness variation ((Δtox)) of the insulation layer, which is severe in the FN tunneling method or the Channel Hot Carrier Effect, and to reduce the standard deviation of the threshold voltage distribution between states. The number of Vth population characteristics can be improved.

Therefore, as shown in FIG. 6C, write voltages having four different magnitudes are applied to the first electrode to have four threshold voltages Vth, thereby providing logic ('00', '01', In addition, in the case of a read operation, when the read voltages Vread applied to the first electrode are divided into three (Vread1, Vread2, and Vread3), the present invention may be stored in the embodiment of the present invention. The nonvolatile memory cell using the mechanical switch can be implemented in a multi-bit.

7 is a simplified diagram of a nonvolatile memory cell array using a mechanical switch according to another embodiment of the present invention, and FIG. 8 is a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention of FIG. It is a figure which embodied the array.

First, as shown in FIG. 7, a nonvolatile memory cell array using a mechanical switch according to another embodiment of the present invention may include a first signal processing line 210, a second signal processing line 220, and a third signal. Non-volatile memory cell 240 using a mechanical switch formed in a region where the processing line 230 and the first signal processing line 210, the second signal processing line 220 and the third signal processing line 230 intersect. It includes. Here, the nonvolatile memory cell 240 using a mechanical switch may be formed using a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention shown in FIGS. 1 to 2. Referring to FIG. 8, a nonvolatile memory cell array using a mechanical switch according to another embodiment of the present invention will be described in detail.

As shown in FIG. 8, a nonvolatile memory cell array using a mechanical switch according to another embodiment of the present invention is electrically connected to a source 202 and a first signal processing line 210 formed spaced apart from each other in a substrate. The drain 203, an insulating layer formed on the substrate, a floating gate 205 formed on the surface of the insulating layer between the source 202 and the drain 203, and spaced apart from one side of the floating gate 205, and It is formed on the surface of the insulating layer between the 202 and the drain 203, spaced apart from the other side of the first electrode (Selection gate, 206), floating gate 205 electrically connected to the third signal processing line 230 And a second electrode formed on the surface of the insulating layer and electrically connected to the second signal processing line 220 and according to a potential difference between the first electrode 206 and the second electrode 207. The moving electrode 208 transfers the potential of the first electrode 206 to the floating gate 205.

Here, each of the first signal processing line 210, the second signal processing line 220, and the third signal processing line 230 is a first bit processing line 210 as a reading bit line (Reading B / L). The second signal processing line 220 is used as a writing bit line (Writing B / L), and the third signal processing line 230 is used as a word line (W / L) for unit cell selection.

Hereinafter, a method of operating a nonvolatile memory cell array using a mechanical switch according to another exemplary embodiment of the present invention will be described in detail with reference to FIG. 9.

9 is a timing diagram illustrating a write / erase / read operation of a nonvolatile memory cell array using a mechanical switch according to another exemplary embodiment of the present invention.

First, FIG. 9A is a timing diagram illustrating a write operation of a nonvolatile memory cell array using a mechanical switch according to another exemplary embodiment of the present invention. As shown in Fig. 9A, the voltage Vhigh is applied to the write bit line as the second signal processing line, and the voltage corresponding to Vhigh-Vpi is applied to the word line as the third signal processing line. Then, since the potential difference between the voltage of the first electrode electrically connected to the third signal processing line and the voltage of the second electrode electrically connected to the second signal processing line is equal to or greater than the pull-in voltage Vpi, the first electrode is connected to the floating gate. The amount of charge corresponding to the voltage Vhigh applied to is stored.

9B is a timing diagram illustrating an erase operation of a nonvolatile memory cell array using a mechanical switch according to another exemplary embodiment of the present invention. As shown in Fig. 9B, a voltage of 0V is applied to the write bit line as the second signal processing line, and a voltage corresponding to -Vpi is applied to the word line as the third signal processing line. Then, since the potential difference between the voltage of the first electrode electrically connected to the third signal processing line and the voltage of the second electrode electrically connected to the second signal processing line is equal to or greater than the pull-in voltage Vpi, the floating gate has no charge. It does not exist.

9C to 9D are timing diagrams illustrating a read operation of a nonvolatile memory cell array using a mechanical switch according to another exemplary embodiment of the present invention. As shown in Figs. 9C to 9D, a voltage corresponding to Vread is applied to the word line as the third signal processing line. If there is no charge in the floating gate ((c) of FIG. 9, the voltage (VFG) = 0V of the floating gate) does not form a channel between the source and the drain, and thus no current flows. If charge is present in the gate ((d) of FIG. 9, VFG = 1V), a channel is formed between the source and the drain, so that current flows.

As described above, since the nonvolatile memory cell array using the mechanical switch according to another embodiment of the present invention includes a nonvolatile memory cell using a mechanical switch and one FET, The unit cell may be selected by the first electrode 206 connected to the word line W / L as the third signal processing line, and at the same time, it may serve as a gate of the FET. This eliminates the need for additional devices for unit cell selection and simplifies wiring, further increasing integration.

As described above, those skilled in the art to which the present invention pertains will understand that the present invention may be implemented in other specific forms without changing the technical spirit or essential features. Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the following claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

As described in detail above, according to the present invention, a nonvolatile memory cell using a mechanical switch capable of reading / writing / erasing using one mechanical switch and one FET and a method of operating the same can be provided.

In addition, the present invention can provide a nonvolatile memory cell using a mechanical switch that can be highly integrated with a simple wiring structure and an operation method thereof.

In addition, the present invention does not use the electron injection method by the FN tunneling or Channel Hot Carrier Effect when the unit cell is configured as a multi-level cell, so that the non-volatile memory cell using a mechanical switch can improve the dispersion characteristics of the threshold voltage. And a driving method thereof.

Claims (12)

A source and a drain formed spaced apart from each other in the substrate; An insulating layer formed on the substrate; A floating gate formed on a surface of the insulating layer between the source and the drain; A first electrode spaced apart from one side of the floating gate and formed on a surface of the insulating layer between the source and the drain; A second electrode spaced apart from the other side of the floating gate and formed on a surface of the insulating layer; And A moving electrode transferring the potential of the first electrode to the floating gate according to the potential difference between the first electrode and the second electrode. Non-volatile memory cell using a mechanical switch, including. The method of claim 1, The moving electrode, A mechanical switch spaced apart from the floating gate, wherein one end of the movable electrode is electrically connected to the first electrode, and the other end of the movable electrode is spaced apart from the second electrode to form a mechanical switch Nonvolatile memory cell using. The method of claim 2, The protrusion, Non-volatile memory cells with dimpled, mechanical switches. In the method of operating a nonvolatile memory cell using a mechanical switch according to claim 1, Applying a first voltage to the first electrode; And Applying a second voltage to the second electrode A method of operating a nonvolatile memory cell using a mechanical switch comprising a. The method of claim 4, wherein The first voltage is a write / erase voltage, the second voltage is a control voltage, and the absolute value of the potential difference between the write / erase voltage and the control voltage is greater than or equal to the pull-in voltage (Vpi). How Cells Work The method of claim 4, wherein Wherein the first voltage is a read voltage, the second voltage is a reference voltage, and an absolute value of a potential difference between the read voltage and the reference voltage is less than a pull-in voltage. In the method of operating a nonvolatile memory cell using a mechanical switch according to claim 1, Applying a plurality of first voltages having different sizes to the first electrode; And Applying a second voltage to the second electrode A method of operating a nonvolatile memory cell using a mechanical switch comprising a. The method of claim 7, wherein The plurality of first voltages are a plurality of write / erase voltages, the second voltage is a control voltage, and the absolute value of the potential difference between the plurality of write / erase voltages and the control voltage is greater than a pull-in voltage. A method of operating a nonvolatile memory cell. The method of claim 7, wherein Wherein the plurality of first voltages are a plurality of read voltages, the second voltage is a reference voltage, and an absolute value of a potential difference between the plurality of read voltages and the reference voltage is less than a pull-in voltage. How to operate. By using a mechanical switch formed in an area where the first signal processing line, the second signal processing line, the third signal processing line and the first signal processing line, the second signal processing line and the third signal processing line intersect. In a nonvolatile memory cell array using a mechanical switch including a nonvolatile memory cell, The nonvolatile memory cell using the mechanical switch, A source electrically spaced apart from each other in the substrate and a drain electrically connected to the first signal processing line; An insulating layer formed on the substrate; A floating gate formed on a surface of the insulating layer between the source and the drain; A first electrode spaced apart from one side of the floating gate and formed on a surface of the insulating layer between the source and the drain and electrically connected to the third signal processing line; A second electrode spaced apart from the other side of the floating gate, formed on a surface of the insulating layer, and electrically connected to the second signal processing line; And A moving electrode transferring the potential of the first electrode to the floating gate according to the potential difference between the first electrode and the second electrode. Non-volatile memory cell array using a mechanical switch comprising a. The method of claim 10, The moving electrode, And a protrusion formed on the movable electrode spaced apart from the floating gate, one end of the movable electrode is electrically connected to the first electrode, and the other end of the movable electrode is spaced apart from the second electrode. Nonvolatile Memory Cell Array Using Switch. The method of claim 11, The protrusion, Non-volatile memory cell array using dimple, mechanical switch.

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