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KR100808586B1 - Stacked Package - Google Patents

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Publication number
KR100808586B1
KR100808586B1 KR1020050110707A KR20050110707A KR100808586B1 KR 100808586 B1 KR100808586 B1 KR 100808586B1 KR 1020050110707 A KR1020050110707 A KR 1020050110707A KR 20050110707 A KR20050110707 A KR 20050110707A KR 100808586 B1 KR100808586 B1 KR 100808586B1
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rearrangement
chips
stacked
substrate
chip
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KR20070052911A (en
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한권환
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

개시된 적층형 패키지는, 기판과, 기판 상에 적층되며, 재배열층이 마련된 다수의 재배열 칩과, 다수의 재배열 칩 양측에 각각 결합되며, 다수의 재배열 칩을 서로 전기적으로 연결하기 위하여 다수의 재배열층 각각에 접촉된 다수의 솔더 볼이 마련된 배선 칩 및 기판과 다수의 재배열 칩을 전기적으로 연결하는 와이어를 포함함으로써, 적층되는 다수의 재배열 칩 사이를 전기적으로 연결하기 위하여 각각의 재배열 칩 사이에 본딩 공간을 형성하지 않아도 되므로 그만큼 두께가 감소하는 장점이 있으며, 따라서 적층되는 재배열 칩의 수도 증가할 수 있어 적층형 패키지의 고용량, 고성능화 및 본딩을 개별적으로 하지 않아도 되므로 공정 수율이 향상되는 효과를 제공한다.The disclosed stacked package includes a substrate, a plurality of rearrangement chips stacked on the substrate and provided with rearrangement layers, respectively coupled to both sides of the plurality of rearrangement chips, and a plurality of rearrangement chips to electrically connect the plurality of rearrangement chips to each other. A wiring chip provided with a plurality of solder balls in contact with each of the rearrangement layers of the substrate, and a wire electrically connecting the substrate and the plurality of rearrangement chips. Since there is no need to form a bonding space between the rearranged chips, the thickness can be reduced. Thus, the number of rearranged chips to be stacked can be increased, thereby increasing the process yield since the high capacity, high performance, and bonding of the stacked package are not required. Provides an improved effect.

Description

적층형 패키지{Stack type package}Stack type package

도 1은 종래의 적층형 패키지를 나타낸 단면도,1 is a cross-sectional view showing a conventional stacked package,

도 2는 본 발명의 일 실시예에 따른 적층형 패키지를 나타낸 단면도,2 is a cross-sectional view showing a stacked package according to an embodiment of the present invention;

도 3은 도 2의 배선 칩을 나타낸 평면도,3 is a plan view showing the wiring chip of FIG.

도 4a 내지 도 4f는 도 2의 배선 칩을 제조하는 방법을 순차적으로 나타낸 단면도,4A to 4F are cross-sectional views sequentially illustrating a method of manufacturing the wiring chip of FIG. 2;

도 5는 본 발명의 또 다른 실시예에 따른 적층형 패키지를 나타낸 단면도.5 is a cross-sectional view showing a stacked package according to another embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

100,200... 적층형 패키지 110... 기판100,200 ... Stacked Package 110 ... Board

120... 재배열 칩 121... 재배열층120 ... rearrangement chip 121 ... rearrangement layer

130... 배선 칩 136... 솔더 볼130 ... wiring chip 136 ... solder ball

본 발명은 적층형 패키지에 관한 것으로서, 특히 전체적인 패키지 두께를 줄일 수 있는 적층형 패키지에 관한 것이다.The present invention relates to a laminated package, and more particularly, to a laminated package capable of reducing the overall package thickness.

최근 전자 산업의 발전으로 거의 대부분의 전자 제품에 반도체를 사용하게 되면서 다양한 크기와 형태를 가진 반도체 패키지가 요구되고 있다.Recently, due to the development of the electronics industry, semiconductors having various sizes and shapes are required as semiconductors are used for almost all electronic products.

특히 소형 가전이나 모바일 제품군에서 사용되는 반도체의 경우 실장 면적을 최소화해야 하며, 고성능 반도체의 성능에 부합하는 고성능 반도체 패키지가 요구되고 있다.In particular, semiconductors used in small home appliances or mobile products have to minimize the mounting area, and high-performance semiconductor packages are required to meet the performance of high-performance semiconductors.

이러한 요구를 만족하며, 고집적화하기 위해 도 1과 같이 수직으로 칩을 적층하는 적층형 패키지가 출현하였다.In order to satisfy this demand and to integrate highly, a stacked package in which chips are stacked vertically as shown in FIG. 1 has emerged.

이 적층형 패키지(60)는 기판(10) 상에 다수의 칩(20)이 접착 테입(30)을 매개로 적층되며, 칩(20) 양단부에 마련된 칩 패드(21)를 통해 기판과 전기적으로 연결되도록 와이어(40) 본딩된다.In the stacked package 60, a plurality of chips 20 are stacked on the substrate 10 through an adhesive tape 30 and electrically connected to the substrate through chip pads 21 provided at both ends of the chip 20. The wire 40 is bonded so as to.

그런데, 이와 같은 구조의 적층형 패키지(60)는 동일한 칩(20)을 적층하는 경우, 칩 패드(21)가 상층에 적층되는 칩(20)에 의하여 가려지기 때문에, 와이어(40) 본딩을 위해서 적층되는 칩(20)들 간에 일정한 간격의 공간이 필요하여, 결국 적층형 패키지(60)의 전체 두께가 두꺼워져 적층되는 칩(20)의 개수에 한계가 있게 되고, 적층되는 칩(20) 마다에 와이어(40) 본딩을 해야 하기 때문에, 공정 수율이 칩을 적층할수록 낮아지는 문제점이 있다.However, the stacked package 60 having such a structure is stacked for bonding the wire 40 because the chip pad 21 is covered by the chip 20 stacked on the upper layer when the same chip 20 is stacked. Space between the chips 20 is required, so that the overall thickness of the stacked package 60 becomes thick, thereby limiting the number of chips 20 to be stacked, and wires for every chip 20 to be stacked. (40) Since bonding has to be performed, there is a problem that the process yield is lower as the chips are stacked.

미설명 부호 50은 EMC이다.Reference numeral 50 is EMC.

본 발명은 상기의 문제점을 해결하기 위하여 창출된 것으로서, 패키지 전체의 두께를 줄이고, 공정 수율을 향상시킬 수 있는 개선된 적층형 패키지를 제공하는 것을 그 목적으로 한다.The present invention has been made to solve the above problems, and an object thereof is to provide an improved laminated package that can reduce the thickness of the whole package and improve the process yield.

상기의 목적을 달성하기 위한 본 발명의 적층형 패키지는, 기판; 상기 기판 상에 적층되며, 재배열층이 마련된 다수의 재배열 칩; 상기 다수의 재배열 칩 양측에 각각 결합되며, 상기 다수의 재배열 칩을 서로 전기적으로 연결하기 위하여 상기 다수의 재배열층 각각에 접촉된 다수의 솔더 볼이 마련된 배선 칩; 및 상기 기판과 상기 다수의 재배열 칩을 전기적으로 연결하는 와이어를 포함한 것이 바람직하다.Laminated package of the present invention for achieving the above object, the substrate; A plurality of rearrangement chips stacked on the substrate and provided with rearrangement layers; A wiring chip coupled to both sides of the plurality of rearrangement chips and provided with a plurality of solder balls in contact with each of the plurality of rearrangement layers to electrically connect the plurality of rearrangement chips to each other; And a wire for electrically connecting the substrate and the plurality of rearrangement chips.

그리고 본 발명의 또 다른 적층형 패키지는, 기판; 상기 기판 상에 다수의 범프를 매개로 전기적으로 연결되며, 재배열층이 마련된 다수의 재배열 칩; 및 상기 다수의 재배열 칩 양측에 각각 결합되며, 상기 다수의 재배열 칩을 서로 전기적으로 연결하기 위하여 상기 다수의 재배열층 각각에 접촉된 다수의 솔더 볼이 마련된 배선 칩을 포함한 것이 바람직하다.And another laminated package of the present invention, the substrate; A plurality of rearrangement chips electrically connected to the plurality of bumps on the substrate and provided with rearrangement layers; And a wiring chip coupled to both sides of the plurality of rearrangement chips and provided with a plurality of solder balls in contact with each of the plurality of rearrangement layers to electrically connect the plurality of rearrangement chips to each other.

여기서, 상기 배선 칩은 웨이퍼 상에 다수의 열로 금속 배선이 마련되고, 상기 금속 배선 상에 서로 이격되게 다수의 솔더 볼이 마련된 것이 바람직하다.Here, the wiring chip may be provided with metal wiring in a plurality of rows on the wafer, and a plurality of solder balls may be provided on the metal wiring to be spaced apart from each other.

또한, 상기 배선 칩은, 웨이퍼 상에 시드 메탈을 증착하는 단계; 상기 시드 메탈 상에 포토 레지스트의 코팅 및 패터닝하는 단계; 상기 포토 레지스트의 패터닝된 부분에 메탈을 도금하는 단계; 상기 메탈이 도금된 부분 이외의 시드 메탈과 포토 레지스트를 에칭하는 단계; 상기 노출된 웨이퍼 상 및 상기 메탈의 일부분이 노출되도록 솔더 마스크를 코팅하는 단계; 및 상기 노출된 메탈 상에 솔더 볼을 형성하는 단계에 의하여 마련된 것이 바람직하다.The wiring chip may further include depositing a seed metal on a wafer; Coating and patterning photoresist on the seed metal; Plating metal on the patterned portion of the photoresist; Etching the seed metal and photoresist other than the metal plated portion; Coating a solder mask to expose a portion of the metal on the exposed wafer; And forming a solder ball on the exposed metal.

이하 첨부된 도면을 참조하면서 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 일 실시예에 따른 적층형 패키지를 나타낸 단면도이다.2 is a cross-sectional view showing a stacked package according to an embodiment of the present invention.

도면을 참조하면, 적층형 패키지(100)는 기판(110)과, 이 기판(100)에 적층된 다수의 재배열 칩(120)과, 다수의 재배열 칩(120) 사이를 전기적으로 연결하기 위한 배선 칩(130) 및 기판(110)과 다수의 재배열 칩(120)을 전기적으로 연결하는 와이어(140)를 포함한다.Referring to the drawings, the stacked package 100 includes a substrate 110, a plurality of rearrangement chips 120 stacked on the substrate 100, and a plurality of rearrangement chips 120 to electrically connect the plurality of rearrangement chips 120. The wire chip 130 and the substrate 110 and a wire 140 for electrically connecting the plurality of rearrangement chip 120.

재배열 칩(120)에는 센터 패드(122)와 연결된 전도성 물질로 된 다수의 재배열층(121)이 에지 부분으로 연장되게 마련된다.The rearrangement chip 120 is provided with a plurality of rearrangement layers 121 made of a conductive material connected to the center pad 122 to extend to the edge portion.

배선 칩(130)은 도 3과 같이 웨이퍼(131) 상에 다수의 열로 금속 배선(134)이 마련되고, 이 금속 배선(134) 상에 일정한 간격으로 다수의 솔더 볼(136)이 마련된다.As shown in FIG. 3, the wiring chip 130 is provided with metal wires 134 in a plurality of rows on the wafer 131, and a plurality of solder balls 136 are provided on the metal wires 134 at regular intervals.

이 배선 칩(130)은 도 4a 내지 도 4f에 도시된 바와 같은 순차적인 공정으로 제조되는데, 먼저 도 4a와 같이 웨이퍼(131) 상에 시드 메탈(132)을 증착한다.The wiring chip 130 is manufactured by a sequential process as shown in FIGS. 4A to 4F. First, the seed metal 132 is deposited on the wafer 131 as shown in FIG. 4A.

다음으로, 도 4b와 같이 이 시드 메탈(132) 상에 포토 레지스트(133)를 코팅한 후, 패터닝을 한다.Next, as shown in FIG. 4B, the photoresist 133 is coated on the seed metal 132 and then patterned.

그런 후, 도 4c와 같이 포토 레지스트(133)의 패터닝에 의하여 외부로 노출된 시드 메탈(132) 상에 Cu, Ni, Au 등의 메탈(134)을 도금한다.Thereafter, as illustrated in FIG. 4C, a metal 134 such as Cu, Ni, Au, or the like is plated on the seed metal 132 exposed to the outside by the patterning of the photoresist 133.

이렇게 메탈(134)이 도금되면, 도 4d와 같이 포토 레지스트(133) 및 이 포토 레지스트(133) 하부의 시드 메탈(132)을 에칭한다.When the metal 134 is plated as described above, the photoresist 133 and the seed metal 132 under the photoresist 133 are etched as shown in FIG. 4D.

다음으로, 도 4e와 같이 메탈(132)의 일부분이 외부로 노출되도록 웨이퍼(131) 상 및 메탈(134) 상부 일부분에 솔더 마스크(135)를 코팅한다.Next, as shown in FIG. 4E, the solder mask 135 is coated on the wafer 131 and the upper portion of the metal 134 so that a portion of the metal 132 is exposed to the outside.

마지막으로, 도 4f와 같이 외부로 노출된 메탈(134) 상에 솔더 볼(136)을 마련한다.Finally, the solder ball 136 is provided on the metal 134 exposed to the outside as shown in FIG. 4F.

이와 같은 공정에 의하여 마련된 배선 칩(130)에서, 솔더 볼(136) 하부의 메탈(134)은 도 3에서의 금속 배선(134)을 일컫는다.In the wiring chip 130 prepared by the above process, the metal 134 under the solder ball 136 refers to the metal wiring 134 in FIG. 3.

이 배선 칩(130)은 기판(110) 상에 적층된 다수의 재배열 칩(120) 양측에 결합하여, 각각의 재배열층(121)과 솔더 볼(136)이 접촉하게 함으로써, 각각의 재배열 칩(120)이 서로 전기적으로 연결되게 한다.The wiring chip 130 is coupled to both sides of the plurality of rearrangement chips 120 stacked on the substrate 110, and the rearrangement layer 121 and the solder balls 136 are in contact with each other. The array chips 120 are electrically connected to each other.

그리고 전기적으로 연결된 다수의 재배열 칩(120)과 기판(110) 사이를 전기적으로 연결하기 위하여 최상부 재배열 칩(120)의 재배열층(121)과 기판(110)을 와이어(140) 본딩하고, EMC(미도시)에 의하여 다수의 재배열 칩(120)과 와이어(140)를 밀봉한다.The wire 140 is bonded to the rearrangement layer 121 and the substrate 110 of the top rearrangement chip 120 to electrically connect the plurality of rearrangement chips 120 and the substrate 110 to be electrically connected. The EMC (not shown) seals the plurality of rearrangement chips 120 and the wires 140.

도 5는 본 발명의 또 다른 실시예를 나타낸 것으로써, 다수의 재배열 칩(120)을 서로 적층하고, 이 적층된 다수의 재배열 칩(120) 양측에 도 3에 도시된 배선 칩(130)을 결합하여 다수의 재배열 칩(120) 사이를 전기적으로 연결하고, 이 배선 칩(130)이 결합된 다수의 재배열 칩(120)을 거꾸로 돌려 재배열층(121)이 아래를 향하도록 한 후, 기판(110) 상에 범프(150)를 매개로 적층한다.5 illustrates another embodiment of the present invention, in which a plurality of rearrangement chips 120 are stacked on each other, and the wiring chip 130 illustrated in FIG. 3 on both sides of the stacked plurality of rearrangement chips 120. ) To electrically connect the plurality of rearrangement chips 120, and turn the plurality of rearrangement chips 120 to which the wiring chip 130 is coupled upside down so that the rearrangement layer 121 faces downward. After that, the bumps 150 are stacked on the substrate 110 via the bumps 150.

즉, 상기 두개의 실시예는 기판(110)과 다수의 재배열 칩(120) 사이를 와이어(140) 본딩 또는 범프(150)로의 연결함에 차이가 있게 된다.That is, the two embodiments have a difference in bonding the wire 140 to the bumps 150 between the substrate 110 and the plurality of rearrangement chips 120.

이와 같은 구성의 적층형 패키지에 의하면, 적층되는 다수의 재배열 칩 사이를 전기적으로 연결하기 위하여 각각의 재배열 칩 사이에 본딩 공간을 형성하지 않아도 되므로 그만큼 두께가 감소하는 장점이 있으며, 따라서 적층되는 재배열 칩의 수도 증가할 수 있어 고용량, 고성능화된 적층형 패키지를 만들 수 있게 되고, 본딩을 개별적으로 하지 않아도 되므로 공정 수율이 향상된다. According to the stacked package having such a configuration, since the bonding space does not have to be formed between the rearranged chips in order to electrically connect the plurality of rearranged chips to be stacked, the thickness is reduced accordingly, and thus the stacked materials are stacked. The number of array chips can also be increased, resulting in higher capacity, higher performance stacked packages, and the need for separate bonding to improve process yield.

미설명 부호 123은 퓨즈 박스이다.Reference numeral 123 is a fuse box.

상술한 바와 같이 본 발명의 적층형 패키지에 의하면, 적층되는 다수의 재배열 칩 사이를 전기적으로 연결하기 위하여 각각의 재배열 칩 사이에 본딩 공간을 형성하지 않아도 되므로 그만큼 두께가 감소하는 장점이 있으며, 따라서 적층되는 재배열 칩의 수도 증가할 수 있어 적층형 패키지의 고용량, 고성능화 및 본딩을 개별적으로 하지 않아도 되므로 공정 수율이 향상되는 효과를 제공한다.As described above, according to the stacked package of the present invention, since the bonding space does not have to be formed between the rearranged chips in order to electrically connect the plurality of rearranged chips to be stacked, the thickness is reduced accordingly. The number of stacked rearranged chips can be increased, thereby increasing the process yield because the high-capacity, high-performance and bonding of the stacked package is not required separately.

본 발명은 상기에 설명되고 도면에 예시된 것에 의해 한정되는 것은 아니며, 다음에 기재되는 청구의 범위 내에서 더 많은 변형 및 변용예가 가능한 것임은 물론이다.It is to be understood that the invention is not limited to that described above and illustrated in the drawings, and that more modifications and variations are possible within the scope of the following claims.

Claims (4)

기판;Board; 상기 기판상에 적층 되며, 에지로 연장된 재배열층을 갖는 다수의 재배열 칩들;A plurality of rearrangement chips stacked on the substrate and having a rearrangement layer extending to an edge; 플레이트 형상으로 상기 각 재배열 칩들에 대하여 수직 하게 배치되고 상기 재배열 칩들의 측면에 배치되며, 상기 각 재배열 칩의 상기 재배열층들과 전기적으로 연결된 솔더 볼 및 상기 솔더 볼들을 전기적으로 연결하는 배선을 포함하는 배선 칩; 및A plate shape disposed vertically with respect to the rearrangement chips and disposed on side surfaces of the rearrangement chips, and electrically connecting the solder balls and the solder balls electrically connected to the rearrangement layers of the rearrangement chips. A wiring chip including wiring; And 상기 기판과 상기 재배열 칩을 전기적으로 연결하는 와이어를 포함하는 것을 특징으로 하는 적층형 패키지.And a wire for electrically connecting the substrate and the rearrangement chip. 기판;Board; 상기 기판 상에 다수의 범프를 매개로 전기적으로 연결되며, 재배열층이 마련된 다수의 재배열 칩; 및A plurality of rearrangement chips electrically connected to the plurality of bumps on the substrate and provided with rearrangement layers; And 플레이트 형상으로 상기 각 재배열 칩들에 대하여 수직 하게 배치되고, 상기 각 재배열 칩의 상기 재배열층들과 전기적으로 연결된 솔더 볼 및 상기 솔더 볼들을 전기적으로 연결하는 배선을 포함하는 배선 칩을 포함하는 것을 특징으로 하는 적층형 패키지.A wiring chip disposed vertically with respect to each of the rearrangement chips in a plate shape, the wiring chip including a solder ball electrically connected to the rearrangement layers of the rearrangement chips, and a wire electrically connecting the solder balls. Stacked package, characterized in that. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 배선 칩의 상기 배선은 웨이퍼 상에 다수의 열로 배치된 것을 특징으로 하는 적층형 패키지.The wiring package of the wiring chip, characterized in that arranged in a plurality of rows on the wafer. 삭제delete
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH118474A (en) 1997-06-16 1999-01-12 Nec Corp Manufacture of multilevel board
KR20030046791A (en) * 2001-12-06 2003-06-18 삼성전자주식회사 Multi chip package using metal bar and manufacturing method thereof
JP2004273525A (en) * 2003-03-05 2004-09-30 Seiko Epson Corp Semiconductor device manufacturing method, semiconductor device, and electronic equipment

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH118474A (en) 1997-06-16 1999-01-12 Nec Corp Manufacture of multilevel board
KR20030046791A (en) * 2001-12-06 2003-06-18 삼성전자주식회사 Multi chip package using metal bar and manufacturing method thereof
JP2004273525A (en) * 2003-03-05 2004-09-30 Seiko Epson Corp Semiconductor device manufacturing method, semiconductor device, and electronic equipment

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