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KR100806061B1 - Power semiconductor module with improved chip protection and improved thermal resistance - Google Patents

Power semiconductor module with improved chip protection and improved thermal resistance Download PDF

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KR100806061B1
KR100806061B1 KR1020020019762A KR20020019762A KR100806061B1 KR 100806061 B1 KR100806061 B1 KR 100806061B1 KR 1020020019762 A KR1020020019762 A KR 1020020019762A KR 20020019762 A KR20020019762 A KR 20020019762A KR 100806061 B1 KR100806061 B1 KR 100806061B1
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lead frame
heat sink
frame pad
insulating heat
semiconductor chip
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KR20030080900A (en
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양귀견
이주상
임을빈
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페어차일드코리아반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

본 발명의 전력용 반도체 모듈은, 절연성 방열판과, 절연성 방열판의 상부 표면에 부착된 리드 프레임 패드와, 리드 프레임 패드 위에서 수직 방향으로 압력을 가하는 지지 핀과, 리드 프레임 패드 위에 부착된 반도체 칩과, 반도체 칩과 전기적으로 연결되어 외부로의 신호 전달 경로로 이용되는 리드, 및 절연성 방열판의 일부, 리드 프레임 패드, 지지 핀, 반도체 칩 및 리드의 일부를 완전히 둘러싸는 몰딩재를 구비하는 것을 특징으로 한다.The power semiconductor module of the present invention includes an insulating heat sink, a lead frame pad attached to an upper surface of the insulating heat sink, a support pin for applying pressure in a vertical direction on the lead frame pad, a semiconductor chip attached to the lead frame pad, And a lead electrically connected to the semiconductor chip and used as a signal transmission path to the outside, and a molding material completely surrounding a portion of the insulating heat sink, a lead frame pad, a support pin, and a portion of the semiconductor chip and the lead. .

Description

칩 손상이 방지되고 열 저항 특성이 개선이 개선된 전력용 반도체 모듈{Power semiconductor module for preventing chip crack and for improving thermal resistance}Power semiconductor module for preventing chip crack and for improving thermal resistance

도 1a는 본 발명에 따른 전력용 반도체 모듈을 나타내 보인 단면도이다.1A is a cross-sectional view illustrating a power semiconductor module according to the present invention.

도 1b는 본 발명에 따른 전력용 반도체 모듈을 나타내 보인 평면도이다.1B is a plan view illustrating a power semiconductor module according to the present invention.

도 2는 본 발명에 따른 전력용 반도체 모듈의 열 저항 특성을 종래의 전력용 반도체 모듈의 열 저항 특성과 비교하기 위하여 나타내 보인 단면도이다.2 is a cross-sectional view illustrating a thermal resistance characteristic of a power semiconductor module according to the present invention with thermal resistance characteristics of a conventional power semiconductor module.

본 발명은 전력용 반도체 모듈에 관한 것으로서, 보다 상세하게는 칩 손상이 방지되고 열 저항 특성이 개선된 전력용 반도체 모듈에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor module, and more particularly, to a power semiconductor module in which chip damage is prevented and thermal resistance characteristics are improved.

일반적인 반도체 패키지는, 한 개 또는 두 개의 반도체 소자를 리드 프레임 위에 부착시킨 후 와이어 본딩 공정 및 에폭시 몰딩 화합물(EMC; Epoxy Molding Compound) 공정을 수행하여 완성된다. 그러나 최근에는 제품의 경박단소 요구에 따라 다수개의 반도체 소자를 실장하여 하나의 패키지로 만듦으로써 공정을 용이하게 수행하고 비용을 감소시키며 제품의 신뢰성을 향상시키고 있다. A general semiconductor package is completed by attaching one or two semiconductor devices onto a lead frame and performing a wire bonding process and an epoxy molding compound (EMC) process. However, in recent years, by mounting a plurality of semiconductor devices in one package according to the light and small requirements of the product to facilitate the process, reduce the cost and improve the reliability of the product.                         

현재 사용되고 있는 전력용 반도체 패키지의 제조를 위해서는, 일 예로서, 먼저 반도체 소자를 웨이퍼에서 분리하는 공정을 수행하고, 이어서 분리된 반도체 소자들을 리드 프레임에 부착시키는 공정을 수행하고, 이어서 부착된 반도체 소자들을 상호 연결시키는 와이어 본딩 공정을 수행하고, 세라믹 방열판이 리드 프레임에 부착되도록 하고 이 리드 프레임을 에폭시 몰딩 화합물이 둘러싸도록 하는 몰딩 공정을 수행하고, 이어서 완제품의 전기적 특성을 검사하는 테스트 공정을 수행한다.In order to manufacture a power semiconductor package that is currently used, as an example, first, a process of separating a semiconductor device from a wafer is performed, and then a process of attaching the separated semiconductor devices to a lead frame is performed. Performing a wire bonding process of interconnecting them, performing a molding process in which a ceramic heat sink is attached to the lead frame, and enclosing the lead frame with an epoxy molding compound, followed by a test process for checking the electrical properties of the finished product. .

이와 같은 제조 공정들 중에서, 특히 세라믹 방열판과 리드 프레임을 부착시켜 외부로의 충격이나 스트레스로부터 패키지를 보호함과 동시에 고절연 내압 및 양호한 외관을 얻기 위한 몰딩 공정은 매우 중요하다. 이와 같은 몰딩 공정은 리드 프레임의 평탄도, 세라믹 방열판의 평탄도 및 강도, 에폭시 몰딩 화합물의 물성 특성, 몰드 금형의 온도 및 작업 조건 등과 같은 환경 변수들이 많이 존재하며, 이와 같은 환경 변수들에 의해 제품의 특성이 결정된다.Among these manufacturing processes, a molding process is particularly important for attaching a ceramic heat sink and a lead frame to protect the package from external shocks and stresses while at the same time obtaining a high insulation withstand voltage and a good appearance. Such molding process has many environmental variables such as flatness of lead frame, flatness and strength of ceramic heat sink, physical properties of epoxy molding compound, temperature and working condition of mold mold, and the like. The characteristics of are determined.

그러나 상기 몰딩 공정을 수행하는 과정에서 리드 프레임과 세라믹 방열판 사이로 에폭시 몰딩 화합물이 침투하여 리드 프레임이 찌그러지거나 구부러지는 현상이 발생하며, 이에 따라 리드 프레임에 부착된 반도체 소자가 깨지는 크랙(crack) 현상이 발생한다는 문제가 있다. 이 외에도, 에폭시 몰딩 화합물이 리드 프레임과 세라믹 방열판 사이로 침투하게 되면, 리드 프레임과 세라믹 방열판 사이의 에폭시 몰딩 화합물에 의해 열 방출이 용이하게 이루어지지 못하여 소자가 동작 중에 손상되는 불량이 발생될 수 있다. 또한 리드 프레임과 세라믹 방열판 사이에 침투된 에폭시 몰딩 화합물 양에 따라 제품의 열 저항값이 변동하므로 제품의 균일성에도 악 영향을 끼친다.However, in the process of performing the molding process, the epoxy molding compound penetrates between the lead frame and the ceramic heat sink, so that the lead frame is crushed or bent. As a result, a crack phenomenon in which the semiconductor device attached to the lead frame is broken may occur. There is a problem that occurs. In addition, when the epoxy molding compound penetrates between the lead frame and the ceramic heat sink, the heat dissipation may not be easily performed by the epoxy molding compound between the lead frame and the ceramic heat sink, which may cause a defect in which the device is damaged during operation. In addition, the thermal resistance value of the product varies according to the amount of epoxy molding compound penetrated between the lead frame and the ceramic heat sink, which adversely affects the uniformity of the product.

본 발명이 이루고자 하는 기술적 과제는, 칩 손상이 방지되고 열 저항 특성이 개선이 개선된 전력용 반도체 모듈을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a power semiconductor module in which chip damage is prevented and thermal resistance is improved.

상기 기술적 과제를 달성하기 위하여, 본 발명에 따른 전력용 반도체 모듈은, 절연성 방열판; 상기 절연성 방열판의 상부 표면에 부착된 리드 프레임 패드; 상기 리드 프레임 패드 위에서 수직 방향으로 압력을 가하는 지지 핀; 상기 리드 프레임 패드 위에 부착된 반도체 칩; 상기 반도체 칩과 전기적으로 연결되어 외부로의 신호 전달 경로로 이용되는 리드; 및 상기 절연성 방열판의 일부, 리드 프레임 패드, 지지 핀, 반도체 칩 및 리드의 일부를 완전히 둘러싸는 몰딩재를 구비하는 것을 특징으로 한다.In order to achieve the above technical problem, the power semiconductor module according to the present invention, the insulating heat sink; A lead frame pad attached to an upper surface of the insulating heat sink; A support pin for applying pressure in the vertical direction on the lead frame pad; A semiconductor chip attached to the lead frame pad; A lead electrically connected to the semiconductor chip and used as a signal transmission path to the outside; And a molding material completely surrounding a part of the insulating heat sink, a lead frame pad, a support pin, a semiconductor chip, and a part of the lead.

상기 리드 프레임 패드와 상기 반도체 칩 사이에서 리드 프레임 패드와 반도체 칩의 부착을 위한 솔더를 더 구비하는 것이 바람직하다.It is preferable to further provide a solder for attaching the lead frame pad and the semiconductor chip between the lead frame pad and the semiconductor chip.

상기 절연성 방열판은 세라믹, Al2O3, AlN, SiO2 또는 BeO 재질로 이루어진 것이 바람직하다.The insulating heat sink is preferably made of ceramic, Al 2 O 3, AlN, SiO 2 or BeO material.

이하 첨부 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서 는 안 된다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

도 1a 및 도 1b는 본 발명에 따른 전력용 반도체 모듈을 나타내 보인 단면도 및 평면도이다.1A and 1B are a cross-sectional view and a plan view showing a power semiconductor module according to the present invention.

도 1a 및 도 1b를 참조하면, 세라믹 방열판과 같은 절연성 방열판(102)의 상부면과 리드 프레임 패드(112)의 하부면이 상호 부착된다. 절연성 방열판(102)은, 세라믹 이외에도, Al2O3, AlN, SiO2 또는 BeO 재질과 같이 절연 특성 및 열 전달 특성이 우수한 재질로 이루어진다. 절연성 방열판(102)의 하부면은 히트 싱크(heat sink)(130)에 부착된다. 리드 프레임 패드(112)는 리드 프레임의 리드(114)와 연결된다. 리드 프레임 패드(112)의 상부 표면 위에는 FRD(Fast Recovery Diode) 및 IGBT(Insulated Gate Bipolar Transistor)와 같은 반도체 칩(104)들이 부착된다. 도면에 나타내지는 않았지만, 리드 프레임 패드(112)와 반도체 칩(104)들 사이에는, 리드 프레임 패드(112)와 반도체 칩(104)의 부착을 위한 솔더(solder)(미도시)가 존재한다. 반도체 칩(104)들 사이는 와이어(110)에 의해 전기적으로 상호 연결된다. 집적 회로와 같은 칩(106)은 리드 프레임의 리드(114) 위에 부착된다. 리드 프레임 패드(112)의 상부 표면에는 적어도 한 개의 지지 핀(support pin)(108)이 배치된다. 도 1a의 단면도에서는 2개의 지지 핀(108)만이 나타나고 있지만, 도 1b의 평면도에는 7개의 지지 핀(108)들이 나타나 있다. 에폭시 몰딩 화합물(EMC)과 같은 몰딩재(120)는 절연성 방열판(102)의 하부 표면을 제외한 부분, 리드 프레임 패드(112), 반도체 칩(104)들, 와이어(110), 집적 회로(106) 및 리드 프레임 리드(114)의 일부를 완전히 덮도록 형성된다. 1A and 1B, an upper surface of an insulating heat sink 102 such as a ceramic heat sink and a lower surface of the lead frame pad 112 are attached to each other. The insulating heat sink 102 is made of a material having excellent insulation characteristics and heat transfer characteristics, such as Al 2 O 3, AlN, SiO 2, or BeO, in addition to ceramics. The bottom surface of the insulating heat sink 102 is attached to a heat sink 130. The lead frame pad 112 is connected to the lead 114 of the lead frame. On the upper surface of the lead frame pad 112, semiconductor chips 104, such as a fast recovery diode (FRD) and an insulated gate bipolar transistor (IGBT), are attached. Although not shown, a solder (not shown) exists between the lead frame pad 112 and the semiconductor chip 104 to attach the lead frame pad 112 and the semiconductor chip 104. The semiconductor chips 104 are electrically interconnected by wires 110. A chip 106, such as an integrated circuit, is attached over the leads 114 of the lead frame. At least one support pin 108 is disposed on the upper surface of the lead frame pad 112. Although only two support pins 108 are shown in the cross-sectional view of FIG. 1A, seven support pins 108 are shown in the top view of FIG. Molding material 120, such as an epoxy molding compound (EMC), may include portions other than the lower surface of insulating heat sink 102, lead frame pads 112, semiconductor chips 104, wires 110, and integrated circuits 106. And a part of the lead frame lead 114 completely.

상기 지지 핀(108)은 몰딩재(120) 내에서 리드 프레임 패드(112)와 절연성 방열판(102)을 압착한다. 이와 같은 지지 핀(108)의 압착력에 의해, 리드 프레임 패드(112)와 절연성 방열판(102) 사이에 빈 공간이 발생하지 않으므로, 몰딩재(120)가 리드 프레임 패드(112)와 절연성 방열판(102) 사이로 침투되지 않는다. 몰딩재(120)가 리드 프레임 패드(112)와 절연성 방열판(102) 사이로 침투되지 않으므로, 리드 프레임 패드(112)가 틀어지거나 구부러지는 현상이 발생하지 않으며, 이에 따라 칩 크랙 현상이 발생하지 않는다. 또한 종래의 전력용 반도체 모듈의 경우, 리드 프레임 패드와 절연성 방열판 사이에 침투된 몰딩재 또는 빈 공간이 존재함으로써 높은 열 저항 특성을 나타내던 것에 비하여, 상기 전력용 반도체 모듈의 경우, 지지 핀(108)의 압착력에 의한 몰딩재 침투 현상 또는 빈 공간 형성 현상이 발생하지 않으므로 낮은 열 저항 특성을 나타낸다.  The support pin 108 compresses the lead frame pad 112 and the insulating heat sink 102 in the molding material 120. Since the pressing force of the support pins 108 does not generate an empty space between the lead frame pad 112 and the insulating heat sink 102, the molding member 120 is formed of the lead frame pad 112 and the insulating heat sink 102. ) Does not penetrate between. Since the molding member 120 does not penetrate between the lead frame pad 112 and the insulating heat sink 102, the lead frame pad 112 is not twisted or bent, and thus no chip crack occurs. In addition, in the case of the conventional power semiconductor module has a high thermal resistance characteristics due to the presence of a molding material or an empty space penetrated between the lead frame pad and the insulating heat sink, in the case of the power semiconductor module, the support pin 108 Since no penetration of the molding material or void formation due to the pressing force of) occurs, it exhibits low heat resistance.

도 2는 본 발명에 따른 전력용 반도체 모듈의 열 저항 특성을 종래의 전력용 반도체 모듈의 열 저항 특성과 비교하기 위하여 나타내 보인 단면도이다. 도 2에서 참조 부호 "210"은 본 발명에 따른 전력용 반도체 모듈을 나타내고, 참조 부호 "220"은 종래의 전력용 반도체 모듈을 나타낸다. 그리고 참조 부호 "16" 및 "120"은 에폭시 몰딩 화합물을 나타낸다.2 is a cross-sectional view illustrating a thermal resistance characteristic of a power semiconductor module according to the present invention with thermal resistance characteristics of a conventional power semiconductor module. In FIG. 2, reference numeral 210 denotes a power semiconductor module according to the present invention, and reference numeral 220 denotes a conventional power semiconductor module. And reference numerals "16" and "120" denote epoxy molding compounds.

도 2를 참조하면, 먼저 종래의 전력용 반도체 모듈(220)의 경우, 반도체 칩(15)으로부터 발생되는 열이 절연성 방열판(11)의 하부 표면으로 방출되는 과정에서의 전체 열 저항은, 반도체 칩(15)의 수직 방향으로 존재하는 열 저항(T11)과, 반도체 칩(15)을 리드 프레임 패드(13)에 부착시키기 위한 솔더(14)의 수직 방향으 로 존재하는 열 저항(T12)과, 리드 프레임 패드(13)의 수직 방향으로 존재하는 열 저항(T13)과, 리드 프레임 패드(13) 및 절연성 방열판(11) 계면에 침투된 에폭시 몰드 화합물 또는 보이드(void)(12)의 수직 방향으로 존재하는 열 저항(T14)과, 그리고 절연성 방열판(11)의 수직 방향으로 존재하는 열 저항(T15)을 모두 합하여 계산된다. 이에 반하여 본 발명에 따른 전력용 반도체 모듈(210)의 경우, 반도체 칩(104)으로부터 발생되는 열이 절연성 방열판(102)의 하부 표면으로 방출되는 과정에서의 전체 열 저항은, 반도체 칩(104)의 수직 방향으로 존재하는 열 저항(T21)과, 반도체 칩(104)을 리드 프레임 패드(112)에 부착시키기 위한 솔더(103)의 수직 방향으로 존재하는 열 저항(T22)과, 리드 프레임 패드(112)의 수직 방향으로 존재하는 열 저항(T23)과, 그리고 절연성 방열판(102)의 수직 방향으로 존재하는 열 저항(T24)을 모두 합하여 계산된다.Referring to FIG. 2, first, in the case of the conventional power semiconductor module 220, the total thermal resistance in a process in which heat generated from the semiconductor chip 15 is discharged to the lower surface of the insulating heat sink 11 is a semiconductor chip. Thermal resistance T 11 existing in the vertical direction of 15 and thermal resistance T 12 existing in the vertical direction of the solder 14 for attaching the semiconductor chip 15 to the lead frame pad 13. And the thermal resistance T 13 existing in the vertical direction of the lead frame pad 13 and the epoxy mold compound or void 12 penetrated into the interface of the lead frame pad 13 and the insulating heat sink 11. The heat resistance T 14 existing in the vertical direction and the heat resistance T 15 existing in the vertical direction of the insulating heat sink 11 are all calculated. In contrast, in the case of the power semiconductor module 210 according to the present invention, the total thermal resistance in the process of dissipating heat generated from the semiconductor chip 104 to the lower surface of the insulating heat sink 102 is the semiconductor chip 104. Thermal resistance (T 21 ) existing in the vertical direction, thermal resistance (T 22 ) existing in the vertical direction of the solder 103 for attaching the semiconductor chip 104 to the lead frame pad 112, and the lead frame The thermal resistance T 23 existing in the vertical direction of the pad 112 and the thermal resistance T 24 existing in the vertical direction of the insulating heat sink 102 are calculated.

이와 같이, 본 발명에 따른 전력용 반도체 모듈(210)의 경우, 종래의 전력용 반도체 모듈(220)의 경우에서 포함되었던 리드 프레임 패드(13) 및 절연성 방열판(11) 계면에 침투된 에폭시 몰드 화합물 또는 보이드(void)(12)의 수직 방향으로 존재하는 열 저항(T14)이 제거되었으므로 전체 열 저항이 감소되며, 결과적으로 반도체 칩(104)으로부터 발생되는 열이 절연성 방열판(102)의 하부 표면 밖으로 더 용이하게 방출된다.As such, in the case of the power semiconductor module 210 according to the present invention, the epoxy mold compound penetrated into the interface of the lead frame pad 13 and the insulating heat sink 11, which were included in the case of the conventional power semiconductor module 220. Or the thermal resistance T 14 existing in the vertical direction of the void 12 is removed, so that the overall thermal resistance is reduced, and as a result, the heat generated from the semiconductor chip 104 is lowered on the lower surface of the insulating heat sink 102. Easier to release out.

실제로 열 저항값을 측정한 결과, 리드 프레임 패드와 절연성 방열판 계면에 에폭시 몰드 화합물이 침투되거나, 또는 보이드가 존재하는 종래의 전력용 반도체 모듈의 열 저항값이 대략 2.3(℃/Watt)의 값을 나타낸 반면, 지지 핀에 의해 리드 프레임 패드와 절연성 방열판이 완전히 밀착된 본 발명에 따른 전력용 반도체 모듈의 열 저항값은 대략 1.5(℃/Watt)의 값을 나타내어 대략 65%의 열 저항 감소 효과를 나타낸다.As a result of measuring the thermal resistance value, the thermal resistance value of the conventional power semiconductor module in which the epoxy mold compound penetrates into the interface between the lead frame pad and the insulating heat sink or voids is approximately 2.3 (° C / Watt). On the other hand, the thermal resistance value of the power semiconductor module according to the present invention, in which the lead frame pad and the insulating heat sink are completely in contact with each other by the support pin, exhibits a value of approximately 1.5 (° C./Watt), thereby reducing the thermal resistance of approximately 65%. Indicates.

이상 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않으며, 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형이 가능함은 당연하다.Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

이상의 설명에서와 같이, 본 발명에 따른 전력용 반도체 모듈에 의하면, 리드 프레임 패드와 절연성 방열판이 지지 핀의 압력에 의해 완전히 밀착되어 계면에 에폭시 몰딩 화합물이 침투되거나 보이드가 형성되는 현상이 방지되므로 리드 프레임 패드의 구부러짐에 의한 반도체 칩의 파손 현상이 발생하지 않으며, 또한 열 저항값이 균일하고도 낮게 나타나 소자의 신뢰성이 향상된다는 이점들을 제공한다.As described above, according to the power semiconductor module according to the present invention, the lead frame pad and the insulating heat sink are completely in contact with the pressure of the support pins to prevent the phenomenon that the epoxy molding compound infiltrates or voids formed at the interface is prevented The breakage of the semiconductor chip due to the bending of the frame pad does not occur, and the thermal resistance value is uniform and low, thereby providing the advantage that the reliability of the device is improved.

Claims (3)

절연성 방열판;Insulating heat sink; 상기 절연성 방열판의 상부 표면에 부착된 리드 프레임 패드;A lead frame pad attached to an upper surface of the insulating heat sink; 상기 리드 프레임 패드 위에서 수직 방향으로 압력을 가하는 지지 핀;A support pin for applying pressure in the vertical direction on the lead frame pad; 상기 리드 프레임 패드 위에 부착된 반도체 칩;A semiconductor chip attached to the lead frame pad; 상기 반도체 칩과 전기적으로 연결되어 외부로의 신호 전달 경로로 이용되는 리드; 및A lead electrically connected to the semiconductor chip and used as a signal transmission path to the outside; And 상기 절연성 방열판의 일부, 리드 프레임 패드, 지지 핀, 반도체 칩 및 리드의 일부를 완전히 둘러싸는 몰딩재를 구비하는 것을 특징으로 하는 전력용 반도체 모듈.And a molding material completely surrounding a part of the insulating heat sink, a lead frame pad, a support pin, a semiconductor chip, and a part of the lead. 제1항에 있어서,The method of claim 1, 상기 리드 프레임 패드와 상기 반도체 칩 사이에서 리드 프레임 패드와 반도체 칩의 부착을 위한 솔더를 더 구비하는 것을 특징으로 하는 전력용 반도체 모듈.And a solder for attaching the lead frame pad and the semiconductor chip between the lead frame pad and the semiconductor chip. 제1항에 있어서,The method of claim 1, 상기 절연성 방열판은 세라믹, Al2O3, AlN, SiO2 또는 BeO 재질로 이루어진 것을 특징으로 하는 전력용 반도체 모듈.The insulating heat sink is a power semiconductor module, characterized in that made of ceramic, Al 2 O 3, AlN, SiO 2 or BeO material.
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