KR100802248B1 - Nonvolatile Semiconductor Memory Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and discloses a technology for dramatically reducing chip size by implementing a cell array of a semiconductor memory device in three dimensions. The present invention includes a unit block cell array in which a plurality of cell arrays including a plurality of unit cells arranged in a row and a column direction are stacked in multiple layers in a vertical direction, and X based on the stacking direction of the plurality of cell arrays. The unit block cell arrays of a specific group unit arranged in the, Y, Z directions form one unit bank cell array, and each unit bank cell array independently performs a read / write operation.

Description

Non-volatile semiconductor memory device

1 is a block diagram of a unit block cell array of a nonvolatile semiconductor memory device according to the present invention;

2 is a configuration diagram of a unit bank cell array of a nonvolatile semiconductor memory device according to the present invention;

3 is a configuration diagram of a plurality of bank cell arrays of a nonvolatile semiconductor memory device according to the present invention;

4 is a layout diagram of the cell array of FIG. 1;

5 and 6 are cross-sectional views of the cell array of FIG.

7 is a cross-sectional configuration diagram of a unit block cell array of FIG. 1.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and is a technology for dramatically reducing chip size by implementing a cell array of a semiconductor memory device in three dimensions.

In general, the nonvolatile ferroelectric memory, or ferroelectric random access memory (FeRAM), has a data processing speed of about DRAM (DRAM) and is attracting attention as a next-generation memory device due to its characteristic that data is preserved even when the power is turned off. have.

The FeRAM is a memory device having a structure almost similar to that of a DRAM, and uses a ferroelectric material as a capacitor material to utilize high residual polarization characteristic of the ferroelectric material. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

Description of the above-described FeRAM has been disclosed in Korean Patent Application No. 2001-57275 filed by the same inventor as the present invention. Therefore, a detailed description of the basic configuration of the FeRAM and its operation will be omitted.

The unit cell of the conventional nonvolatile ferroelectric memory device includes one switching element connecting a sub bit line and a nonvolatile ferroelectric capacitor by switching according to a state of a word line, and one connected between one end of the switching element and a plate line. Of nonvolatile ferroelectric capacitors. Here, the switching element of the conventional nonvolatile ferroelectric memory device mainly uses an NMOS transistor whose switching operation is controlled by a gate control signal.

However, in such a conventional nonvolatile ferroelectric memory device, when the cell size becomes small, the data retention characteristic is deteriorated, which makes normal cell operation difficult. In other words, when a cell read operation, voltage is applied to an adjacent cell, and data is destroyed, thereby causing interface noise between cells. In addition, since a write voltage is applied to an unselected cell during the write operation of the cell, data of the unselected cells is destroyed, thereby making it difficult to perform a random access operation.

In addition, in the conventional MFIS (Metal Ferroelectric Insulator Silicon) and MFMIS (Metal Ferroelectric Metal Insulator Silicon) there is a problem that the data retention characteristics are significantly deteriorated by the depolarization charge.

The present invention has been made to solve the above problems, and has the following object.

First, the purpose is to reduce the chip size by stacking a plurality of unit block cell array arranged in the row and column direction in the vertical direction.

Second, the purpose of the present invention is to improve the operation speed of a cell by performing independent read / write operations by dividing a plurality of unit block cell arrays stacked in a vertical direction in bank units.

A nonvolatile semiconductor memory device of the present invention for achieving the above object includes a unit block cell array in which a plurality of cell arrays including a plurality of unit cells each arranged in a row and column direction are stacked in multiple layers in a vertical direction. The unit block cell array of a specific group unit arranged in the X, Y, and Z directions based on the stacking direction of the plurality of cell arrays constitutes one unit bank cell array, and each unit bank cell array is independently read / write. Characterized in performing the operation.

In addition, the present invention includes a first cell array including a plurality of unit cells each arranged in a row and column direction; One or a plurality of second cell arrays each including a plurality of unit cells arranged in a row and column direction and arranged in a Z direction with respect to the first cell array; A unit block cell array including a first cell array and a plurality of second cell arrays; And a unit bank cell array including one or a plurality of unit block cell arrays, wherein the unit block cell array includes one cell array selected from a first cell array and a plurality of second cell arrays by a vertical address. .

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is a block diagram illustrating a unit block cell array 100 of a nonvolatile semiconductor memory device according to the present invention.

Referring to FIG. 1, one cell array CA1 includes a plurality of row address X regions arranged in a row direction (X-axis direction) and a plurality of column addresses arranged in a column direction (Y-axis direction). The two-dimensional plane structure is formed including the area (Y).

In the unit block cell array 100, a plurality of cell arrays CA1 to CAn are stacked in a vertical direction (Z-axis direction) to form a three-dimensional structure, and the plurality of cell arrays CA1 to CA are formed by a vertical address Z. Select one of the CAn.

Here, an address for selecting a word line in one cell array CA1 is referred to as a row address (X), and an address for selecting a bit line is referred to as a column address (Y). The address for selecting one of the plurality of cell arrays CA1 to CAn is referred to as a vertical address Z.

2 is a block diagram illustrating a unit bank cell array BCA of a nonvolatile semiconductor memory device according to the present invention. Referring to FIG. 2, a plurality of cell arrays CA1 to CAn stacked in a vertical direction constitute one unit block cell array 100, and the plurality of unit block cell arrays 100 are configured as one unit bank cell array BCA. do.

In the exemplary embodiment of the present invention, the plurality of cell arrays CA1 to CAn stacked in the vertical direction are described as one unit block cell array 100, and the plurality of unit block cell arrays 100 are referred to as one unit bank cell array BCA. Explained. However, the present invention is not limited thereto, and the plurality of cell arrays CA1 and CA1 formed on the same layer in the horizontal direction may be formed as one unit bank cell array BCA, and the plurality of unit bank cell arrays BCA may be stacked in the vertical direction. have.

In addition, a plurality of unit bank cell arrays BCAs are arranged in a row and column direction as shown in FIG. 3 to perform an independent read / write operation in each unit bank cell array BCA unit to improve an operation speed of a cell. do.

Although the present invention has been described in the embodiment in which a plurality of unit bank cell arrays BCAs are arranged in row and column directions, the plurality of unit bank cell arrays BCA of the present invention is based on the stacking direction of the plurality of cell arrays CA1 to CAn. It can be arranged in the X, Y, Z direction. In addition, the unit block cell array 100 of a specific group unit forms one unit bank cell array BCA, and each unit bank cell array BCA independently performs a read / write operation.

4 is a layout cross-sectional view of an n-th layer cell array CAn of a nonvolatile semiconductor memory device according to the present invention.

In the present invention, the word line WL and the bottom word line BWL are arranged in parallel in the same direction and provided in plural in the column direction. A plurality of bit lines BL are provided in a direction perpendicular to the word line WL. In addition, a plurality of unit cells C are positioned in an area where a plurality of word lines WL, a plurality of bottom word lines BWL, and a plurality of bit lines BL intersect.

5 is a cross-sectional view of an nth layer cell array CAn of a nonvolatile semiconductor memory device according to the present invention.

FIG. 5 shows a cross-sectional structure of the n-th layer cell array CAn in the direction (A) parallel to the word line WL in the layout sectional view of FIG. 4.

In the n-th layer cell array CAn of the present invention, a plurality of insulating layers 11 are formed on the bottom word line 10, and a plurality of P-type channel regions 12 are formed on the plurality of insulating layers 11. Is formed. The plurality of ferroelectric layers 16 are formed on the plurality of channel regions 12, and the word lines 17 are formed on the plurality of ferroelectric layers 16 in parallel with the bottom word lines 10. Thus, a plurality of cells are connected between one word line WL_1 and one bottom word line BWL_1.

6 illustrates a cross-sectional structure of the n-th layer cell array CAn in the direction (B) perpendicular to the word line WL in the layout cross-sectional view of FIG. 4.

In the nth layer cell array CAn of the present invention, an insulating layer 11 is formed on each of the bottom word lines BWL_1, BWL_2, and BWL_3. In addition, the floating channel layer 15 having the P-type drain region 13, the P-type channel region 12, and the P-type source region 14 connected in series is formed on the insulating layer 11.

Here, the P-type drain region 13 may be used as a source region in an adjacent cell, and the P-type source region 14 may be used as a drain region in an adjacent cell. That is, the P-type region is commonly used as a drain region and a source region in adjacent cells.

In addition, the drain region 13, the source region 14, and the channel region 12 of the floating channel layer 15 are formed in a P-type to be in a floating state. The semiconductor of the floating channel layer 15 may be made of a material such as carbon nanotube, silicon, Ge (germanium), or organic.

In addition, a ferroelectric layer 16 is formed on each channel region 12 of the floating channel layer 15, and word lines WL_1, WL_2, and WL_3 are formed on the ferroelectric layer 16. Here, the bottom word line 10 and the word line 17 are selectively driven by the same row address decoder (not shown).

The present invention having such a configuration reads and writes data using the characteristic that the channel resistance of the floating channel layer 15 varies depending on the polarization state of the ferroelectric layer 16. That is, when the polarity of the ferroelectric layer 16 induces positive charge in the channel region 12, the memory cell is in a high resistance state and the channel is turned off. On the contrary, when the polarity of the ferroelectric layer 16 induces negative charge in the channel region 12, the memory cell is in a low resistance state and the channel is turned on.

7 is a cross-sectional view of a unit block cell array 100 of a nonvolatile semiconductor memory device according to the present invention.

In the unit block cell array 100 illustrated in FIG. 7, the unit cell array CAn of the present invention having the configuration as shown in FIG. 6 is stacked in a multilayer structure. The unit cell arrays CA1 to CAn are separated from each other through the cell insulating layer 18.

In the present invention, the floating channel layer 15 is composed of the P-type drain region 13, the P-type channel region 12 and the P-type source region 14 in the embodiment, but the present invention is not limited thereto. The floating channel layer 15 may be formed of an N-type drain region, an N-type channel region, and an N-type source region.

The high data write / read operation of the nonvolatile semiconductor memory device according to the present invention will be described as follows.

First, in the write operation mode of the data "1", the ground voltage <GND> is applied to the bottom word line 10 and a negative voltage <-V> is applied to the word line 17. At this time, the drain region 13 and the source region 14 are in a ground voltage <GND> state.

In this case, a voltage is applied between the P-type channel region 12 and the ferroelectric layer 16 of the floating channel layer 15 by the voltage distribution of the capacitor between the ferroelectric layer 16 and the insulating layer 11. Accordingly, positive charge is induced in the channel region 12 depending on the polarity of the ferroelectric layer 16, resulting in a low resistance state of the memory cell. Accordingly, data "1" can be written to all cells in the memory in the write operation mode.

On the other hand, the ground voltage <GND> or the positive read voltage <+ Vrd> is applied to the bottom word line 10 in the read operation mode of the data "1". Then, the ground voltage <GND> is applied to the word line 17. At this time, the depletion layer is formed under the channel region 12 by the read voltage <+ Vrd> applied from the bottom word line 10.

In addition, a positive charge is induced on the channel region 12 so that no depletion layer is formed. Accordingly, the channel region 12 is turned on so that current flows from the source region 14 to the drain region 13. Therefore, data "1" stored in the memory cell can be read in the read operation mode. At this time, even if a slight voltage difference is applied to the drain region 13 and the source region 14, a large current flows because the channel region 12 is turned on.

A low data write / read operation of a nonvolatile semiconductor memory device according to the present invention will be described below.

First, in the write operation mode of the data "0", a negative voltage <-V> is applied to the bottom word line 10 and a ground voltage <GND> is applied to the word line 17. Then, a negative voltage <-V> is applied to the drain region 13 and the source region 14.

At this time, a high voltage is formed between the positive voltage <+ V> applied from the word line 17 and the negative voltage <-V> formed in the channel region 12. Accordingly, negative charge is induced in the channel region 12 depending on the polarity of the ferroelectric layer 16, resulting in a high resistance state of the memory cell. Accordingly, data "0" can be written to the memory cell in the write operation mode.

On the other hand, in the read operation mode of the data "0", the ground voltage <GND> or the read voltage <+ Vrd> having a positive value is applied to the bottom word line 10. Then, the ground voltage <GND> is applied to the word line 17.

At this time, the depletion layer is formed under the channel region 12 by the read voltage <+ Vrd> applied from the bottom word line 10. A negative charge is induced on the channel region 12 to form a depletion layer. Accordingly, the channel of the channel region 12 is turned off by the depletion layer formed in the channel region 12 to block the current path from the source region 14 to the drain region 13.

At this time, even if a slight voltage difference is applied between the drain region 13 and the source region 14, a small current flows because the channel region 12 is turned off. Accordingly, data "0" stored in the memory cell can be read in the read operation mode.

Accordingly, since the voltage line is not applied to the ferroelectric layer 16 by controlling the word line 17 and the bottom word line 10 to the ground in the read operation mode, the data retention characteristic of the cell can be improved.

As described above, the present invention provides the following effects.

First, data of a cell is not destroyed during a read operation using a non destructive read out (NDRO) method. Accordingly, the present invention can improve the reliability of the cell during the low voltage operation of the nano-scale ferroelectric cell and improve the read operation speed.

Second, a plurality of ferroelectric unit cell arrays are provided in the row and column directions, and stacked in the vertical direction to improve the integrated capacity of the cell, thereby reducing the overall size of the chip.

Third, a plurality of unit block cell arrays stacked in a vertical direction may be divided into bank units to perform independent read / write operations, thereby improving an operation speed of a cell.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (16)

A plurality of cell arrays including a plurality of unit cells each arranged in a row and column direction includes a unit block cell array stacked in multiple layers in a vertical direction, Unit block cell arrays of a specific group unit arranged in X, Y, and Z directions based on the stacking direction of the plurality of cell arrays form one unit bank cell array, and a plurality of unit bank cell arrays are provided to each unit. A nonvolatile semiconductor memory device characterized by performing independent read / write operations for each bank cell array. The nonvolatile semiconductor memory device of claim 1, wherein the unit block cell array selects one of the plurality of cell arrays by a vertical address. The nonvolatile semiconductor memory device of claim 1, wherein the unit cell comprises a nonvolatile ferroelectric capacitor. The method of claim 1, wherein the unit cell Bottom wordline; An insulating layer formed on the bottom word line; A floating channel layer formed on the insulating layer to maintain a floating state; A ferroelectric layer formed on the floating channel layer to store data; And A word line formed in parallel with the bottom word line on the ferroelectric layer, And read / write control the data by inducing different channel resistances in the channel region of the floating channel layer according to the polarity of the ferroelectric layer. The nonvolatile semiconductor memory device of claim 4, wherein the floating channel layer comprises at least one of carbon nanotubes, silicon, germanium, and an organic semiconductor. 5. The method of claim 4, wherein the floating channel layer comprises a P-type channel region formed on the insulating layer to maintain a floating state, and a P-type drain region and a P-type source region connected to both sides of the channel region. Non-volatile semiconductor memory device characterized in that. The method of claim 1, wherein each of the plurality of cell arrays A plurality of bottom word lines; An insulation layer formed on the bottom word lines; A floating channel layer formed on the insulating layer and having a plurality of P-type channel regions and a plurality of P-type drain and source regions alternately connected in series with the plurality of P-type channel regions; A ferroelectric layer formed on the floating channel layer; And A plurality of word lines formed in parallel with the plurality of bottom word lines on the ferroelectric layer, And a read / write control of a plurality of data by inducing different channel resistances to the plurality of P-type channel regions according to the polarity of the ferroelectric layer. The nonvolatile semiconductor memory device of claim 1, further comprising a cell insulating layer formed between the plurality of cell arrays to separate the plurality of cell arrays from each other. 9. A first cell array including a plurality of unit cells each arranged in a row and column direction; One or more second cell arrays each including a plurality of unit cells arranged in a row and column direction and arranged in a Z direction with respect to the first cell array; A unit block cell array including the first cell array and the plurality of second cell arrays; And A unit bank cell array including one or a plurality of unit block cell arrays, The unit block cell array of claim 1, wherein one cell array of the first cell array and the plurality of second cell arrays is selected by a vertical address. 10. The method of claim 9, wherein the unit block cell array of a specific group unit arranged in the X, Y, Z directions constitutes one unit bank cell array, and a plurality of unit bank cell arrays are provided to be independent of each unit bank cell array. A nonvolatile semiconductor memory device, characterized in that to perform an in read / write operation. 10. The nonvolatile semiconductor memory device of claim 9, wherein the unit cell comprises a nonvolatile ferroelectric capacitor. The method of claim 9, wherein the unit cell Bottom wordline; An insulating layer formed on the bottom word line; A floating channel layer formed on the insulating layer to maintain a floating state; A ferroelectric layer formed on the floating channel layer to store data; And A word line formed in parallel with the bottom word line on the ferroelectric layer, And read / write control the data by inducing different channel resistances in the channel region of the floating channel layer according to the polarity of the ferroelectric layer. The nonvolatile semiconductor memory device of claim 12, wherein the floating channel layer is formed of at least one of carbon nanotubes, silicon, germanium, and an organic semiconductor. 13. The method of claim 12, wherein the floating channel layer comprises a P-type channel region formed on top of the insulating layer to maintain a floating state, and a P-type drain region and a P-type source region connected to both sides of the channel region. Non-volatile semiconductor memory device characterized in that. The method of claim 9, wherein the first cell array and each of the plurality of second cell arrays A plurality of bottom word lines; An insulation layer formed on the bottom word lines; A floating channel layer formed on the insulating layer and having a plurality of P-type channel regions and a plurality of P-type drain and source regions alternately connected in series with the plurality of P-type channel regions; A ferroelectric layer formed on the floating channel layer; And A plurality of word lines formed in parallel with the plurality of bottom word lines on the ferroelectric layer, And a read / write control of a plurality of data by inducing different channel resistances to the plurality of P-type channel regions according to the polarity of the ferroelectric layer. 16. The nonvolatile semiconductor memory of claim 9 or 15, further comprising a cell insulating layer formed between each of the first cell array and the plurality of second cell arrays to separate the cell arrays from each other. Device.

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